1 | /**************************************************************************//**
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2 | * @file mmu_Renesas_RZ_A1.c
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3 | * @brief MMU Startup File for
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4 | * mmu_Renesas_RZ_A1 Device Series
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5 | * @version V1.01
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6 | * @date 2 Aug 2013
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7 | *
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8 | * @note
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9 | *
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10 | ******************************************************************************/
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11 | /* Copyright (c) 2011 - 2013 ARM LIMITED
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12 |
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13 | All rights reserved.
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14 | Redistribution and use in source and binary forms, with or without
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15 | modification, are permitted provided that the following conditions are met:
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16 | - Redistributions of source code must retain the above copyright
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17 | notice, this list of conditions and the following disclaimer.
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18 | - Redistributions in binary form must reproduce the above copyright
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19 | notice, this list of conditions and the following disclaimer in the
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20 | documentation and/or other materials provided with the distribution.
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21 | - Neither the name of ARM nor the names of its contributors may be used
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22 | to endorse or promote products derived from this software without
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23 | specific prior written permission.
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24 | *
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25 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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26 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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28 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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29 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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31 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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32 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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33 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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34 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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35 | POSSIBILITY OF SUCH DAMAGE.
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36 | ---------------------------------------------------------------------------*/
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37 |
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38 |
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39 | #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
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40 | #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
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41 | #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
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42 | #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
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43 | // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
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44 | // Write-Through support *not* available
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45 | // Write-Back support available.
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46 | // Read allocation support available.
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47 | // Write allocation support available.
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48 |
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49 | //Note: You should use the Shareable attribute carefully.
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50 | //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
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51 | //CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
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52 | //Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
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53 |
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54 | //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
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55 | //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
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56 | //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
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57 |
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58 |
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59 | //Following MMU configuration is expected
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60 | //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
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61 | //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
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62 | //Domain 0 is always the Client domain
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63 | //Descriptors place all memory in domain 0
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64 | //There are no restrictions by privilege level (PL0 can access all memory)
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65 |
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66 | #include <stdint.h>
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67 | #include "MBRZA1H.h"
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68 |
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69 | //Import symbols from linker
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70 | extern uint32_t Image$$VECTORS$$Base;
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71 | extern uint32_t Image$$RO_DATA$$Base;
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72 | extern uint32_t Image$$RW_DATA$$Base;
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73 | extern uint32_t Image$$ZI_DATA$$Base;
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74 | extern uint32_t Image$$CMD_AREA$$Base;
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75 | extern uint32_t Image$$TTB$$ZI$$Base;
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76 | #if defined( __CC_ARM )
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77 | #else
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78 | extern uint32_t Image$$RW_DATA_NC$$Base;
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79 | extern uint32_t Image$$ZI_DATA_NC$$Base;
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80 | #endif
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81 |
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82 | extern uint32_t Image$$VECTORS$$Limit;
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83 | extern uint32_t Image$$RO_DATA$$Limit;
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84 | extern uint32_t Image$$RW_DATA$$Limit;
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85 | extern uint32_t Image$$ZI_DATA$$Limit;
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86 | extern uint32_t Image$$CMD_AREA$$Limit;
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87 | #if defined( __CC_ARM )
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88 | #else
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89 | extern uint32_t Image$$RW_DATA_NC$$Limit;
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90 | extern uint32_t Image$$ZI_DATA_NC$$Limit;
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91 | #endif
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92 |
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93 | #define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
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94 | #define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
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95 | #define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
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96 | #define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
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97 | #define CMD_AREA_SIZE (((uint32_t)&Image$$CMD_AREA$$Limit >> 20) - ((uint32_t)&Image$$CMD_AREA$$Base >> 20) + 1)
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98 | #if defined( __CC_ARM )
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99 | #else
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100 | #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
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101 | #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
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102 | #endif
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103 |
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104 | static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
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105 | static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
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106 | static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
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107 | static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
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108 | static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
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109 | static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
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110 | static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
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111 |
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112 | /* Define global descriptors */
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113 | static uint32_t Page_L1_4k = 0x0; //generic
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114 | static uint32_t Page_L1_64k = 0x0; //generic
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115 | static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
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116 | static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
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117 |
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118 | void create_translation_table(void)
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119 | {
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120 | mmu_region_attributes_Type region;
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121 |
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122 | /*
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123 | * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
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124 | *
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125 | */
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126 | //Create descriptors for Vectors, RO, RW, ZI sections
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127 | section_normal(Sect_Normal, region);
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128 | section_normal_cod(Sect_Normal_Cod, region);
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129 | section_normal_ro(Sect_Normal_RO, region);
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130 | section_normal_rw(Sect_Normal_RW, region);
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131 | //Create descriptors for peripherals
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132 | section_device_ro(Sect_Device_RO, region);
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133 | section_device_rw(Sect_Device_RW, region);
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134 | section_normal_nc(Sect_Normal_NC, region);
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135 | //Create descriptors for 64k pages
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136 | page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
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137 | //Create descriptors for 4k pages
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138 | page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
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139 |
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140 | /*
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141 | * Define MMU flat-map regions and attributes
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142 | *
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143 | */
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144 |
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145 | //Create 4GB of faulting entries
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146 | __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
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147 |
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148 | // R7S72100 memory map.
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149 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
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150 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
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151 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
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152 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
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153 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
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154 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
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155 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
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156 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
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157 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
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158 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
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159 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
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160 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
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161 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
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162 |
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163 | //Define Image
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164 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
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165 | __TTSection (&Image$$TTB$$ZI$$Base, 0x18200000, (0x18800000 >> 20) - (0x18200000 >> 20) + 1, Sect_Normal_Cod);
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166 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
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167 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
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168 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
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169 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$CMD_AREA$$Base, CMD_AREA_SIZE, Sect_Normal);
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170 | #if defined( __CC_ARM )
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171 | __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
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172 | #else
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173 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
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174 | __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
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175 | #endif
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176 |
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177 | /* Set location of level 1 page table
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178 | ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
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179 | ; 13:7 - 0x0
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180 | ; 6 - IRGN[0] 0x0 (Inner WB WA)
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181 | ; 5 - NOS 0x0 (Non-shared)
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182 | ; 4:3 - RGN 0x1 (Outer WB WA)
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183 | ; 2 - IMP 0x0 (Implementation Defined)
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184 | ; 1 - S 0x0 (Non-shared)
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185 | ; 0 - IRGN[1] 0x1 (Inner WB WA) */
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186 | __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
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187 |
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188 | /* Set up domain access control register
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189 | ; We set domain 0 to Client and all other domains to No Access.
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190 | ; All translation table entries specify domain 0 */
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191 | __set_DACR(1);
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192 | }
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193 |
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194 |
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195 | /*----------------------------------------------------------------------------
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196 | * end of file
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197 | *---------------------------------------------------------------------------*/
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