1 | /*******************************************************************************
|
---|
2 | * DISCLAIMER
|
---|
3 | * This software is supplied by Renesas Electronics Corporation and is only
|
---|
4 | * intended for use with Renesas products. No other uses are authorized. This
|
---|
5 | * software is owned by Renesas Electronics Corporation and is protected under
|
---|
6 | * all applicable laws, including copyright laws.
|
---|
7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
---|
8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
---|
9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
---|
10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
---|
11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
---|
12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
---|
13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
---|
14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
---|
15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
---|
16 | * Renesas reserves the right, without notice, to make changes to this software
|
---|
17 | * and to discontinue the availability of this software. By using this software,
|
---|
18 | * you agree to the additional terms and conditions found by accessing the
|
---|
19 | * following link:
|
---|
20 | * http://www.renesas.com/disclaimer*
|
---|
21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
|
---|
22 | *******************************************************************************/
|
---|
23 | /*******************************************************************************
|
---|
24 | * File Name : spibsc_iodefine.h
|
---|
25 | * $Rev: $
|
---|
26 | * $Date:: $
|
---|
27 | * Description : Definition of I/O Register (V1.00a)
|
---|
28 | ******************************************************************************/
|
---|
29 | #ifndef SPIBSC_IODEFINE_H
|
---|
30 | #define SPIBSC_IODEFINE_H
|
---|
31 | /* ->SEC M1.10.1 : Not magic number */
|
---|
32 |
|
---|
33 | struct st_spibsc
|
---|
34 | { /* SPIBSC */
|
---|
35 | volatile uint32_t CMNCR; /* CMNCR */
|
---|
36 | volatile uint32_t SSLDR; /* SSLDR */
|
---|
37 | volatile uint32_t SPBCR; /* SPBCR */
|
---|
38 | volatile uint32_t DRCR; /* DRCR */
|
---|
39 | volatile uint32_t DRCMR; /* DRCMR */
|
---|
40 | volatile uint32_t DREAR; /* DREAR */
|
---|
41 | volatile uint32_t DROPR; /* DROPR */
|
---|
42 | volatile uint32_t DRENR; /* DRENR */
|
---|
43 | volatile uint32_t SMCR; /* SMCR */
|
---|
44 | volatile uint32_t SMCMR; /* SMCMR */
|
---|
45 | volatile uint32_t SMADR; /* SMADR */
|
---|
46 | volatile uint32_t SMOPR; /* SMOPR */
|
---|
47 | volatile uint32_t SMENR; /* SMENR */
|
---|
48 | volatile uint8_t dummy1[4]; /* */
|
---|
49 | union iodefine_reg32_t SMRDR0; /* SMRDR0 */
|
---|
50 | union iodefine_reg32_t SMRDR1; /* SMRDR1 */
|
---|
51 | union iodefine_reg32_t SMWDR0; /* SMWDR0 */
|
---|
52 | union iodefine_reg32_t SMWDR1; /* SMWDR1 */
|
---|
53 |
|
---|
54 | volatile uint32_t CMNSR; /* CMNSR */
|
---|
55 | volatile uint8_t dummy2[12]; /* */
|
---|
56 | volatile uint32_t DRDMCR; /* DRDMCR */
|
---|
57 | volatile uint32_t DRDRENR; /* DRDRENR */
|
---|
58 | volatile uint32_t SMDMCR; /* SMDMCR */
|
---|
59 | volatile uint32_t SMDRENR; /* SMDRENR */
|
---|
60 | };
|
---|
61 |
|
---|
62 |
|
---|
63 | #define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
|
---|
64 | #define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
|
---|
65 |
|
---|
66 |
|
---|
67 | /* Start of channnel array defines of SPIBSC */
|
---|
68 |
|
---|
69 | /* Channnel array defines of SPIBSC */
|
---|
70 | /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
|
---|
71 | #define SPIBSC_COUNT 2
|
---|
72 | #define SPIBSC_ADDRESS_LIST \
|
---|
73 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
74 | &SPIBSC0, &SPIBSC1 \
|
---|
75 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
76 |
|
---|
77 | /* End of channnel array defines of SPIBSC */
|
---|
78 |
|
---|
79 |
|
---|
80 | #define CMNCR_0 SPIBSC0.CMNCR
|
---|
81 | #define SSLDR_0 SPIBSC0.SSLDR
|
---|
82 | #define SPBCR_0 SPIBSC0.SPBCR
|
---|
83 | #define DRCR_0 SPIBSC0.DRCR
|
---|
84 | #define DRCMR_0 SPIBSC0.DRCMR
|
---|
85 | #define DREAR_0 SPIBSC0.DREAR
|
---|
86 | #define DROPR_0 SPIBSC0.DROPR
|
---|
87 | #define DRENR_0 SPIBSC0.DRENR
|
---|
88 | #define SMCR_0 SPIBSC0.SMCR
|
---|
89 | #define SMCMR_0 SPIBSC0.SMCMR
|
---|
90 | #define SMADR_0 SPIBSC0.SMADR
|
---|
91 | #define SMOPR_0 SPIBSC0.SMOPR
|
---|
92 | #define SMENR_0 SPIBSC0.SMENR
|
---|
93 | #define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
|
---|
94 | #define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
|
---|
95 | #define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
|
---|
96 | #define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
|
---|
97 | #define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
|
---|
98 | #define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
|
---|
99 | #define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
|
---|
100 | #define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
|
---|
101 | #define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
|
---|
102 | #define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
|
---|
103 | #define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
|
---|
104 | #define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
|
---|
105 | #define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
|
---|
106 | #define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
|
---|
107 | #define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
|
---|
108 | #define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
|
---|
109 | #define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
|
---|
110 | #define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
|
---|
111 | #define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
|
---|
112 | #define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
|
---|
113 | #define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
|
---|
114 | #define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
|
---|
115 | #define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
|
---|
116 | #define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
|
---|
117 | #define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
|
---|
118 | #define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
|
---|
119 | #define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
|
---|
120 | #define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
|
---|
121 | #define CMNSR_0 SPIBSC0.CMNSR
|
---|
122 | #define DRDMCR_0 SPIBSC0.DRDMCR
|
---|
123 | #define DRDRENR_0 SPIBSC0.DRDRENR
|
---|
124 | #define SMDMCR_0 SPIBSC0.SMDMCR
|
---|
125 | #define SMDRENR_0 SPIBSC0.SMDRENR
|
---|
126 | #define CMNCR_1 SPIBSC1.CMNCR
|
---|
127 | #define SSLDR_1 SPIBSC1.SSLDR
|
---|
128 | #define SPBCR_1 SPIBSC1.SPBCR
|
---|
129 | #define DRCR_1 SPIBSC1.DRCR
|
---|
130 | #define DRCMR_1 SPIBSC1.DRCMR
|
---|
131 | #define DREAR_1 SPIBSC1.DREAR
|
---|
132 | #define DROPR_1 SPIBSC1.DROPR
|
---|
133 | #define DRENR_1 SPIBSC1.DRENR
|
---|
134 | #define SMCR_1 SPIBSC1.SMCR
|
---|
135 | #define SMCMR_1 SPIBSC1.SMCMR
|
---|
136 | #define SMADR_1 SPIBSC1.SMADR
|
---|
137 | #define SMOPR_1 SPIBSC1.SMOPR
|
---|
138 | #define SMENR_1 SPIBSC1.SMENR
|
---|
139 | #define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
|
---|
140 | #define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
|
---|
141 | #define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
|
---|
142 | #define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
|
---|
143 | #define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
|
---|
144 | #define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
|
---|
145 | #define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
|
---|
146 | #define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
|
---|
147 | #define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
|
---|
148 | #define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
|
---|
149 | #define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
|
---|
150 | #define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
|
---|
151 | #define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
|
---|
152 | #define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
|
---|
153 | #define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
|
---|
154 | #define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
|
---|
155 | #define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
|
---|
156 | #define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
|
---|
157 | #define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
|
---|
158 | #define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
|
---|
159 | #define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
|
---|
160 | #define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
|
---|
161 | #define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
|
---|
162 | #define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
|
---|
163 | #define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
|
---|
164 | #define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
|
---|
165 | #define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
|
---|
166 | #define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
|
---|
167 | #define CMNSR_1 SPIBSC1.CMNSR
|
---|
168 | #define DRDMCR_1 SPIBSC1.DRDMCR
|
---|
169 | #define DRDRENR_1 SPIBSC1.DRDRENR
|
---|
170 | #define SMDMCR_1 SPIBSC1.SMDMCR
|
---|
171 | #define SMDRENR_1 SPIBSC1.SMDRENR
|
---|
172 | /* <-SEC M1.10.1 */
|
---|
173 | #endif
|
---|