1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : scim_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register (V1.00a)
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28 | ******************************************************************************/
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29 | #ifndef SCIM_IODEFINE_H
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30 | #define SCIM_IODEFINE_H
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31 | /* ->SEC M1.10.1 : Not magic number */
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32 |
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33 | struct st_scim
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34 | { /* SCIM */
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35 | volatile uint8_t SMR; /* SMR */
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36 | volatile uint8_t BRR; /* BRR */
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37 | volatile uint8_t SCR; /* SCR */
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38 | volatile uint8_t TDR; /* TDR */
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39 | volatile uint8_t SSR; /* SSR */
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40 | volatile uint8_t RDR; /* RDR */
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41 | volatile uint8_t SCMR; /* SCMR */
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42 | volatile uint8_t SEMR; /* SEMR */
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43 | volatile uint8_t SNFR; /* SNFR */
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44 | volatile uint8_t dummy1[4]; /* */
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45 | volatile uint8_t SECR; /* SECR */
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46 | };
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47 |
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48 |
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49 | #define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
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50 | #define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
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51 |
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52 |
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53 | /* Start of channnel array defines of SCIM */
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54 |
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55 | /* Channnel array defines of SCIM */
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56 | /*(Sample) value = SCIM[ channel ]->SMR; */
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57 | #define SCIM_COUNT 2
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58 | #define SCIM_ADDRESS_LIST \
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59 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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60 | &SCIM0, &SCIM1 \
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61 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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62 |
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63 | /* End of channnel array defines of SCIM */
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64 |
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65 |
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66 | #define SMR0 SCIM0.SMR
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67 | #define BRR0 SCIM0.BRR
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68 | #define SCR0 SCIM0.SCR
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69 | #define TDR0 SCIM0.TDR
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70 | #define SSR0 SCIM0.SSR
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71 | #define RDR0 SCIM0.RDR
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72 | #define SCMR0 SCIM0.SCMR
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73 | #define SEMR0 SCIM0.SEMR
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74 | #define SNFR0 SCIM0.SNFR
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75 | #define SECR0 SCIM0.SECR
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76 | #define SMR1 SCIM1.SMR
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77 | #define BRR1 SCIM1.BRR
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78 | #define SCR1 SCIM1.SCR
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79 | #define TDR1 SCIM1.TDR
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80 | #define SSR1 SCIM1.SSR
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81 | #define RDR1 SCIM1.RDR
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82 | #define SCMR1 SCIM1.SCMR
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83 | #define SEMR1 SCIM1.SEMR
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84 | #define SNFR1 SCIM1.SNFR
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85 | #define SECR1 SCIM1.SECR
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86 | /* <-SEC M1.10.1 */
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87 | #endif
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