source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h@ 270

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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : l2c_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef L2C_IODEFINE_H
30#define L2C_IODEFINE_H
31/* ->SEC M1.10.1 : Not magic number */
32
33struct st_l2c
34{ /* L2C */
35 volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
36 volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
37 volatile uint8_t dummy8[248]; /* */
38 volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
39 volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
40 volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
41 volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
42 volatile uint8_t dummy9[240]; /* */
43 volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
44 volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
45 volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
46 volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
47 volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
48 volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
49 volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
50 volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
51 volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
52 volatile uint8_t dummy10[1292]; /* */
53 volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
54 volatile uint8_t dummy11[60]; /* */
55 volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
56 volatile uint8_t dummy12[8]; /* */
57 volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
58 volatile uint8_t dummy13[48]; /* */
59 volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
60 volatile uint8_t dummy14[4]; /* */
61 volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
62 volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
63 volatile uint8_t dummy15[48]; /* */
64 volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
65 volatile uint8_t dummy16[4]; /* */
66 volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
67 volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
68 volatile uint8_t dummy17[256]; /* */
69/* start of struct st_l2c_from_reg9_d_lockdown0 */
70 volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
71 volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
72/* end of struct st_l2c_from_reg9_d_lockdown0 */
73/* start of struct st_l2c_from_reg9_d_lockdown0 */
74 volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
75 volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
76/* end of struct st_l2c_from_reg9_d_lockdown0 */
77/* start of struct st_l2c_from_reg9_d_lockdown0 */
78 volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
79 volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
80/* end of struct st_l2c_from_reg9_d_lockdown0 */
81/* start of struct st_l2c_from_reg9_d_lockdown0 */
82 volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
83 volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
84/* end of struct st_l2c_from_reg9_d_lockdown0 */
85/* start of struct st_l2c_from_reg9_d_lockdown0 */
86 volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
87 volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
88/* end of struct st_l2c_from_reg9_d_lockdown0 */
89/* start of struct st_l2c_from_reg9_d_lockdown0 */
90 volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
91 volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
92/* end of struct st_l2c_from_reg9_d_lockdown0 */
93/* start of struct st_l2c_from_reg9_d_lockdown0 */
94 volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
95 volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
96/* end of struct st_l2c_from_reg9_d_lockdown0 */
97/* start of struct st_l2c_from_reg9_d_lockdown0 */
98 volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
99 volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
100/* end of struct st_l2c_from_reg9_d_lockdown0 */
101 volatile uint8_t dummy18[16]; /* */
102 volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
103 volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
104 volatile uint8_t dummy19[680]; /* */
105 volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
106 volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
107 volatile uint8_t dummy20[824]; /* */
108 volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
109 volatile uint8_t dummy21[28]; /* */
110 volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
111 volatile uint8_t dummy22[28]; /* */
112 volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
113};
114
115
116struct st_l2c_from_reg9_d_lockdown0
117{
118 volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
119 volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
120};
121
122
123#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
124
125
126/* Start of channnel array defines of L2C */
127
128/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
129/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
130#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8
131#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
132{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
133 &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
134} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
135#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
136#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
137#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
138#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
139#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
140#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
141#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
142#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
143
144/* End of channnel array defines of L2C */
145
146
147#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
148#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
149#define L2CREG1_CONTROL L2C.REG1_CONTROL
150#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
151#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
152#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
153#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
154#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
155#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
156#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
157#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
158#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
159#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
160#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
161#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
162#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
163#define L2CREG7_INV_PA L2C.REG7_INV_PA
164#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
165#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
166#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
167#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
168#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
169#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
170#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
171#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
172#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
173#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
174#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
175#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
176#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
177#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
178#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
179#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
180#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
181#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
182#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
183#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
184#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
185#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
186#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
187#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
188#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
189#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
190#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
191#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
192#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
193#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
194/* <-SEC M1.10.1 */
195#endif
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