source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h@ 270

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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : dmac_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef DMAC_IODEFINE_H
30#define DMAC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->SEC M1.10.1 : Not magic number */
33
34struct st_dmac
35{ /* DMAC */
36/* start of struct st_dmac_n */
37 volatile uint32_t N0SA_0; /* N0SA_0 */
38 volatile uint32_t N0DA_0; /* N0DA_0 */
39 volatile uint32_t N0TB_0; /* N0TB_0 */
40 volatile uint32_t N1SA_0; /* N1SA_0 */
41 volatile uint32_t N1DA_0; /* N1DA_0 */
42 volatile uint32_t N1TB_0; /* N1TB_0 */
43 volatile uint32_t CRSA_0; /* CRSA_0 */
44 volatile uint32_t CRDA_0; /* CRDA_0 */
45 volatile uint32_t CRTB_0; /* CRTB_0 */
46 volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
47 volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
48 volatile uint32_t CHCFG_0; /* CHCFG_0 */
49 volatile uint32_t CHITVL_0; /* CHITVL_0 */
50 volatile uint32_t CHEXT_0; /* CHEXT_0 */
51 volatile uint32_t NXLA_0; /* NXLA_0 */
52 volatile uint32_t CRLA_0; /* CRLA_0 */
53/* end of struct st_dmac_n */
54/* start of struct st_dmac_n */
55 volatile uint32_t N0SA_1; /* N0SA_1 */
56 volatile uint32_t N0DA_1; /* N0DA_1 */
57 volatile uint32_t N0TB_1; /* N0TB_1 */
58 volatile uint32_t N1SA_1; /* N1SA_1 */
59 volatile uint32_t N1DA_1; /* N1DA_1 */
60 volatile uint32_t N1TB_1; /* N1TB_1 */
61 volatile uint32_t CRSA_1; /* CRSA_1 */
62 volatile uint32_t CRDA_1; /* CRDA_1 */
63 volatile uint32_t CRTB_1; /* CRTB_1 */
64 volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
65 volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
66 volatile uint32_t CHCFG_1; /* CHCFG_1 */
67 volatile uint32_t CHITVL_1; /* CHITVL_1 */
68 volatile uint32_t CHEXT_1; /* CHEXT_1 */
69 volatile uint32_t NXLA_1; /* NXLA_1 */
70 volatile uint32_t CRLA_1; /* CRLA_1 */
71/* end of struct st_dmac_n */
72/* start of struct st_dmac_n */
73 volatile uint32_t N0SA_2; /* N0SA_2 */
74 volatile uint32_t N0DA_2; /* N0DA_2 */
75 volatile uint32_t N0TB_2; /* N0TB_2 */
76 volatile uint32_t N1SA_2; /* N1SA_2 */
77 volatile uint32_t N1DA_2; /* N1DA_2 */
78 volatile uint32_t N1TB_2; /* N1TB_2 */
79 volatile uint32_t CRSA_2; /* CRSA_2 */
80 volatile uint32_t CRDA_2; /* CRDA_2 */
81 volatile uint32_t CRTB_2; /* CRTB_2 */
82 volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
83 volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
84 volatile uint32_t CHCFG_2; /* CHCFG_2 */
85 volatile uint32_t CHITVL_2; /* CHITVL_2 */
86 volatile uint32_t CHEXT_2; /* CHEXT_2 */
87 volatile uint32_t NXLA_2; /* NXLA_2 */
88 volatile uint32_t CRLA_2; /* CRLA_2 */
89/* end of struct st_dmac_n */
90/* start of struct st_dmac_n */
91 volatile uint32_t N0SA_3; /* N0SA_3 */
92 volatile uint32_t N0DA_3; /* N0DA_3 */
93 volatile uint32_t N0TB_3; /* N0TB_3 */
94 volatile uint32_t N1SA_3; /* N1SA_3 */
95 volatile uint32_t N1DA_3; /* N1DA_3 */
96 volatile uint32_t N1TB_3; /* N1TB_3 */
97 volatile uint32_t CRSA_3; /* CRSA_3 */
98 volatile uint32_t CRDA_3; /* CRDA_3 */
99 volatile uint32_t CRTB_3; /* CRTB_3 */
100 volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
101 volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
102 volatile uint32_t CHCFG_3; /* CHCFG_3 */
103 volatile uint32_t CHITVL_3; /* CHITVL_3 */
104 volatile uint32_t CHEXT_3; /* CHEXT_3 */
105 volatile uint32_t NXLA_3; /* NXLA_3 */
106 volatile uint32_t CRLA_3; /* CRLA_3 */
107/* end of struct st_dmac_n */
108/* start of struct st_dmac_n */
109 volatile uint32_t N0SA_4; /* N0SA_4 */
110 volatile uint32_t N0DA_4; /* N0DA_4 */
111 volatile uint32_t N0TB_4; /* N0TB_4 */
112 volatile uint32_t N1SA_4; /* N1SA_4 */
113 volatile uint32_t N1DA_4; /* N1DA_4 */
114 volatile uint32_t N1TB_4; /* N1TB_4 */
115 volatile uint32_t CRSA_4; /* CRSA_4 */
116 volatile uint32_t CRDA_4; /* CRDA_4 */
117 volatile uint32_t CRTB_4; /* CRTB_4 */
118 volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
119 volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
120 volatile uint32_t CHCFG_4; /* CHCFG_4 */
121 volatile uint32_t CHITVL_4; /* CHITVL_4 */
122 volatile uint32_t CHEXT_4; /* CHEXT_4 */
123 volatile uint32_t NXLA_4; /* NXLA_4 */
124 volatile uint32_t CRLA_4; /* CRLA_4 */
125/* end of struct st_dmac_n */
126/* start of struct st_dmac_n */
127 volatile uint32_t N0SA_5; /* N0SA_5 */
128 volatile uint32_t N0DA_5; /* N0DA_5 */
129 volatile uint32_t N0TB_5; /* N0TB_5 */
130 volatile uint32_t N1SA_5; /* N1SA_5 */
131 volatile uint32_t N1DA_5; /* N1DA_5 */
132 volatile uint32_t N1TB_5; /* N1TB_5 */
133 volatile uint32_t CRSA_5; /* CRSA_5 */
134 volatile uint32_t CRDA_5; /* CRDA_5 */
135 volatile uint32_t CRTB_5; /* CRTB_5 */
136 volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
137 volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
138 volatile uint32_t CHCFG_5; /* CHCFG_5 */
139 volatile uint32_t CHITVL_5; /* CHITVL_5 */
140 volatile uint32_t CHEXT_5; /* CHEXT_5 */
141 volatile uint32_t NXLA_5; /* NXLA_5 */
142 volatile uint32_t CRLA_5; /* CRLA_5 */
143/* end of struct st_dmac_n */
144/* start of struct st_dmac_n */
145 volatile uint32_t N0SA_6; /* N0SA_6 */
146 volatile uint32_t N0DA_6; /* N0DA_6 */
147 volatile uint32_t N0TB_6; /* N0TB_6 */
148 volatile uint32_t N1SA_6; /* N1SA_6 */
149 volatile uint32_t N1DA_6; /* N1DA_6 */
150 volatile uint32_t N1TB_6; /* N1TB_6 */
151 volatile uint32_t CRSA_6; /* CRSA_6 */
152 volatile uint32_t CRDA_6; /* CRDA_6 */
153 volatile uint32_t CRTB_6; /* CRTB_6 */
154 volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
155 volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
156 volatile uint32_t CHCFG_6; /* CHCFG_6 */
157 volatile uint32_t CHITVL_6; /* CHITVL_6 */
158 volatile uint32_t CHEXT_6; /* CHEXT_6 */
159 volatile uint32_t NXLA_6; /* NXLA_6 */
160 volatile uint32_t CRLA_6; /* CRLA_6 */
161/* end of struct st_dmac_n */
162/* start of struct st_dmac_n */
163 volatile uint32_t N0SA_7; /* N0SA_7 */
164 volatile uint32_t N0DA_7; /* N0DA_7 */
165 volatile uint32_t N0TB_7; /* N0TB_7 */
166 volatile uint32_t N1SA_7; /* N1SA_7 */
167 volatile uint32_t N1DA_7; /* N1DA_7 */
168 volatile uint32_t N1TB_7; /* N1TB_7 */
169 volatile uint32_t CRSA_7; /* CRSA_7 */
170 volatile uint32_t CRDA_7; /* CRDA_7 */
171 volatile uint32_t CRTB_7; /* CRTB_7 */
172 volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
173 volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
174 volatile uint32_t CHCFG_7; /* CHCFG_7 */
175 volatile uint32_t CHITVL_7; /* CHITVL_7 */
176 volatile uint32_t CHEXT_7; /* CHEXT_7 */
177 volatile uint32_t NXLA_7; /* NXLA_7 */
178 volatile uint32_t CRLA_7; /* CRLA_7 */
179/* end of struct st_dmac_n */
180 volatile uint8_t dummy187[256]; /* */
181/* start of struct st_dmaccommon_n */
182 volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
183 volatile uint8_t dummy188[12]; /* */
184 volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
185 volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
186 volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
187 volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
188 volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
189/* end of struct st_dmaccommon_n */
190 volatile uint8_t dummy189[220]; /* */
191/* start of struct st_dmac_n */
192 volatile uint32_t N0SA_8; /* N0SA_8 */
193 volatile uint32_t N0DA_8; /* N0DA_8 */
194 volatile uint32_t N0TB_8; /* N0TB_8 */
195 volatile uint32_t N1SA_8; /* N1SA_8 */
196 volatile uint32_t N1DA_8; /* N1DA_8 */
197 volatile uint32_t N1TB_8; /* N1TB_8 */
198 volatile uint32_t CRSA_8; /* CRSA_8 */
199 volatile uint32_t CRDA_8; /* CRDA_8 */
200 volatile uint32_t CRTB_8; /* CRTB_8 */
201 volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
202 volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
203 volatile uint32_t CHCFG_8; /* CHCFG_8 */
204 volatile uint32_t CHITVL_8; /* CHITVL_8 */
205 volatile uint32_t CHEXT_8; /* CHEXT_8 */
206 volatile uint32_t NXLA_8; /* NXLA_8 */
207 volatile uint32_t CRLA_8; /* CRLA_8 */
208/* end of struct st_dmac_n */
209/* start of struct st_dmac_n */
210 volatile uint32_t N0SA_9; /* N0SA_9 */
211 volatile uint32_t N0DA_9; /* N0DA_9 */
212 volatile uint32_t N0TB_9; /* N0TB_9 */
213 volatile uint32_t N1SA_9; /* N1SA_9 */
214 volatile uint32_t N1DA_9; /* N1DA_9 */
215 volatile uint32_t N1TB_9; /* N1TB_9 */
216 volatile uint32_t CRSA_9; /* CRSA_9 */
217 volatile uint32_t CRDA_9; /* CRDA_9 */
218 volatile uint32_t CRTB_9; /* CRTB_9 */
219 volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
220 volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
221 volatile uint32_t CHCFG_9; /* CHCFG_9 */
222 volatile uint32_t CHITVL_9; /* CHITVL_9 */
223 volatile uint32_t CHEXT_9; /* CHEXT_9 */
224 volatile uint32_t NXLA_9; /* NXLA_9 */
225 volatile uint32_t CRLA_9; /* CRLA_9 */
226/* end of struct st_dmac_n */
227/* start of struct st_dmac_n */
228 volatile uint32_t N0SA_10; /* N0SA_10 */
229 volatile uint32_t N0DA_10; /* N0DA_10 */
230 volatile uint32_t N0TB_10; /* N0TB_10 */
231 volatile uint32_t N1SA_10; /* N1SA_10 */
232 volatile uint32_t N1DA_10; /* N1DA_10 */
233 volatile uint32_t N1TB_10; /* N1TB_10 */
234 volatile uint32_t CRSA_10; /* CRSA_10 */
235 volatile uint32_t CRDA_10; /* CRDA_10 */
236 volatile uint32_t CRTB_10; /* CRTB_10 */
237 volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
238 volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
239 volatile uint32_t CHCFG_10; /* CHCFG_10 */
240 volatile uint32_t CHITVL_10; /* CHITVL_10 */
241 volatile uint32_t CHEXT_10; /* CHEXT_10 */
242 volatile uint32_t NXLA_10; /* NXLA_10 */
243 volatile uint32_t CRLA_10; /* CRLA_10 */
244/* end of struct st_dmac_n */
245/* start of struct st_dmac_n */
246 volatile uint32_t N0SA_11; /* N0SA_11 */
247 volatile uint32_t N0DA_11; /* N0DA_11 */
248 volatile uint32_t N0TB_11; /* N0TB_11 */
249 volatile uint32_t N1SA_11; /* N1SA_11 */
250 volatile uint32_t N1DA_11; /* N1DA_11 */
251 volatile uint32_t N1TB_11; /* N1TB_11 */
252 volatile uint32_t CRSA_11; /* CRSA_11 */
253 volatile uint32_t CRDA_11; /* CRDA_11 */
254 volatile uint32_t CRTB_11; /* CRTB_11 */
255 volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
256 volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
257 volatile uint32_t CHCFG_11; /* CHCFG_11 */
258 volatile uint32_t CHITVL_11; /* CHITVL_11 */
259 volatile uint32_t CHEXT_11; /* CHEXT_11 */
260 volatile uint32_t NXLA_11; /* NXLA_11 */
261 volatile uint32_t CRLA_11; /* CRLA_11 */
262/* end of struct st_dmac_n */
263/* start of struct st_dmac_n */
264 volatile uint32_t N0SA_12; /* N0SA_12 */
265 volatile uint32_t N0DA_12; /* N0DA_12 */
266 volatile uint32_t N0TB_12; /* N0TB_12 */
267 volatile uint32_t N1SA_12; /* N1SA_12 */
268 volatile uint32_t N1DA_12; /* N1DA_12 */
269 volatile uint32_t N1TB_12; /* N1TB_12 */
270 volatile uint32_t CRSA_12; /* CRSA_12 */
271 volatile uint32_t CRDA_12; /* CRDA_12 */
272 volatile uint32_t CRTB_12; /* CRTB_12 */
273 volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
274 volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
275 volatile uint32_t CHCFG_12; /* CHCFG_12 */
276 volatile uint32_t CHITVL_12; /* CHITVL_12 */
277 volatile uint32_t CHEXT_12; /* CHEXT_12 */
278 volatile uint32_t NXLA_12; /* NXLA_12 */
279 volatile uint32_t CRLA_12; /* CRLA_12 */
280/* end of struct st_dmac_n */
281/* start of struct st_dmac_n */
282 volatile uint32_t N0SA_13; /* N0SA_13 */
283 volatile uint32_t N0DA_13; /* N0DA_13 */
284 volatile uint32_t N0TB_13; /* N0TB_13 */
285 volatile uint32_t N1SA_13; /* N1SA_13 */
286 volatile uint32_t N1DA_13; /* N1DA_13 */
287 volatile uint32_t N1TB_13; /* N1TB_13 */
288 volatile uint32_t CRSA_13; /* CRSA_13 */
289 volatile uint32_t CRDA_13; /* CRDA_13 */
290 volatile uint32_t CRTB_13; /* CRTB_13 */
291 volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
292 volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
293 volatile uint32_t CHCFG_13; /* CHCFG_13 */
294 volatile uint32_t CHITVL_13; /* CHITVL_13 */
295 volatile uint32_t CHEXT_13; /* CHEXT_13 */
296 volatile uint32_t NXLA_13; /* NXLA_13 */
297 volatile uint32_t CRLA_13; /* CRLA_13 */
298/* end of struct st_dmac_n */
299/* start of struct st_dmac_n */
300 volatile uint32_t N0SA_14; /* N0SA_14 */
301 volatile uint32_t N0DA_14; /* N0DA_14 */
302 volatile uint32_t N0TB_14; /* N0TB_14 */
303 volatile uint32_t N1SA_14; /* N1SA_14 */
304 volatile uint32_t N1DA_14; /* N1DA_14 */
305 volatile uint32_t N1TB_14; /* N1TB_14 */
306 volatile uint32_t CRSA_14; /* CRSA_14 */
307 volatile uint32_t CRDA_14; /* CRDA_14 */
308 volatile uint32_t CRTB_14; /* CRTB_14 */
309 volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
310 volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
311 volatile uint32_t CHCFG_14; /* CHCFG_14 */
312 volatile uint32_t CHITVL_14; /* CHITVL_14 */
313 volatile uint32_t CHEXT_14; /* CHEXT_14 */
314 volatile uint32_t NXLA_14; /* NXLA_14 */
315 volatile uint32_t CRLA_14; /* CRLA_14 */
316/* end of struct st_dmac_n */
317/* start of struct st_dmac_n */
318 volatile uint32_t N0SA_15; /* N0SA_15 */
319 volatile uint32_t N0DA_15; /* N0DA_15 */
320 volatile uint32_t N0TB_15; /* N0TB_15 */
321 volatile uint32_t N1SA_15; /* N1SA_15 */
322 volatile uint32_t N1DA_15; /* N1DA_15 */
323 volatile uint32_t N1TB_15; /* N1TB_15 */
324 volatile uint32_t CRSA_15; /* CRSA_15 */
325 volatile uint32_t CRDA_15; /* CRDA_15 */
326 volatile uint32_t CRTB_15; /* CRTB_15 */
327 volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
328 volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
329 volatile uint32_t CHCFG_15; /* CHCFG_15 */
330 volatile uint32_t CHITVL_15; /* CHITVL_15 */
331 volatile uint32_t CHEXT_15; /* CHEXT_15 */
332 volatile uint32_t NXLA_15; /* NXLA_15 */
333 volatile uint32_t CRLA_15; /* CRLA_15 */
334/* end of struct st_dmac_n */
335 volatile uint8_t dummy190[256]; /* */
336/* start of struct st_dmaccommon_n */
337 volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
338 volatile uint8_t dummy191[12]; /* */
339 volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
340 volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
341 volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
342 volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
343 volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
344/* end of struct st_dmaccommon_n */
345 volatile uint8_t dummy192[350095580]; /* */
346 volatile uint32_t DMARS0; /* DMARS0 */
347 volatile uint32_t DMARS1; /* DMARS1 */
348 volatile uint32_t DMARS2; /* DMARS2 */
349 volatile uint32_t DMARS3; /* DMARS3 */
350 volatile uint32_t DMARS4; /* DMARS4 */
351 volatile uint32_t DMARS5; /* DMARS5 */
352 volatile uint32_t DMARS6; /* DMARS6 */
353 volatile uint32_t DMARS7; /* DMARS7 */
354};
355
356
357struct st_dmaccommon_n
358{
359 volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
360 volatile uint8_t dummy1[12]; /* */
361 volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
362 volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
363 volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
364 volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
365 volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
366};
367
368
369struct st_dmac_n
370{
371 volatile uint32_t N0SA_n; /* N0SA_n */
372 volatile uint32_t N0DA_n; /* N0DA_n */
373 volatile uint32_t N0TB_n; /* N0TB_n */
374 volatile uint32_t N1SA_n; /* N1SA_n */
375 volatile uint32_t N1DA_n; /* N1DA_n */
376 volatile uint32_t N1TB_n; /* N1TB_n */
377 volatile uint32_t CRSA_n; /* CRSA_n */
378 volatile uint32_t CRDA_n; /* CRDA_n */
379 volatile uint32_t CRTB_n; /* CRTB_n */
380 volatile uint32_t CHSTAT_n; /* CHSTAT_n */
381 volatile uint32_t CHCTRL_n; /* CHCTRL_n */
382 volatile uint32_t CHCFG_n; /* CHCFG_n */
383 volatile uint32_t CHITVL_n; /* CHITVL_n */
384 volatile uint32_t CHEXT_n; /* CHEXT_n */
385 volatile uint32_t NXLA_n; /* NXLA_n */
386 volatile uint32_t CRLA_n; /* CRLA_n */
387};
388
389
390#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
391
392
393/* Start of channnel array defines of DMAC */
394
395/* Channnel array defines of DMACn */
396/*(Sample) value = DMACn[ channel ]->N0SA_n; */
397#define DMACn_COUNT 16
398#define DMACn_ADDRESS_LIST \
399{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
400 &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
401 &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
402} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
403#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
404#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
405#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
406#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
407#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
408#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
409#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
410#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
411#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
412#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
413#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
414#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
415#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
416#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
417#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
418#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
419
420
421/* Channnel array defines of DMACnn */
422/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
423#define DMACnn_COUNT 2
424#define DMACnn_ADDRESS_LIST \
425{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
426 &DMAC07, &DMAC815 \
427} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
428#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
429#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
430
431
432/* Channnel array defines of DMACmm */
433/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
434struct st_dmars_mm
435{
436 uint32_t DMARS; /* DMARS */
437};
438#define DMACmm_COUNT 8
439#define DMACmm_ADDRESS_LIST \
440{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
441 &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
442} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
443#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
444#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
445#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
446#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
447#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
448#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
449#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
450#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
451
452/* End of channnel array defines of DMAC */
453
454
455#define DMACN0SA_0 DMAC.N0SA_0
456#define DMACN0DA_0 DMAC.N0DA_0
457#define DMACN0TB_0 DMAC.N0TB_0
458#define DMACN1SA_0 DMAC.N1SA_0
459#define DMACN1DA_0 DMAC.N1DA_0
460#define DMACN1TB_0 DMAC.N1TB_0
461#define DMACCRSA_0 DMAC.CRSA_0
462#define DMACCRDA_0 DMAC.CRDA_0
463#define DMACCRTB_0 DMAC.CRTB_0
464#define DMACCHSTAT_0 DMAC.CHSTAT_0
465#define DMACCHCTRL_0 DMAC.CHCTRL_0
466#define DMACCHCFG_0 DMAC.CHCFG_0
467#define DMACCHITVL_0 DMAC.CHITVL_0
468#define DMACCHEXT_0 DMAC.CHEXT_0
469#define DMACNXLA_0 DMAC.NXLA_0
470#define DMACCRLA_0 DMAC.CRLA_0
471#define DMACN0SA_1 DMAC.N0SA_1
472#define DMACN0DA_1 DMAC.N0DA_1
473#define DMACN0TB_1 DMAC.N0TB_1
474#define DMACN1SA_1 DMAC.N1SA_1
475#define DMACN1DA_1 DMAC.N1DA_1
476#define DMACN1TB_1 DMAC.N1TB_1
477#define DMACCRSA_1 DMAC.CRSA_1
478#define DMACCRDA_1 DMAC.CRDA_1
479#define DMACCRTB_1 DMAC.CRTB_1
480#define DMACCHSTAT_1 DMAC.CHSTAT_1
481#define DMACCHCTRL_1 DMAC.CHCTRL_1
482#define DMACCHCFG_1 DMAC.CHCFG_1
483#define DMACCHITVL_1 DMAC.CHITVL_1
484#define DMACCHEXT_1 DMAC.CHEXT_1
485#define DMACNXLA_1 DMAC.NXLA_1
486#define DMACCRLA_1 DMAC.CRLA_1
487#define DMACN0SA_2 DMAC.N0SA_2
488#define DMACN0DA_2 DMAC.N0DA_2
489#define DMACN0TB_2 DMAC.N0TB_2
490#define DMACN1SA_2 DMAC.N1SA_2
491#define DMACN1DA_2 DMAC.N1DA_2
492#define DMACN1TB_2 DMAC.N1TB_2
493#define DMACCRSA_2 DMAC.CRSA_2
494#define DMACCRDA_2 DMAC.CRDA_2
495#define DMACCRTB_2 DMAC.CRTB_2
496#define DMACCHSTAT_2 DMAC.CHSTAT_2
497#define DMACCHCTRL_2 DMAC.CHCTRL_2
498#define DMACCHCFG_2 DMAC.CHCFG_2
499#define DMACCHITVL_2 DMAC.CHITVL_2
500#define DMACCHEXT_2 DMAC.CHEXT_2
501#define DMACNXLA_2 DMAC.NXLA_2
502#define DMACCRLA_2 DMAC.CRLA_2
503#define DMACN0SA_3 DMAC.N0SA_3
504#define DMACN0DA_3 DMAC.N0DA_3
505#define DMACN0TB_3 DMAC.N0TB_3
506#define DMACN1SA_3 DMAC.N1SA_3
507#define DMACN1DA_3 DMAC.N1DA_3
508#define DMACN1TB_3 DMAC.N1TB_3
509#define DMACCRSA_3 DMAC.CRSA_3
510#define DMACCRDA_3 DMAC.CRDA_3
511#define DMACCRTB_3 DMAC.CRTB_3
512#define DMACCHSTAT_3 DMAC.CHSTAT_3
513#define DMACCHCTRL_3 DMAC.CHCTRL_3
514#define DMACCHCFG_3 DMAC.CHCFG_3
515#define DMACCHITVL_3 DMAC.CHITVL_3
516#define DMACCHEXT_3 DMAC.CHEXT_3
517#define DMACNXLA_3 DMAC.NXLA_3
518#define DMACCRLA_3 DMAC.CRLA_3
519#define DMACN0SA_4 DMAC.N0SA_4
520#define DMACN0DA_4 DMAC.N0DA_4
521#define DMACN0TB_4 DMAC.N0TB_4
522#define DMACN1SA_4 DMAC.N1SA_4
523#define DMACN1DA_4 DMAC.N1DA_4
524#define DMACN1TB_4 DMAC.N1TB_4
525#define DMACCRSA_4 DMAC.CRSA_4
526#define DMACCRDA_4 DMAC.CRDA_4
527#define DMACCRTB_4 DMAC.CRTB_4
528#define DMACCHSTAT_4 DMAC.CHSTAT_4
529#define DMACCHCTRL_4 DMAC.CHCTRL_4
530#define DMACCHCFG_4 DMAC.CHCFG_4
531#define DMACCHITVL_4 DMAC.CHITVL_4
532#define DMACCHEXT_4 DMAC.CHEXT_4
533#define DMACNXLA_4 DMAC.NXLA_4
534#define DMACCRLA_4 DMAC.CRLA_4
535#define DMACN0SA_5 DMAC.N0SA_5
536#define DMACN0DA_5 DMAC.N0DA_5
537#define DMACN0TB_5 DMAC.N0TB_5
538#define DMACN1SA_5 DMAC.N1SA_5
539#define DMACN1DA_5 DMAC.N1DA_5
540#define DMACN1TB_5 DMAC.N1TB_5
541#define DMACCRSA_5 DMAC.CRSA_5
542#define DMACCRDA_5 DMAC.CRDA_5
543#define DMACCRTB_5 DMAC.CRTB_5
544#define DMACCHSTAT_5 DMAC.CHSTAT_5
545#define DMACCHCTRL_5 DMAC.CHCTRL_5
546#define DMACCHCFG_5 DMAC.CHCFG_5
547#define DMACCHITVL_5 DMAC.CHITVL_5
548#define DMACCHEXT_5 DMAC.CHEXT_5
549#define DMACNXLA_5 DMAC.NXLA_5
550#define DMACCRLA_5 DMAC.CRLA_5
551#define DMACN0SA_6 DMAC.N0SA_6
552#define DMACN0DA_6 DMAC.N0DA_6
553#define DMACN0TB_6 DMAC.N0TB_6
554#define DMACN1SA_6 DMAC.N1SA_6
555#define DMACN1DA_6 DMAC.N1DA_6
556#define DMACN1TB_6 DMAC.N1TB_6
557#define DMACCRSA_6 DMAC.CRSA_6
558#define DMACCRDA_6 DMAC.CRDA_6
559#define DMACCRTB_6 DMAC.CRTB_6
560#define DMACCHSTAT_6 DMAC.CHSTAT_6
561#define DMACCHCTRL_6 DMAC.CHCTRL_6
562#define DMACCHCFG_6 DMAC.CHCFG_6
563#define DMACCHITVL_6 DMAC.CHITVL_6
564#define DMACCHEXT_6 DMAC.CHEXT_6
565#define DMACNXLA_6 DMAC.NXLA_6
566#define DMACCRLA_6 DMAC.CRLA_6
567#define DMACN0SA_7 DMAC.N0SA_7
568#define DMACN0DA_7 DMAC.N0DA_7
569#define DMACN0TB_7 DMAC.N0TB_7
570#define DMACN1SA_7 DMAC.N1SA_7
571#define DMACN1DA_7 DMAC.N1DA_7
572#define DMACN1TB_7 DMAC.N1TB_7
573#define DMACCRSA_7 DMAC.CRSA_7
574#define DMACCRDA_7 DMAC.CRDA_7
575#define DMACCRTB_7 DMAC.CRTB_7
576#define DMACCHSTAT_7 DMAC.CHSTAT_7
577#define DMACCHCTRL_7 DMAC.CHCTRL_7
578#define DMACCHCFG_7 DMAC.CHCFG_7
579#define DMACCHITVL_7 DMAC.CHITVL_7
580#define DMACCHEXT_7 DMAC.CHEXT_7
581#define DMACNXLA_7 DMAC.NXLA_7
582#define DMACCRLA_7 DMAC.CRLA_7
583#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
584#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
585#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
586#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
587#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
588#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
589#define DMACN0SA_8 DMAC.N0SA_8
590#define DMACN0DA_8 DMAC.N0DA_8
591#define DMACN0TB_8 DMAC.N0TB_8
592#define DMACN1SA_8 DMAC.N1SA_8
593#define DMACN1DA_8 DMAC.N1DA_8
594#define DMACN1TB_8 DMAC.N1TB_8
595#define DMACCRSA_8 DMAC.CRSA_8
596#define DMACCRDA_8 DMAC.CRDA_8
597#define DMACCRTB_8 DMAC.CRTB_8
598#define DMACCHSTAT_8 DMAC.CHSTAT_8
599#define DMACCHCTRL_8 DMAC.CHCTRL_8
600#define DMACCHCFG_8 DMAC.CHCFG_8
601#define DMACCHITVL_8 DMAC.CHITVL_8
602#define DMACCHEXT_8 DMAC.CHEXT_8
603#define DMACNXLA_8 DMAC.NXLA_8
604#define DMACCRLA_8 DMAC.CRLA_8
605#define DMACN0SA_9 DMAC.N0SA_9
606#define DMACN0DA_9 DMAC.N0DA_9
607#define DMACN0TB_9 DMAC.N0TB_9
608#define DMACN1SA_9 DMAC.N1SA_9
609#define DMACN1DA_9 DMAC.N1DA_9
610#define DMACN1TB_9 DMAC.N1TB_9
611#define DMACCRSA_9 DMAC.CRSA_9
612#define DMACCRDA_9 DMAC.CRDA_9
613#define DMACCRTB_9 DMAC.CRTB_9
614#define DMACCHSTAT_9 DMAC.CHSTAT_9
615#define DMACCHCTRL_9 DMAC.CHCTRL_9
616#define DMACCHCFG_9 DMAC.CHCFG_9
617#define DMACCHITVL_9 DMAC.CHITVL_9
618#define DMACCHEXT_9 DMAC.CHEXT_9
619#define DMACNXLA_9 DMAC.NXLA_9
620#define DMACCRLA_9 DMAC.CRLA_9
621#define DMACN0SA_10 DMAC.N0SA_10
622#define DMACN0DA_10 DMAC.N0DA_10
623#define DMACN0TB_10 DMAC.N0TB_10
624#define DMACN1SA_10 DMAC.N1SA_10
625#define DMACN1DA_10 DMAC.N1DA_10
626#define DMACN1TB_10 DMAC.N1TB_10
627#define DMACCRSA_10 DMAC.CRSA_10
628#define DMACCRDA_10 DMAC.CRDA_10
629#define DMACCRTB_10 DMAC.CRTB_10
630#define DMACCHSTAT_10 DMAC.CHSTAT_10
631#define DMACCHCTRL_10 DMAC.CHCTRL_10
632#define DMACCHCFG_10 DMAC.CHCFG_10
633#define DMACCHITVL_10 DMAC.CHITVL_10
634#define DMACCHEXT_10 DMAC.CHEXT_10
635#define DMACNXLA_10 DMAC.NXLA_10
636#define DMACCRLA_10 DMAC.CRLA_10
637#define DMACN0SA_11 DMAC.N0SA_11
638#define DMACN0DA_11 DMAC.N0DA_11
639#define DMACN0TB_11 DMAC.N0TB_11
640#define DMACN1SA_11 DMAC.N1SA_11
641#define DMACN1DA_11 DMAC.N1DA_11
642#define DMACN1TB_11 DMAC.N1TB_11
643#define DMACCRSA_11 DMAC.CRSA_11
644#define DMACCRDA_11 DMAC.CRDA_11
645#define DMACCRTB_11 DMAC.CRTB_11
646#define DMACCHSTAT_11 DMAC.CHSTAT_11
647#define DMACCHCTRL_11 DMAC.CHCTRL_11
648#define DMACCHCFG_11 DMAC.CHCFG_11
649#define DMACCHITVL_11 DMAC.CHITVL_11
650#define DMACCHEXT_11 DMAC.CHEXT_11
651#define DMACNXLA_11 DMAC.NXLA_11
652#define DMACCRLA_11 DMAC.CRLA_11
653#define DMACN0SA_12 DMAC.N0SA_12
654#define DMACN0DA_12 DMAC.N0DA_12
655#define DMACN0TB_12 DMAC.N0TB_12
656#define DMACN1SA_12 DMAC.N1SA_12
657#define DMACN1DA_12 DMAC.N1DA_12
658#define DMACN1TB_12 DMAC.N1TB_12
659#define DMACCRSA_12 DMAC.CRSA_12
660#define DMACCRDA_12 DMAC.CRDA_12
661#define DMACCRTB_12 DMAC.CRTB_12
662#define DMACCHSTAT_12 DMAC.CHSTAT_12
663#define DMACCHCTRL_12 DMAC.CHCTRL_12
664#define DMACCHCFG_12 DMAC.CHCFG_12
665#define DMACCHITVL_12 DMAC.CHITVL_12
666#define DMACCHEXT_12 DMAC.CHEXT_12
667#define DMACNXLA_12 DMAC.NXLA_12
668#define DMACCRLA_12 DMAC.CRLA_12
669#define DMACN0SA_13 DMAC.N0SA_13
670#define DMACN0DA_13 DMAC.N0DA_13
671#define DMACN0TB_13 DMAC.N0TB_13
672#define DMACN1SA_13 DMAC.N1SA_13
673#define DMACN1DA_13 DMAC.N1DA_13
674#define DMACN1TB_13 DMAC.N1TB_13
675#define DMACCRSA_13 DMAC.CRSA_13
676#define DMACCRDA_13 DMAC.CRDA_13
677#define DMACCRTB_13 DMAC.CRTB_13
678#define DMACCHSTAT_13 DMAC.CHSTAT_13
679#define DMACCHCTRL_13 DMAC.CHCTRL_13
680#define DMACCHCFG_13 DMAC.CHCFG_13
681#define DMACCHITVL_13 DMAC.CHITVL_13
682#define DMACCHEXT_13 DMAC.CHEXT_13
683#define DMACNXLA_13 DMAC.NXLA_13
684#define DMACCRLA_13 DMAC.CRLA_13
685#define DMACN0SA_14 DMAC.N0SA_14
686#define DMACN0DA_14 DMAC.N0DA_14
687#define DMACN0TB_14 DMAC.N0TB_14
688#define DMACN1SA_14 DMAC.N1SA_14
689#define DMACN1DA_14 DMAC.N1DA_14
690#define DMACN1TB_14 DMAC.N1TB_14
691#define DMACCRSA_14 DMAC.CRSA_14
692#define DMACCRDA_14 DMAC.CRDA_14
693#define DMACCRTB_14 DMAC.CRTB_14
694#define DMACCHSTAT_14 DMAC.CHSTAT_14
695#define DMACCHCTRL_14 DMAC.CHCTRL_14
696#define DMACCHCFG_14 DMAC.CHCFG_14
697#define DMACCHITVL_14 DMAC.CHITVL_14
698#define DMACCHEXT_14 DMAC.CHEXT_14
699#define DMACNXLA_14 DMAC.NXLA_14
700#define DMACCRLA_14 DMAC.CRLA_14
701#define DMACN0SA_15 DMAC.N0SA_15
702#define DMACN0DA_15 DMAC.N0DA_15
703#define DMACN0TB_15 DMAC.N0TB_15
704#define DMACN1SA_15 DMAC.N1SA_15
705#define DMACN1DA_15 DMAC.N1DA_15
706#define DMACN1TB_15 DMAC.N1TB_15
707#define DMACCRSA_15 DMAC.CRSA_15
708#define DMACCRDA_15 DMAC.CRDA_15
709#define DMACCRTB_15 DMAC.CRTB_15
710#define DMACCHSTAT_15 DMAC.CHSTAT_15
711#define DMACCHCTRL_15 DMAC.CHCTRL_15
712#define DMACCHCFG_15 DMAC.CHCFG_15
713#define DMACCHITVL_15 DMAC.CHITVL_15
714#define DMACCHEXT_15 DMAC.CHEXT_15
715#define DMACNXLA_15 DMAC.NXLA_15
716#define DMACCRLA_15 DMAC.CRLA_15
717#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
718#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
719#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
720#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
721#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
722#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
723#define DMACDMARS0 DMAC.DMARS0
724#define DMACDMARS1 DMAC.DMARS1
725#define DMACDMARS2 DMAC.DMARS2
726#define DMACDMARS3 DMAC.DMARS3
727#define DMACDMARS4 DMAC.DMARS4
728#define DMACDMARS5 DMAC.DMARS5
729#define DMACDMARS6 DMAC.DMARS6
730#define DMACDMARS7 DMAC.DMARS7
731/* <-SEC M1.10.1 */
732/* <-QAC 0639 */
733#endif
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