1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer
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21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : rspi_iobitmask.h
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25 | * $Rev: 1114 $
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26 | * $Date:: 2014-07-09 14:56:39 +0900#$
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27 | * Description : Renesas Serial Peripheral Interface register define header
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28 | *******************************************************************************/
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29 | #ifndef RSPI_IOBITMASK_H
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30 | #define RSPI_IOBITMASK_H
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31 |
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32 |
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33 | /* ==== Mask values for IO registers ==== */
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34 | #define RSPIn_SPCR_MODFEN (0x04u)
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35 | #define RSPIn_SPCR_MSTR (0x08u)
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36 | #define RSPIn_SPCR_SPEIE (0x10u)
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37 | #define RSPIn_SPCR_SPTIE (0x20u)
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38 | #define RSPIn_SPCR_SPE (0x40u)
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39 | #define RSPIn_SPCR_SPRIE (0x80u)
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40 |
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41 | #define RSPIn_SSLP_SSL0P (0x01u)
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42 |
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43 | #define RSPIn_SPPCR_SPLP (0x01u)
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44 | #define RSPIn_SPPCR_MOIFV (0x10u)
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45 | #define RSPIn_SPPCR_MOIFE (0x20u)
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46 |
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47 | #define RSPIn_SPSR_OVRF (0x01u)
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48 | #define RSPIn_SPSR_MODF (0x04u)
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49 | #define RSPIn_SPSR_SPTEF (0x20u)
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50 | #define RSPIn_SPSR_TEND (0x40u)
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51 | #define RSPIn_SPSR_SPRF (0x80u)
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52 |
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53 | #define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
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54 |
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55 | #define RSPIn_SPDR_UINT16 (0xFFFFu)
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56 |
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57 | #define RSPIn_SPDR_UINT8 (0xFFu)
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58 |
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59 | #define RSPIn_SPSCR_SPSLN (0x03u)
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60 |
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61 | #define RSPIn_SPSSR_SPCP (0x03u)
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62 |
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63 | #define RSPIn_SPBR_SPR (0xFFu)
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64 |
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65 | #define RSPIn_SPDCR_SPLW (0x60u)
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66 | #define RSPIn_SPDCR_TXDMY (0x80u)
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67 |
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68 | #define RSPIn_SPCKD_SCKDL (0x07u)
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69 |
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70 | #define RSPIn_SSLND_SLNDL (0x07u)
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71 |
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72 | #define RSPIn_SPND_SPNDL (0x07u)
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73 |
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74 | #define RSPIn_SPCMD0_CPHA (0x0001u)
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75 | #define RSPIn_SPCMD0_CPOL (0x0002u)
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76 | #define RSPIn_SPCMD0_BRDV (0x000Cu)
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77 | #define RSPIn_SPCMD0_SSLKP (0x0080u)
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78 | #define RSPIn_SPCMD0_SPB (0x0F00u)
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79 | #define RSPIn_SPCMD0_LSBF (0x1000u)
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80 | #define RSPIn_SPCMD0_SPNDEN (0x2000u)
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81 | #define RSPIn_SPCMD0_SLNDEN (0x4000u)
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82 | #define RSPIn_SPCMD0_SCKDEN (0x8000u)
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83 |
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84 | #define RSPIn_SPCMD1_CPHA (0x0001u)
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85 | #define RSPIn_SPCMD1_CPOL (0x0002u)
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86 | #define RSPIn_SPCMD1_BRDV (0x000Cu)
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87 | #define RSPIn_SPCMD1_SSLKP (0x0080u)
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88 | #define RSPIn_SPCMD1_SPB (0x0F00u)
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89 | #define RSPIn_SPCMD1_LSBF (0x1000u)
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90 | #define RSPIn_SPCMD1_SPNDEN (0x2000u)
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91 | #define RSPIn_SPCMD1_SLNDEN (0x4000u)
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92 | #define RSPIn_SPCMD1_SCKDEN (0x8000u)
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93 |
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94 | #define RSPIn_SPCMD2_CPHA (0x0001u)
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95 | #define RSPIn_SPCMD2_CPOL (0x0002u)
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96 | #define RSPIn_SPCMD2_BRDV (0x000Cu)
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97 | #define RSPIn_SPCMD2_SSLKP (0x0080u)
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98 | #define RSPIn_SPCMD2_SPB (0x0F00u)
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99 | #define RSPIn_SPCMD2_LSBF (0x1000u)
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100 | #define RSPIn_SPCMD2_SPNDEN (0x2000u)
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101 | #define RSPIn_SPCMD2_SLNDEN (0x4000u)
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102 | #define RSPIn_SPCMD2_SCKDEN (0x8000u)
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103 |
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104 | #define RSPIn_SPCMD3_CPHA (0x0001u)
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105 | #define RSPIn_SPCMD3_CPOL (0x0002u)
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106 | #define RSPIn_SPCMD3_BRDV (0x000Cu)
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107 | #define RSPIn_SPCMD3_SSLKP (0x0080u)
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108 | #define RSPIn_SPCMD3_SPB (0x0F00u)
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109 | #define RSPIn_SPCMD3_LSBF (0x1000u)
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110 | #define RSPIn_SPCMD3_SPNDEN (0x2000u)
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111 | #define RSPIn_SPCMD3_SLNDEN (0x4000u)
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112 | #define RSPIn_SPCMD3_SCKDEN (0x8000u)
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113 |
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114 | #define RSPIn_SPBFCR_RXTRG (0x07u)
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115 | #define RSPIn_SPBFCR_TXTRG (0x30u)
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116 | #define RSPIn_SPBFCR_RXRST (0x40u)
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117 | #define RSPIn_SPBFCR_TXRST (0x80u)
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118 |
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119 | #define RSPIn_SPBFDR_R (0x003Fu)
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120 | #define RSPIn_SPBFDR_T (0x0F00u)
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121 |
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122 |
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123 | /* ==== Shift values for IO registers ==== */
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124 | #define RSPIn_SPCR_MODFEN_SHIFT (2u)
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125 | #define RSPIn_SPCR_MSTR_SHIFT (3u)
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126 | #define RSPIn_SPCR_SPEIE_SHIFT (4u)
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127 | #define RSPIn_SPCR_SPTIE_SHIFT (5u)
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128 | #define RSPIn_SPCR_SPE_SHIFT (6u)
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129 | #define RSPIn_SPCR_SPRIE_SHIFT (7u)
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130 |
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131 | #define RSPIn_SSLP_SSL0P_SHIFT (0u)
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132 |
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133 | #define RSPIn_SPPCR_SPLP_SHIFT (0u)
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134 | #define RSPIn_SPPCR_MOIFV_SHIFT (4u)
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135 | #define RSPIn_SPPCR_MOIFE_SHIFT (5u)
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136 |
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137 | #define RSPIn_SPSR_OVRF_SHIFT (0u)
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138 | #define RSPIn_SPSR_MODF_SHIFT (2u)
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139 | #define RSPIn_SPSR_SPTEF_SHIFT (5u)
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140 | #define RSPIn_SPSR_TEND_SHIFT (6u)
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141 | #define RSPIn_SPSR_SPRF_SHIFT (7u)
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142 |
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143 | #define RSPIn_SPDR_UINT32_SHIFT (0u)
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144 |
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145 | #define RSPIn_SPDR_UINT16_SHIFT (0u)
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146 |
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147 | #define RSPIn_SPDR_UINT8_SHIFT (0u)
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148 |
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149 | #define RSPIn_SPSCR_SPSLN_SHIFT (0u)
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150 |
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151 | #define RSPIn_SPSSR_SPCP_SHIFT (0u)
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152 |
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153 | #define RSPIn_SPBR_SPR_SHIFT (0u)
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154 |
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155 | #define RSPIn_SPDCR_SPLW_SHIFT (5u)
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156 | #define RSPIn_SPDCR_TXDMY_SHIFT (7u)
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157 |
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158 | #define RSPIn_SPCKD_SCKDL_SHIFT (0u)
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159 |
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160 | #define RSPIn_SSLND_SLNDL_SHIFT (0u)
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161 |
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162 | #define RSPIn_SPND_SPNDL_SHIFT (0u)
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163 |
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164 | #define RSPIn_SPCMD0_CPHA_SHIFT (0u)
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165 | #define RSPIn_SPCMD0_CPOL_SHIFT (1u)
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166 | #define RSPIn_SPCMD0_BRDV_SHIFT (2u)
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167 | #define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
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168 | #define RSPIn_SPCMD0_SPB_SHIFT (8u)
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169 | #define RSPIn_SPCMD0_LSBF_SHIFT (12u)
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170 | #define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
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171 | #define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
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172 | #define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
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173 |
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174 | #define RSPIn_SPCMD1_CPHA_SHIFT (0u)
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175 | #define RSPIn_SPCMD1_CPOL_SHIFT (1u)
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176 | #define RSPIn_SPCMD1_BRDV_SHIFT (2u)
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177 | #define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
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178 | #define RSPIn_SPCMD1_SPB_SHIFT (8u)
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179 | #define RSPIn_SPCMD1_LSBF_SHIFT (12u)
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180 | #define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
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181 | #define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
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182 | #define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
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183 |
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184 | #define RSPIn_SPCMD2_CPHA_SHIFT (0u)
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185 | #define RSPIn_SPCMD2_CPOL_SHIFT (1u)
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186 | #define RSPIn_SPCMD2_BRDV_SHIFT (2u)
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187 | #define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
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188 | #define RSPIn_SPCMD2_SPB_SHIFT (8u)
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189 | #define RSPIn_SPCMD2_LSBF_SHIFT (12u)
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190 | #define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
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191 | #define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
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192 | #define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
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193 |
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194 | #define RSPIn_SPCMD3_CPHA_SHIFT (0u)
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195 | #define RSPIn_SPCMD3_CPOL_SHIFT (1u)
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196 | #define RSPIn_SPCMD3_BRDV_SHIFT (2u)
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197 | #define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
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198 | #define RSPIn_SPCMD3_SPB_SHIFT (8u)
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199 | #define RSPIn_SPCMD3_LSBF_SHIFT (12u)
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200 | #define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
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201 | #define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
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202 | #define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
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203 |
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204 | #define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
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205 | #define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
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206 | #define RSPIn_SPBFCR_RXRST_SHIFT (6u)
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207 | #define RSPIn_SPBFCR_TXRST_SHIFT (7u)
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208 |
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209 | #define RSPIn_SPBFDR_R_SHIFT (0u)
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210 | #define RSPIn_SPBFDR_T_SHIFT (8u)
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211 |
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212 |
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213 | #endif /* RSPI_IOBITMASK_H */
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214 |
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215 | /* End of File */
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