[270] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer
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| 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : mtu2_iobitmask.h
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| 25 | * $Rev: 1138 $
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| 26 | * $Date:: 2014-08-08 11:03:56 +0900#$
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| 27 | * Description : MTU2 register define header
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| 28 | *******************************************************************************/
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| 29 | #ifndef MTU2_IOBITMASK_H
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| 30 | #define MTU2_IOBITMASK_H
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| 31 |
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| 32 |
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| 33 | /* ==== Mask values for IO registers ==== */
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| 34 | #define MTU2_TCR_n_TPSC (0x07u)
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| 35 | #define MTU2_TCR_n_CKEG (0x18u)
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| 36 | #define MTU2_TCR_n_CCLR (0xE0u)
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| 37 |
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| 38 | #define MTU2_TMDR_n_MD (0x0Fu)
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| 39 |
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| 40 | #define MTU2_TIOR_2_IOA (0x0Fu)
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| 41 | #define MTU2_TIOR_2_IOB (0xF0u)
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| 42 |
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| 43 | #define MTU2_TIER_n_TGIEA (0x01u)
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| 44 | #define MTU2_TIER_n_TGIEB (0x02u)
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| 45 | #define MTU2_TIER_n_TCIEV (0x10u)
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| 46 | #define MTU2_TIER_2_TCIEU (0x20u)
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| 47 | #define MTU2_TIER_n_TTGE (0x80u)
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| 48 |
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| 49 | #define MTU2_TSR_n_TGFA (0x01u)
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| 50 | #define MTU2_TSR_n_TGFB (0x02u)
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| 51 | #define MTU2_TSR_n_TCFV (0x10u)
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| 52 | #define MTU2_TSR_2_TCFU (0x20u)
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| 53 | #define MTU2_TSR_2_TCFD (0x80u)
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| 54 |
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| 55 | #define MTU2_TCNT_n_D (0xFFFFu)
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| 56 |
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| 57 | #define MTU2_TGRA_n_D (0xFFFFu)
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| 58 |
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| 59 | #define MTU2_TGRB_n_D (0xFFFFu)
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| 60 |
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| 61 | #define MTU2_TMDR_3_BFA (0x10u)
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| 62 | #define MTU2_TMDR_3_BFB (0x20u)
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| 63 |
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| 64 | #define MTU2_TMDR_4_BFA (0x10u)
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| 65 | #define MTU2_TMDR_4_BFB (0x20u)
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| 66 |
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| 67 | #define MTU2_TIORH_3_IOA (0x0Fu)
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| 68 | #define MTU2_TIORH_3_IOB (0xF0u)
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| 69 |
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| 70 | #define MTU2_TIORL_3_IOC (0x0Fu)
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| 71 | #define MTU2_TIORL_3_IOD (0xF0u)
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| 72 |
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| 73 | #define MTU2_TIORH_4_IOA (0x0Fu)
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| 74 | #define MTU2_TIORH_4_IOB (0xF0u)
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| 75 |
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| 76 | #define MTU2_TIORL_4_IOC (0x0Fu)
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| 77 | #define MTU2_TIORL_4_IOD (0xF0u)
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| 78 |
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| 79 | #define MTU2_TIER_3_TGIEC (0x04u)
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| 80 | #define MTU2_TIER_3_TGIED (0x08u)
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| 81 |
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| 82 | #define MTU2_TIER_4_TGIEC (0x04u)
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| 83 | #define MTU2_TIER_4_TGIED (0x08u)
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| 84 | #define MTU2_TIER_4_TTGE2 (0x40u)
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| 85 |
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| 86 | #define MTU2_TOER_OE3B (0x01u)
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| 87 | #define MTU2_TOER_OE4A (0x02u)
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| 88 | #define MTU2_TOER_OE4B (0x04u)
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| 89 | #define MTU2_TOER_OE3D (0x08u)
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| 90 | #define MTU2_TOER_OE4C (0x10u)
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| 91 | #define MTU2_TOER_OE4D (0x20u)
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| 92 |
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| 93 | #define MTU2_TGCR_UF (0x01u)
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| 94 | #define MTU2_TGCR_VF (0x02u)
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| 95 | #define MTU2_TGCR_WF (0x04u)
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| 96 | #define MTU2_TGCR_FB (0x08u)
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| 97 | #define MTU2_TGCR_P (0x10u)
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| 98 | #define MTU2_TGCR_N (0x20u)
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| 99 | #define MTU2_TGCR_BDC (0x40u)
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| 100 |
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| 101 | #define MTU2_TOCR1_OLSP (0x01u)
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| 102 | #define MTU2_TOCR1_OLSN (0x02u)
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| 103 | #define MTU2_TOCR1_TOCS (0x04u)
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| 104 | #define MTU2_TOCR1_TOCL (0x08u)
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| 105 | #define MTU2_TOCR1_PSYE (0x40u)
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| 106 |
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| 107 | #define MTU2_TOCR2_OLS1P (0x01u)
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| 108 | #define MTU2_TOCR2_OLS1N (0x02u)
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| 109 | #define MTU2_TOCR2_OLS2P (0x04u)
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| 110 | #define MTU2_TOCR2_OLS2N (0x08u)
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| 111 | #define MTU2_TOCR2_OLS3P (0x10u)
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| 112 | #define MTU2_TOCR2_OLS3N (0x20u)
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| 113 | #define MTU2_TOCR2_BF (0xC0u)
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| 114 |
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| 115 | #define MTU2_TCDR_D (0xFFFFu)
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| 116 |
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| 117 | #define MTU2_TDDR_D (0xFFFFu)
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| 118 |
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| 119 | #define MTU2_TCNTS_D (0xFFFFu)
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| 120 |
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| 121 | #define MTU2_TCBR_D (0xFFFFu)
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| 122 |
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| 123 | #define MTU2_TGRC_3_D (0xFFFFu)
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| 124 |
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| 125 | #define MTU2_TGRD_3_D (0xFFFFu)
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| 126 |
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| 127 | #define MTU2_TGRC_4_D (0xFFFFu)
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| 128 |
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| 129 | #define MTU2_TGRD_4_D (0xFFFFu)
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| 130 |
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| 131 | #define MTU2_TSR_3_TGFC (0x04u)
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| 132 | #define MTU2_TSR_3_TGFD (0x08u)
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| 133 | #define MTU2_TSR_3_TCFD (0x80u)
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| 134 |
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| 135 | #define MTU2_TSR_4_TGFC (0x04u)
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| 136 | #define MTU2_TSR_4_TGFD (0x08u)
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| 137 | #define MTU2_TSR_4_TCFD (0x80u)
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| 138 |
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| 139 | #define MTU2_TITCR_4VCOR (0x07u)
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| 140 | #define MTU2_TITCR_T4VEN (0x08u)
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| 141 | #define MTU2_TITCR_3ACOR (0x70u)
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| 142 | #define MTU2_TITCR_T3AEN (0x80u)
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| 143 |
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| 144 | #define MTU2_TITCNT_4VCNT (0x07u)
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| 145 | #define MTU2_TITCNT_3ACNT (0x70u)
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| 146 |
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| 147 | #define MTU2_TBTER_BTE (0x03u)
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| 148 |
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| 149 | #define MTU2_TDER_TDER (0x01u)
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| 150 |
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| 151 | #define MTU2_TOLBR_OLS1P (0x01u)
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| 152 | #define MTU2_TOLBR_OLS1N (0x02u)
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| 153 | #define MTU2_TOLBR_OLS2P (0x04u)
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| 154 | #define MTU2_TOLBR_OLS2N (0x08u)
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| 155 | #define MTU2_TOLBR_OLS3P (0x10u)
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| 156 | #define MTU2_TOLBR_OLS3N (0x20u)
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| 157 |
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| 158 | #define MTU2_TBTM_3_TTSA (0x01u)
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| 159 | #define MTU2_TBTM_3_TTSB (0x02u)
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| 160 |
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| 161 | #define MTU2_TBTM_4_TTSA (0x01u)
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| 162 | #define MTU2_TBTM_4_TTSB (0x02u)
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| 163 |
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| 164 | #define MTU2_TADCR_ITB4VE (0x0001u)
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| 165 | #define MTU2_TADCR_ITB3AE (0x0002u)
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| 166 | #define MTU2_TADCR_ITA4VE (0x0004u)
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| 167 | #define MTU2_TADCR_ITA3AE (0x0008u)
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| 168 | #define MTU2_TADCR_DT4BE (0x0010u)
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| 169 | #define MTU2_TADCR_UT4BE (0x0020u)
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| 170 | #define MTU2_TADCR_DT4AE (0x0040u)
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| 171 | #define MTU2_TADCR_UT4AE (0x0080u)
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| 172 | #define MTU2_TADCR_BF (0xC000u)
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| 173 |
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| 174 | #define MTU2_TADCORA_4_D (0xFFFFu)
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| 175 |
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| 176 | #define MTU2_TADCORB_4_D (0xFFFFu)
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| 177 |
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| 178 | #define MTU2_TADCOBRA_4_D (0xFFFFu)
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| 179 |
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| 180 | #define MTU2_TADCOBRB_4_D (0xFFFFu)
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| 181 |
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| 182 | #define MTU2_TWCR_WRE (0x01u)
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| 183 | #define MTU2_TWCR_CCE (0x80u)
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| 184 |
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| 185 | #define MTU2_TSTR_CST0 (0x01u)
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| 186 | #define MTU2_TSTR_CST1 (0x02u)
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| 187 | #define MTU2_TSTR_CST2 (0x04u)
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| 188 | #define MTU2_TSTR_CST3 (0x40u)
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| 189 | #define MTU2_TSTR_CST4 (0x80u)
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| 190 |
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| 191 | #define MTU2_TSYR_SYNC0 (0x01u)
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| 192 | #define MTU2_TSYR_SYNC1 (0x02u)
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| 193 | #define MTU2_TSYR_SYNC2 (0x04u)
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| 194 | #define MTU2_TSYR_SYNC3 (0x40u)
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| 195 | #define MTU2_TSYR_SYNC4 (0x80u)
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| 196 |
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| 197 | #define MTU2_TRWER_RWE (0x01u)
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| 198 |
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| 199 | #define MTU2_TMDR_0_BFA (0x10u)
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| 200 | #define MTU2_TMDR_0_BFB (0x20u)
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| 201 | #define MTU2_TMDR_0_BFE (0x40u)
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| 202 |
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| 203 | #define MTU2_TIORH_0_IOA (0x0Fu)
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| 204 | #define MTU2_TIORH_0_IOB (0xF0u)
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| 205 |
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| 206 | #define MTU2_TIORL_0_IOC (0x0Fu)
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| 207 | #define MTU2_TIORL_0_IOD (0xF0u)
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| 208 |
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| 209 | #define MTU2_TIER_0_TGIEC (0x04u)
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| 210 | #define MTU2_TIER_0_TGIED (0x08u)
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| 211 |
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| 212 | #define MTU2_TSR_0_TGFC (0x04u)
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| 213 | #define MTU2_TSR_0_TGFD (0x08u)
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| 214 |
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| 215 | #define MTU2_TGRC_0_D (0xFFFFu)
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| 216 |
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| 217 | #define MTU2_TGRD_0_D (0xFFFFu)
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| 218 |
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| 219 | #define MTU2_TGRE_0_D (0xFFFFu)
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| 220 |
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| 221 | #define MTU2_TGRF_0_D (0xFFFFu)
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| 222 |
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| 223 | #define MTU2_TIER2_0_TGIEE (0x01u)
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| 224 | #define MTU2_TIER2_0_TGIEF (0x02u)
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| 225 |
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| 226 | #define MTU2_TSR2_0_TGFE (0x01u)
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| 227 | #define MTU2_TSR2_0_TGFF (0x02u)
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| 228 |
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| 229 | #define MTU2_TBTM_0_TTSA (0x01u)
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| 230 | #define MTU2_TBTM_0_TTSB (0x02u)
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| 231 | #define MTU2_TBTM_0_TTSE (0x04u)
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| 232 |
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| 233 | #define MTU2_TIOR_1_IOA (0x0Fu)
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| 234 | #define MTU2_TIOR_1_IOB (0xF0u)
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| 235 |
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| 236 | #define MTU2_TIER_1_TCIEU (0x20u)
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| 237 |
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| 238 | #define MTU2_TSR_1_TCFU (0x20u)
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| 239 | #define MTU2_TSR_1_TCFD (0x80u)
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| 240 |
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| 241 | #define MTU2_TICCR_I1AE (0x01u)
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| 242 | #define MTU2_TICCR_I1BE (0x02u)
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| 243 | #define MTU2_TICCR_I2AE (0x04u)
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| 244 | #define MTU2_TICCR_I2BE (0x08u)
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| 245 |
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| 246 |
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| 247 | /* ==== Shift values for IO registers ==== */
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| 248 | #define MTU2_TCR_n_TPSC_SHIFT (0u)
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| 249 | #define MTU2_TCR_n_CKEG_SHIFT (3u)
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| 250 | #define MTU2_TCR_n_CCLR_SHIFT (5u)
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| 251 |
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| 252 | #define MTU2_TMDR_n_MD_SHIFT (0u)
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| 253 |
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| 254 | #define MTU2_TIOR_2_IOA_SHIFT (0u)
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| 255 | #define MTU2_TIOR_2_IOB_SHIFT (4u)
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| 256 |
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| 257 | #define MTU2_TIER_n_TGIEA_SHIFT (0u)
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| 258 | #define MTU2_TIER_n_TGIEB_SHIFT (1u)
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| 259 | #define MTU2_TIER_n_TCIEV_SHIFT (4u)
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| 260 | #define MTU2_TIER_2_TCIEU_SHIFT (5u)
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| 261 | #define MTU2_TIER_n_TTGE_SHIFT (7u)
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| 262 |
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| 263 | #define MTU2_TSR_n_TGFA_SHIFT (0u)
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| 264 | #define MTU2_TSR_n_TGFB_SHIFT (1u)
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| 265 | #define MTU2_TSR_n_TCFV_SHIFT (4u)
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| 266 | #define MTU2_TSR_2_TCFU_SHIFT (5u)
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| 267 | #define MTU2_TSR_2_TCFD_SHIFT (7u)
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| 268 |
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| 269 | #define MTU2_TCNT_n_D_SHIFT (0u)
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| 270 |
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| 271 | #define MTU2_TGRA_n_D_SHIFT (0u)
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| 272 |
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| 273 | #define MTU2_TGRB_n_D_SHIFT (0u)
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| 274 |
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| 275 | #define MTU2_TMDR_3_BFA_SHIFT (4u)
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| 276 | #define MTU2_TMDR_3_BFB_SHIFT (5u)
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| 277 |
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| 278 | #define MTU2_TMDR_4_BFA_SHIFT (4u)
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| 279 | #define MTU2_TMDR_4_BFB_SHIFT (5u)
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| 280 |
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| 281 | #define MTU2_TIORH_3_IOA_SHIFT (0u)
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| 282 | #define MTU2_TIORH_3_IOB_SHIFT (4u)
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| 283 |
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| 284 | #define MTU2_TIORL_3_IOC_SHIFT (0u)
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| 285 | #define MTU2_TIORL_3_IOD_SHIFT (4u)
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| 286 |
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| 287 | #define MTU2_TIORH_4_IOA_SHIFT (0u)
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| 288 | #define MTU2_TIORH_4_IOB_SHIFT (4u)
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| 289 |
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| 290 | #define MTU2_TIORL_4_IOC_SHIFT (0u)
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| 291 | #define MTU2_TIORL_4_IOD_SHIFT (4u)
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| 292 |
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| 293 | #define MTU2_TIER_3_TGIEC_SHIFT (2u)
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| 294 | #define MTU2_TIER_3_TGIED_SHIFT (3u)
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| 295 |
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| 296 | #define MTU2_TIER_4_TGIEC_SHIFT (2u)
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| 297 | #define MTU2_TIER_4_TGIED_SHIFT (3u)
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| 298 | #define MTU2_TIER_4_TTGE2_SHIFT (6u)
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| 299 |
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| 300 | #define MTU2_TOER_OE3B_SHIFT (0u)
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| 301 | #define MTU2_TOER_OE4A_SHIFT (1u)
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| 302 | #define MTU2_TOER_OE4B_SHIFT (2u)
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| 303 | #define MTU2_TOER_OE3D_SHIFT (3u)
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| 304 | #define MTU2_TOER_OE4C_SHIFT (4u)
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| 305 | #define MTU2_TOER_OE4D_SHIFT (5u)
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| 306 |
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| 307 | #define MTU2_TGCR_UF_SHIFT (0u)
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| 308 | #define MTU2_TGCR_VF_SHIFT (1u)
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| 309 | #define MTU2_TGCR_WF_SHIFT (2u)
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| 310 | #define MTU2_TGCR_FB_SHIFT (3u)
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| 311 | #define MTU2_TGCR_P_SHIFT (4u)
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| 312 | #define MTU2_TGCR_N_SHIFT (5u)
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| 313 | #define MTU2_TGCR_BDC_SHIFT (6u)
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| 314 |
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| 315 | #define MTU2_TOCR1_OLSP_SHIFT (0u)
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| 316 | #define MTU2_TOCR1_OLSN_SHIFT (1u)
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| 317 | #define MTU2_TOCR1_TOCS_SHIFT (2u)
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| 318 | #define MTU2_TOCR1_TOCL_SHIFT (3u)
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| 319 | #define MTU2_TOCR1_PSYE_SHIFT (6u)
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| 320 |
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| 321 | #define MTU2_TOCR2_OLS1P_SHIFT (0u)
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| 322 | #define MTU2_TOCR2_OLS1N_SHIFT (1u)
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| 323 | #define MTU2_TOCR2_OLS2P_SHIFT (2u)
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| 324 | #define MTU2_TOCR2_OLS2N_SHIFT (3u)
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| 325 | #define MTU2_TOCR2_OLS3P_SHIFT (4u)
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| 326 | #define MTU2_TOCR2_OLS3N_SHIFT (5u)
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| 327 | #define MTU2_TOCR2_BF_SHIFT (6u)
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| 328 |
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| 329 | #define MTU2_TCDR_D_SHIFT (0u)
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| 330 |
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| 331 | #define MTU2_TDDR_D_SHIFT (0u)
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| 332 |
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| 333 | #define MTU2_TCNTS_D_SHIFT (0u)
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| 334 |
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| 335 | #define MTU2_TCBR_D_SHIFT (0u)
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| 336 |
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| 337 | #define MTU2_TGRC_3_D_SHIFT (0u)
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| 338 |
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| 339 | #define MTU2_TGRD_3_D_SHIFT (0u)
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| 340 |
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| 341 | #define MTU2_TGRC_4_D_SHIFT (0u)
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| 342 |
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| 343 | #define MTU2_TGRD_4_D_SHIFT (0u)
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| 344 |
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| 345 | #define MTU2_TSR_3_TGFC_SHIFT (2u)
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| 346 | #define MTU2_TSR_3_TGFD_SHIFT (3u)
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| 347 | #define MTU2_TSR_3_TCFD_SHIFT (7u)
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| 348 |
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| 349 | #define MTU2_TSR_4_TGFC_SHIFT (2u)
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| 350 | #define MTU2_TSR_4_TGFD_SHIFT (3u)
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| 351 | #define MTU2_TSR_4_TCFD_SHIFT (7u)
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| 352 |
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| 353 | #define MTU2_TITCR_4VCOR_SHIFT (0u)
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| 354 | #define MTU2_TITCR_T4VEN_SHIFT (3u)
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| 355 | #define MTU2_TITCR_3ACOR_SHIFT (4u)
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| 356 | #define MTU2_TITCR_T3AEN_SHIFT (7u)
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| 357 |
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| 358 | #define MTU2_TITCNT_4VCNT_SHIFT (0u)
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| 359 | #define MTU2_TITCNT_3ACNT_SHIFT (4u)
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| 360 |
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| 361 | #define MTU2_TBTER_BTE_SHIFT (0u)
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| 362 |
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| 363 | #define MTU2_TDER_TDER_SHIFT (0u)
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| 364 |
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| 365 | #define MTU2_TOLBR_OLS1P_SHIFT (0u)
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| 366 | #define MTU2_TOLBR_OLS1N_SHIFT (1u)
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| 367 | #define MTU2_TOLBR_OLS2P_SHIFT (2u)
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| 368 | #define MTU2_TOLBR_OLS2N_SHIFT (3u)
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| 369 | #define MTU2_TOLBR_OLS3P_SHIFT (4u)
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| 370 | #define MTU2_TOLBR_OLS3N_SHIFT (5u)
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| 371 |
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| 372 | #define MTU2_TBTM_3_TTSA_SHIFT (0u)
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| 373 | #define MTU2_TBTM_3_TTSB_SHIFT (1u)
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| 374 |
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| 375 | #define MTU2_TBTM_4_TTSA_SHIFT (0u)
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| 376 | #define MTU2_TBTM_4_TTSB_SHIFT (1u)
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| 377 |
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| 378 | #define MTU2_TADCR_ITB4VE_SHIFT (0u)
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| 379 | #define MTU2_TADCR_ITB3AE_SHIFT (1u)
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| 380 | #define MTU2_TADCR_ITA4VE_SHIFT (2u)
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| 381 | #define MTU2_TADCR_ITA3AE_SHIFT (3u)
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| 382 | #define MTU2_TADCR_DT4BE_SHIFT (4u)
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| 383 | #define MTU2_TADCR_UT4BE_SHIFT (5u)
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| 384 | #define MTU2_TADCR_DT4AE_SHIFT (6u)
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| 385 | #define MTU2_TADCR_UT4AE_SHIFT (7u)
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| 386 | #define MTU2_TADCR_BF_SHIFT (14u)
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| 387 |
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| 388 | #define MTU2_TADCORA_4_D_SHIFT (0u)
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| 389 |
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| 390 | #define MTU2_TADCORB_4_D_SHIFT (0u)
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| 391 |
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| 392 | #define MTU2_TADCOBRA_4_D_SHIFT (0u)
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| 393 |
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| 394 | #define MTU2_TADCOBRB_4_D_SHIFT (0u)
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| 395 |
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| 396 | #define MTU2_TWCR_WRE_SHIFT (0u)
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| 397 | #define MTU2_TWCR_CCE_SHIFT (7u)
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| 398 |
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| 399 | #define MTU2_TSTR_CST0_SHIFT (0u)
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| 400 | #define MTU2_TSTR_CST1_SHIFT (1u)
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| 401 | #define MTU2_TSTR_CST2_SHIFT (2u)
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| 402 | #define MTU2_TSTR_CST3_SHIFT (6u)
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| 403 | #define MTU2_TSTR_CST4_SHIFT (7u)
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| 404 |
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| 405 | #define MTU2_TSYR_SYNC0_SHIFT (0u)
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| 406 | #define MTU2_TSYR_SYNC1_SHIFT (1u)
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| 407 | #define MTU2_TSYR_SYNC2_SHIFT (2u)
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| 408 | #define MTU2_TSYR_SYNC3_SHIFT (6u)
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| 409 | #define MTU2_TSYR_SYNC4_SHIFT (7u)
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| 410 |
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| 411 | #define MTU2_TRWER_RWE_SHIFT (0u)
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| 412 |
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| 413 | #define MTU2_TMDR_0_BFA_SHIFT (4u)
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| 414 | #define MTU2_TMDR_0_BFB_SHIFT (5u)
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| 415 | #define MTU2_TMDR_0_BFE_SHIFT (6u)
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| 416 |
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| 417 | #define MTU2_TIORH_0_IOA_SHIFT (0u)
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| 418 | #define MTU2_TIORH_0_IOB_SHIFT (4u)
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| 419 |
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| 420 | #define MTU2_TIORL_0_IOC_SHIFT (0u)
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| 421 | #define MTU2_TIORL_0_IOD_SHIFT (4u)
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| 422 |
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| 423 | #define MTU2_TIER_0_TGIEC_SHIFT (2u)
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| 424 | #define MTU2_TIER_0_TGIED_SHIFT (3u)
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| 425 |
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| 426 | #define MTU2_TSR_0_TGFC_SHIFT (2u)
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| 427 | #define MTU2_TSR_0_TGFD_SHIFT (3u)
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| 428 |
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| 429 | #define MTU2_TGRC_0_D_SHIFT (0u)
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| 430 |
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| 431 | #define MTU2_TGRD_0_D_SHIFT (0u)
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| 432 |
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| 433 | #define MTU2_TGRE_0_D_SHIFT (0u)
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| 434 |
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| 435 | #define MTU2_TGRF_0_D_SHIFT (0u)
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| 436 |
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| 437 | #define MTU2_TIER2_0_TGIEE_SHIFT (0u)
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| 438 | #define MTU2_TIER2_0_TGIEF_SHIFT (1u)
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| 439 |
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| 440 | #define MTU2_TSR2_0_TGFE_SHIFT (0u)
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| 441 | #define MTU2_TSR2_0_TGFF_SHIFT (1u)
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| 442 |
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| 443 | #define MTU2_TBTM_0_TTSA_SHIFT (0u)
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| 444 | #define MTU2_TBTM_0_TTSB_SHIFT (1u)
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| 445 | #define MTU2_TBTM_0_TTSE_SHIFT (2u)
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| 446 |
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| 447 | #define MTU2_TIOR_1_IOA_SHIFT (0u)
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| 448 | #define MTU2_TIOR_1_IOB_SHIFT (4u)
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| 449 |
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| 450 | #define MTU2_TIER_1_TCIEU_SHIFT (5u)
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| 451 |
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| 452 | #define MTU2_TSR_1_TCFU_SHIFT (5u)
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| 453 | #define MTU2_TSR_1_TCFD_SHIFT (7u)
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| 454 |
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| 455 | #define MTU2_TICCR_I1AE_SHIFT (0u)
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| 456 | #define MTU2_TICCR_I1BE_SHIFT (1u)
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| 457 | #define MTU2_TICCR_I2AE_SHIFT (2u)
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| 458 | #define MTU2_TICCR_I2BE_SHIFT (3u)
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| 459 |
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| 460 |
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| 461 | #endif /* MTU2_IOBITMASK_H */
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| 462 | /* End of File */
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