1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer
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21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : dmac_iobitmask.h
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25 | * $Rev: 1114 $
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26 | * $Date:: 2014-07-09 14:56:39 +0900#$
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27 | * Description : DMAC register define header
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28 | *******************************************************************************/
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29 | #ifndef DMAC_IOBITMASK_H
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30 | #define DMAC_IOBITMASK_H
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31 |
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32 |
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33 | /* ==== Mask values for IO registers ==== */
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34 | /* ---- DMAC0 ---- */
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35 | #define DMAC0_N0SA_n_SA (0xFFFFFFFFuL)
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36 |
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37 | #define DMAC0_N0DA_n_DA (0xFFFFFFFFuL)
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38 |
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39 | #define DMAC0_N0TB_n_TB (0xFFFFFFFFuL)
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40 |
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41 | #define DMAC0_N1SA_n_SA (0xFFFFFFFFuL)
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42 |
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43 | #define DMAC0_N1DA_n_DA (0xFFFFFFFFuL)
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44 |
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45 | #define DMAC0_N1TB_n_TB (0xFFFFFFFFuL)
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46 |
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47 | #define DMAC0_CRSA_n_CRSA (0xFFFFFFFFuL)
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48 |
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49 | #define DMAC0_CRDA_n_CRDA (0xFFFFFFFFuL)
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50 |
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51 | #define DMAC0_CRTB_n_CRTB (0xFFFFFFFFuL)
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52 |
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53 | #define DMAC0_CHSTAT_n_EN (0x00000001uL)
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54 | #define DMAC0_CHSTAT_n_RQST (0x00000002uL)
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55 | #define DMAC0_CHSTAT_n_TACT (0x00000004uL)
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56 | #define DMAC0_CHSTAT_n_SUS (0x00000008uL)
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57 | #define DMAC0_CHSTAT_n_ER (0x00000010uL)
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58 | #define DMAC0_CHSTAT_n_END (0x00000020uL)
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59 | #define DMAC0_CHSTAT_n_TC (0x00000040uL)
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60 | #define DMAC0_CHSTAT_n_SR (0x00000080uL)
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61 | #define DMAC0_CHSTAT_n_DL (0x00000100uL)
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62 | #define DMAC0_CHSTAT_n_DW (0x00000200uL)
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63 | #define DMAC0_CHSTAT_n_DER (0x00000400uL)
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64 | #define DMAC0_CHSTAT_n_MODE (0x00000800uL)
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65 | #define DMAC0_CHSTAT_n_INTMSK (0x00010000uL)
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66 |
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67 | #define DMAC0_CHCTRL_n_SETEN (0x00000001uL)
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68 | #define DMAC0_CHCTRL_n_CLREN (0x00000002uL)
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69 | #define DMAC0_CHCTRL_n_STG (0x00000004uL)
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70 | #define DMAC0_CHCTRL_n_SWRST (0x00000008uL)
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71 | #define DMAC0_CHCTRL_n_CLRRQ (0x00000010uL)
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72 | #define DMAC0_CHCTRL_n_CLREND (0x00000020uL)
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73 | #define DMAC0_CHCTRL_n_CLRTC (0x00000040uL)
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74 | #define DMAC0_CHCTRL_n_SETSUS (0x00000100uL)
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75 | #define DMAC0_CHCTRL_n_CLRSUS (0x00000200uL)
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76 | #define DMAC0_CHCTRL_n_SETINTMSK (0x00010000uL)
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77 | #define DMAC0_CHCTRL_n_CLRINTMSK (0x00020000uL)
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78 |
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79 | #define DMAC0_CHCFG_n_SEL (0x00000007uL)
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80 | #define DMAC0_CHCFG_n_REQD (0x00000008uL)
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81 | #define DMAC0_CHCFG_n_LOEN (0x00000010uL)
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82 | #define DMAC0_CHCFG_n_HIEN (0x00000020uL)
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83 | #define DMAC0_CHCFG_n_LVL (0x00000040uL)
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84 | #define DMAC0_CHCFG_n_AM (0x00000700uL)
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85 | #define DMAC0_CHCFG_n_SDS (0x0000F000uL)
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86 | #define DMAC0_CHCFG_n_DDS (0x000F0000uL)
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87 | #define DMAC0_CHCFG_n_SAD (0x00100000uL)
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88 | #define DMAC0_CHCFG_n_DAD (0x00200000uL)
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89 | #define DMAC0_CHCFG_n_TM (0x00400000uL)
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90 | #define DMAC0_CHCFG_n_DEM (0x01000000uL)
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91 | #define DMAC0_CHCFG_n_TCM (0x02000000uL)
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92 | #define DMAC0_CHCFG_n_SBE (0x08000000uL)
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93 | #define DMAC0_CHCFG_n_RSEL (0x10000000uL)
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94 | #define DMAC0_CHCFG_n_RSW (0x20000000uL)
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95 | #define DMAC0_CHCFG_n_REN (0x40000000uL)
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96 | #define DMAC0_CHCFG_n_DMS (0x80000000uL)
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97 |
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98 | #define DMAC0_CHITVL_n_ITVL (0x0000FFFFuL)
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99 |
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100 | #define DMAC0_CHEXT_n_SCA (0x000000F0uL)
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101 | #define DMAC0_CHEXT_n_DCA (0x0000F000uL)
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102 |
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103 | #define DMAC0_NXLA_n_NXLA (0xFFFFFFFFuL)
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104 |
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105 | #define DMAC0_CRLA_n_CRLA (0xFFFFFFFFuL)
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106 |
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107 | /* ---- DMAC1 ---- */
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108 | #define DMAC1_N0SA_n_SA (0xFFFFFFFFuL)
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109 |
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110 | #define DMAC1_N0DA_n_DA (0xFFFFFFFFuL)
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111 |
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112 | #define DMAC1_N0TB_n_TB (0xFFFFFFFFuL)
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113 |
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114 | #define DMAC1_N1SA_n_SA (0xFFFFFFFFuL)
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115 |
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116 | #define DMAC1_N1DA_n_DA (0xFFFFFFFFuL)
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117 |
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118 | #define DMAC1_N1TB_n_TB (0xFFFFFFFFuL)
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119 |
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120 | #define DMAC1_CRSA_n_CRSA (0xFFFFFFFFuL)
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121 |
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122 | #define DMAC1_CRDA_n_CRDA (0xFFFFFFFFuL)
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123 |
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124 | #define DMAC1_CRTB_n_CRTB (0xFFFFFFFFuL)
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125 |
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126 | #define DMAC1_CHSTAT_n_EN (0x00000001uL)
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127 | #define DMAC1_CHSTAT_n_RQST (0x00000002uL)
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128 | #define DMAC1_CHSTAT_n_TACT (0x00000004uL)
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129 | #define DMAC1_CHSTAT_n_SUS (0x00000008uL)
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130 | #define DMAC1_CHSTAT_n_ER (0x00000010uL)
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131 | #define DMAC1_CHSTAT_n_END (0x00000020uL)
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132 | #define DMAC1_CHSTAT_n_TC (0x00000040uL)
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133 | #define DMAC1_CHSTAT_n_SR (0x00000080uL)
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134 | #define DMAC1_CHSTAT_n_DL (0x00000100uL)
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135 | #define DMAC1_CHSTAT_n_DW (0x00000200uL)
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136 | #define DMAC1_CHSTAT_n_DER (0x00000400uL)
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137 | #define DMAC1_CHSTAT_n_MODE (0x00000800uL)
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138 | #define DMAC1_CHSTAT_n_INTMSK (0x00010000uL)
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139 |
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140 | #define DMAC1_CHCTRL_n_SETEN (0x00000001uL)
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141 | #define DMAC1_CHCTRL_n_CLREN (0x00000002uL)
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142 | #define DMAC1_CHCTRL_n_STG (0x00000004uL)
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143 | #define DMAC1_CHCTRL_n_SWRST (0x00000008uL)
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144 | #define DMAC1_CHCTRL_n_CLRRQ (0x00000010uL)
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145 | #define DMAC1_CHCTRL_n_CLREND (0x00000020uL)
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146 | #define DMAC1_CHCTRL_n_CLRTC (0x00000040uL)
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147 | #define DMAC1_CHCTRL_n_SETSUS (0x00000100uL)
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148 | #define DMAC1_CHCTRL_n_CLRSUS (0x00000200uL)
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149 | #define DMAC1_CHCTRL_n_SETINTMSK (0x00010000uL)
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150 | #define DMAC1_CHCTRL_n_CLRINTMSK (0x00020000uL)
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151 |
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152 | #define DMAC1_CHCFG_n_SEL (0x00000007uL)
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153 | #define DMAC1_CHCFG_n_REQD (0x00000008uL)
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154 | #define DMAC1_CHCFG_n_LOEN (0x00000010uL)
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155 | #define DMAC1_CHCFG_n_HIEN (0x00000020uL)
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156 | #define DMAC1_CHCFG_n_LVL (0x00000040uL)
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157 | #define DMAC1_CHCFG_n_AM (0x00000700uL)
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158 | #define DMAC1_CHCFG_n_SDS (0x0000F000uL)
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159 | #define DMAC1_CHCFG_n_DDS (0x000F0000uL)
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160 | #define DMAC1_CHCFG_n_SAD (0x00100000uL)
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161 | #define DMAC1_CHCFG_n_DAD (0x00200000uL)
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162 | #define DMAC1_CHCFG_n_TM (0x00400000uL)
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163 | #define DMAC1_CHCFG_n_DEM (0x01000000uL)
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164 | #define DMAC1_CHCFG_n_TCM (0x02000000uL)
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165 | #define DMAC1_CHCFG_n_SBE (0x08000000uL)
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166 | #define DMAC1_CHCFG_n_RSEL (0x10000000uL)
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167 | #define DMAC1_CHCFG_n_RSW (0x20000000uL)
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168 | #define DMAC1_CHCFG_n_REN (0x40000000uL)
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169 | #define DMAC1_CHCFG_n_DMS (0x80000000uL)
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170 |
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171 | #define DMAC1_CHITVL_n_ITVL (0x0000FFFFuL)
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172 |
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173 | #define DMAC1_CHEXT_n_SCA (0x000000F0uL)
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174 | #define DMAC1_CHEXT_n_DCA (0x0000F000uL)
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175 |
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176 | #define DMAC1_NXLA_n_NXLA (0xFFFFFFFFuL)
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177 |
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178 | #define DMAC1_CRLA_n_CRLA (0xFFFFFFFFuL)
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179 |
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180 | /* ---- DMAC2 ---- */
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181 | #define DMAC2_N0SA_n_SA (0xFFFFFFFFuL)
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182 |
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183 | #define DMAC2_N0DA_n_DA (0xFFFFFFFFuL)
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184 |
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185 | #define DMAC2_N0TB_n_TB (0xFFFFFFFFuL)
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186 |
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187 | #define DMAC2_N1SA_n_SA (0xFFFFFFFFuL)
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188 |
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189 | #define DMAC2_N1DA_n_DA (0xFFFFFFFFuL)
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190 |
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191 | #define DMAC2_N1TB_n_TB (0xFFFFFFFFuL)
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192 |
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193 | #define DMAC2_CRSA_n_CRSA (0xFFFFFFFFuL)
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194 |
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195 | #define DMAC2_CRDA_n_CRDA (0xFFFFFFFFuL)
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196 |
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197 | #define DMAC2_CRTB_n_CRTB (0xFFFFFFFFuL)
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198 |
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199 | #define DMAC2_CHSTAT_n_EN (0x00000001uL)
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200 | #define DMAC2_CHSTAT_n_RQST (0x00000002uL)
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201 | #define DMAC2_CHSTAT_n_TACT (0x00000004uL)
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202 | #define DMAC2_CHSTAT_n_SUS (0x00000008uL)
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203 | #define DMAC2_CHSTAT_n_ER (0x00000010uL)
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204 | #define DMAC2_CHSTAT_n_END (0x00000020uL)
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205 | #define DMAC2_CHSTAT_n_TC (0x00000040uL)
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206 | #define DMAC2_CHSTAT_n_SR (0x00000080uL)
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207 | #define DMAC2_CHSTAT_n_DL (0x00000100uL)
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208 | #define DMAC2_CHSTAT_n_DW (0x00000200uL)
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209 | #define DMAC2_CHSTAT_n_DER (0x00000400uL)
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210 | #define DMAC2_CHSTAT_n_MODE (0x00000800uL)
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211 | #define DMAC2_CHSTAT_n_INTMSK (0x00010000uL)
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212 |
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213 | #define DMAC2_CHCTRL_n_SETEN (0x00000001uL)
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214 | #define DMAC2_CHCTRL_n_CLREN (0x00000002uL)
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215 | #define DMAC2_CHCTRL_n_STG (0x00000004uL)
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216 | #define DMAC2_CHCTRL_n_SWRST (0x00000008uL)
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217 | #define DMAC2_CHCTRL_n_CLRRQ (0x00000010uL)
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218 | #define DMAC2_CHCTRL_n_CLREND (0x00000020uL)
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219 | #define DMAC2_CHCTRL_n_CLRTC (0x00000040uL)
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220 | #define DMAC2_CHCTRL_n_SETSUS (0x00000100uL)
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221 | #define DMAC2_CHCTRL_n_CLRSUS (0x00000200uL)
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222 | #define DMAC2_CHCTRL_n_SETINTMSK (0x00010000uL)
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223 | #define DMAC2_CHCTRL_n_CLRINTMSK (0x00020000uL)
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224 |
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225 | #define DMAC2_CHCFG_n_SEL (0x00000007uL)
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226 | #define DMAC2_CHCFG_n_REQD (0x00000008uL)
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227 | #define DMAC2_CHCFG_n_LOEN (0x00000010uL)
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228 | #define DMAC2_CHCFG_n_HIEN (0x00000020uL)
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229 | #define DMAC2_CHCFG_n_LVL (0x00000040uL)
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230 | #define DMAC2_CHCFG_n_AM (0x00000700uL)
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231 | #define DMAC2_CHCFG_n_SDS (0x0000F000uL)
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232 | #define DMAC2_CHCFG_n_DDS (0x000F0000uL)
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233 | #define DMAC2_CHCFG_n_SAD (0x00100000uL)
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234 | #define DMAC2_CHCFG_n_DAD (0x00200000uL)
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235 | #define DMAC2_CHCFG_n_TM (0x00400000uL)
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236 | #define DMAC2_CHCFG_n_DEM (0x01000000uL)
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237 | #define DMAC2_CHCFG_n_TCM (0x02000000uL)
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238 | #define DMAC2_CHCFG_n_SBE (0x08000000uL)
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239 | #define DMAC2_CHCFG_n_RSEL (0x10000000uL)
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240 | #define DMAC2_CHCFG_n_RSW (0x20000000uL)
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241 | #define DMAC2_CHCFG_n_REN (0x40000000uL)
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242 | #define DMAC2_CHCFG_n_DMS (0x80000000uL)
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243 |
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244 | #define DMAC2_CHITVL_n_ITVL (0x0000FFFFuL)
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245 |
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246 | #define DMAC2_CHEXT_n_SCA (0x000000F0uL)
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247 | #define DMAC2_CHEXT_n_DCA (0x0000F000uL)
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248 |
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249 | #define DMAC2_NXLA_n_NXLA (0xFFFFFFFFuL)
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250 |
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251 | #define DMAC2_CRLA_n_CRLA (0xFFFFFFFFuL)
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252 |
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253 | /* ---- DMAC3 ---- */
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254 | #define DMAC3_N0SA_n_SA (0xFFFFFFFFuL)
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255 |
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256 | #define DMAC3_N0DA_n_DA (0xFFFFFFFFuL)
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257 |
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258 | #define DMAC3_N0TB_n_TB (0xFFFFFFFFuL)
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259 |
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260 | #define DMAC3_N1SA_n_SA (0xFFFFFFFFuL)
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261 |
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262 | #define DMAC3_N1DA_n_DA (0xFFFFFFFFuL)
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263 |
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264 | #define DMAC3_N1TB_n_TB (0xFFFFFFFFuL)
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265 |
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266 | #define DMAC3_CRSA_n_CRSA (0xFFFFFFFFuL)
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267 |
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268 | #define DMAC3_CRDA_n_CRDA (0xFFFFFFFFuL)
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269 |
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270 | #define DMAC3_CRTB_n_CRTB (0xFFFFFFFFuL)
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271 |
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272 | #define DMAC3_CHSTAT_n_EN (0x00000001uL)
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273 | #define DMAC3_CHSTAT_n_RQST (0x00000002uL)
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274 | #define DMAC3_CHSTAT_n_TACT (0x00000004uL)
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275 | #define DMAC3_CHSTAT_n_SUS (0x00000008uL)
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276 | #define DMAC3_CHSTAT_n_ER (0x00000010uL)
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277 | #define DMAC3_CHSTAT_n_END (0x00000020uL)
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278 | #define DMAC3_CHSTAT_n_TC (0x00000040uL)
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279 | #define DMAC3_CHSTAT_n_SR (0x00000080uL)
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280 | #define DMAC3_CHSTAT_n_DL (0x00000100uL)
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281 | #define DMAC3_CHSTAT_n_DW (0x00000200uL)
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282 | #define DMAC3_CHSTAT_n_DER (0x00000400uL)
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283 | #define DMAC3_CHSTAT_n_MODE (0x00000800uL)
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284 | #define DMAC3_CHSTAT_n_INTMSK (0x00010000uL)
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285 |
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286 | #define DMAC3_CHCTRL_n_SETEN (0x00000001uL)
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287 | #define DMAC3_CHCTRL_n_CLREN (0x00000002uL)
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288 | #define DMAC3_CHCTRL_n_STG (0x00000004uL)
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289 | #define DMAC3_CHCTRL_n_SWRST (0x00000008uL)
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290 | #define DMAC3_CHCTRL_n_CLRRQ (0x00000010uL)
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291 | #define DMAC3_CHCTRL_n_CLREND (0x00000020uL)
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292 | #define DMAC3_CHCTRL_n_CLRTC (0x00000040uL)
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293 | #define DMAC3_CHCTRL_n_SETSUS (0x00000100uL)
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294 | #define DMAC3_CHCTRL_n_CLRSUS (0x00000200uL)
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295 | #define DMAC3_CHCTRL_n_SETINTMSK (0x00010000uL)
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296 | #define DMAC3_CHCTRL_n_CLRINTMSK (0x00020000uL)
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297 |
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298 | #define DMAC3_CHCFG_n_SEL (0x00000007uL)
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299 | #define DMAC3_CHCFG_n_REQD (0x00000008uL)
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300 | #define DMAC3_CHCFG_n_LOEN (0x00000010uL)
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301 | #define DMAC3_CHCFG_n_HIEN (0x00000020uL)
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302 | #define DMAC3_CHCFG_n_LVL (0x00000040uL)
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303 | #define DMAC3_CHCFG_n_AM (0x00000700uL)
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304 | #define DMAC3_CHCFG_n_SDS (0x0000F000uL)
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305 | #define DMAC3_CHCFG_n_DDS (0x000F0000uL)
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306 | #define DMAC3_CHCFG_n_SAD (0x00100000uL)
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307 | #define DMAC3_CHCFG_n_DAD (0x00200000uL)
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308 | #define DMAC3_CHCFG_n_TM (0x00400000uL)
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309 | #define DMAC3_CHCFG_n_DEM (0x01000000uL)
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310 | #define DMAC3_CHCFG_n_TCM (0x02000000uL)
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311 | #define DMAC3_CHCFG_n_SBE (0x08000000uL)
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312 | #define DMAC3_CHCFG_n_RSEL (0x10000000uL)
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313 | #define DMAC3_CHCFG_n_RSW (0x20000000uL)
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314 | #define DMAC3_CHCFG_n_REN (0x40000000uL)
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315 | #define DMAC3_CHCFG_n_DMS (0x80000000uL)
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316 |
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317 | #define DMAC3_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
318 |
|
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319 | #define DMAC3_CHEXT_n_SCA (0x000000F0uL)
|
---|
320 | #define DMAC3_CHEXT_n_DCA (0x0000F000uL)
|
---|
321 |
|
---|
322 | #define DMAC3_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
323 |
|
---|
324 | #define DMAC3_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
325 |
|
---|
326 | /* ---- DMAC4 ---- */
|
---|
327 | #define DMAC4_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
328 |
|
---|
329 | #define DMAC4_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
330 |
|
---|
331 | #define DMAC4_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
332 |
|
---|
333 | #define DMAC4_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
334 |
|
---|
335 | #define DMAC4_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
336 |
|
---|
337 | #define DMAC4_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
338 |
|
---|
339 | #define DMAC4_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
340 |
|
---|
341 | #define DMAC4_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
342 |
|
---|
343 | #define DMAC4_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
344 |
|
---|
345 | #define DMAC4_CHSTAT_n_EN (0x00000001uL)
|
---|
346 | #define DMAC4_CHSTAT_n_RQST (0x00000002uL)
|
---|
347 | #define DMAC4_CHSTAT_n_TACT (0x00000004uL)
|
---|
348 | #define DMAC4_CHSTAT_n_SUS (0x00000008uL)
|
---|
349 | #define DMAC4_CHSTAT_n_ER (0x00000010uL)
|
---|
350 | #define DMAC4_CHSTAT_n_END (0x00000020uL)
|
---|
351 | #define DMAC4_CHSTAT_n_TC (0x00000040uL)
|
---|
352 | #define DMAC4_CHSTAT_n_SR (0x00000080uL)
|
---|
353 | #define DMAC4_CHSTAT_n_DL (0x00000100uL)
|
---|
354 | #define DMAC4_CHSTAT_n_DW (0x00000200uL)
|
---|
355 | #define DMAC4_CHSTAT_n_DER (0x00000400uL)
|
---|
356 | #define DMAC4_CHSTAT_n_MODE (0x00000800uL)
|
---|
357 | #define DMAC4_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
358 |
|
---|
359 | #define DMAC4_CHCTRL_n_SETEN (0x00000001uL)
|
---|
360 | #define DMAC4_CHCTRL_n_CLREN (0x00000002uL)
|
---|
361 | #define DMAC4_CHCTRL_n_STG (0x00000004uL)
|
---|
362 | #define DMAC4_CHCTRL_n_SWRST (0x00000008uL)
|
---|
363 | #define DMAC4_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
364 | #define DMAC4_CHCTRL_n_CLREND (0x00000020uL)
|
---|
365 | #define DMAC4_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
366 | #define DMAC4_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
367 | #define DMAC4_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
368 | #define DMAC4_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
369 | #define DMAC4_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
370 |
|
---|
371 | #define DMAC4_CHCFG_n_SEL (0x00000007uL)
|
---|
372 | #define DMAC4_CHCFG_n_REQD (0x00000008uL)
|
---|
373 | #define DMAC4_CHCFG_n_LOEN (0x00000010uL)
|
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374 | #define DMAC4_CHCFG_n_HIEN (0x00000020uL)
|
---|
375 | #define DMAC4_CHCFG_n_LVL (0x00000040uL)
|
---|
376 | #define DMAC4_CHCFG_n_AM (0x00000700uL)
|
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377 | #define DMAC4_CHCFG_n_SDS (0x0000F000uL)
|
---|
378 | #define DMAC4_CHCFG_n_DDS (0x000F0000uL)
|
---|
379 | #define DMAC4_CHCFG_n_SAD (0x00100000uL)
|
---|
380 | #define DMAC4_CHCFG_n_DAD (0x00200000uL)
|
---|
381 | #define DMAC4_CHCFG_n_TM (0x00400000uL)
|
---|
382 | #define DMAC4_CHCFG_n_DEM (0x01000000uL)
|
---|
383 | #define DMAC4_CHCFG_n_TCM (0x02000000uL)
|
---|
384 | #define DMAC4_CHCFG_n_SBE (0x08000000uL)
|
---|
385 | #define DMAC4_CHCFG_n_RSEL (0x10000000uL)
|
---|
386 | #define DMAC4_CHCFG_n_RSW (0x20000000uL)
|
---|
387 | #define DMAC4_CHCFG_n_REN (0x40000000uL)
|
---|
388 | #define DMAC4_CHCFG_n_DMS (0x80000000uL)
|
---|
389 |
|
---|
390 | #define DMAC4_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
391 |
|
---|
392 | #define DMAC4_CHEXT_n_SCA (0x000000F0uL)
|
---|
393 | #define DMAC4_CHEXT_n_DCA (0x0000F000uL)
|
---|
394 |
|
---|
395 | #define DMAC4_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
396 |
|
---|
397 | #define DMAC4_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
398 |
|
---|
399 | /* ---- DMAC5 ---- */
|
---|
400 | #define DMAC5_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
401 |
|
---|
402 | #define DMAC5_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
403 |
|
---|
404 | #define DMAC5_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
405 |
|
---|
406 | #define DMAC5_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
407 |
|
---|
408 | #define DMAC5_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
409 |
|
---|
410 | #define DMAC5_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
411 |
|
---|
412 | #define DMAC5_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
413 |
|
---|
414 | #define DMAC5_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
415 |
|
---|
416 | #define DMAC5_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
417 |
|
---|
418 | #define DMAC5_CHSTAT_n_EN (0x00000001uL)
|
---|
419 | #define DMAC5_CHSTAT_n_RQST (0x00000002uL)
|
---|
420 | #define DMAC5_CHSTAT_n_TACT (0x00000004uL)
|
---|
421 | #define DMAC5_CHSTAT_n_SUS (0x00000008uL)
|
---|
422 | #define DMAC5_CHSTAT_n_ER (0x00000010uL)
|
---|
423 | #define DMAC5_CHSTAT_n_END (0x00000020uL)
|
---|
424 | #define DMAC5_CHSTAT_n_TC (0x00000040uL)
|
---|
425 | #define DMAC5_CHSTAT_n_SR (0x00000080uL)
|
---|
426 | #define DMAC5_CHSTAT_n_DL (0x00000100uL)
|
---|
427 | #define DMAC5_CHSTAT_n_DW (0x00000200uL)
|
---|
428 | #define DMAC5_CHSTAT_n_DER (0x00000400uL)
|
---|
429 | #define DMAC5_CHSTAT_n_MODE (0x00000800uL)
|
---|
430 | #define DMAC5_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
431 |
|
---|
432 | #define DMAC5_CHCTRL_n_SETEN (0x00000001uL)
|
---|
433 | #define DMAC5_CHCTRL_n_CLREN (0x00000002uL)
|
---|
434 | #define DMAC5_CHCTRL_n_STG (0x00000004uL)
|
---|
435 | #define DMAC5_CHCTRL_n_SWRST (0x00000008uL)
|
---|
436 | #define DMAC5_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
437 | #define DMAC5_CHCTRL_n_CLREND (0x00000020uL)
|
---|
438 | #define DMAC5_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
439 | #define DMAC5_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
440 | #define DMAC5_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
441 | #define DMAC5_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
442 | #define DMAC5_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
443 |
|
---|
444 | #define DMAC5_CHCFG_n_SEL (0x00000007uL)
|
---|
445 | #define DMAC5_CHCFG_n_REQD (0x00000008uL)
|
---|
446 | #define DMAC5_CHCFG_n_LOEN (0x00000010uL)
|
---|
447 | #define DMAC5_CHCFG_n_HIEN (0x00000020uL)
|
---|
448 | #define DMAC5_CHCFG_n_LVL (0x00000040uL)
|
---|
449 | #define DMAC5_CHCFG_n_AM (0x00000700uL)
|
---|
450 | #define DMAC5_CHCFG_n_SDS (0x0000F000uL)
|
---|
451 | #define DMAC5_CHCFG_n_DDS (0x000F0000uL)
|
---|
452 | #define DMAC5_CHCFG_n_SAD (0x00100000uL)
|
---|
453 | #define DMAC5_CHCFG_n_DAD (0x00200000uL)
|
---|
454 | #define DMAC5_CHCFG_n_TM (0x00400000uL)
|
---|
455 | #define DMAC5_CHCFG_n_DEM (0x01000000uL)
|
---|
456 | #define DMAC5_CHCFG_n_TCM (0x02000000uL)
|
---|
457 | #define DMAC5_CHCFG_n_SBE (0x08000000uL)
|
---|
458 | #define DMAC5_CHCFG_n_RSEL (0x10000000uL)
|
---|
459 | #define DMAC5_CHCFG_n_RSW (0x20000000uL)
|
---|
460 | #define DMAC5_CHCFG_n_REN (0x40000000uL)
|
---|
461 | #define DMAC5_CHCFG_n_DMS (0x80000000uL)
|
---|
462 |
|
---|
463 | #define DMAC5_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
464 |
|
---|
465 | #define DMAC5_CHEXT_n_SCA (0x000000F0uL)
|
---|
466 | #define DMAC5_CHEXT_n_DCA (0x0000F000uL)
|
---|
467 |
|
---|
468 | #define DMAC5_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
469 |
|
---|
470 | #define DMAC5_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
471 |
|
---|
472 | /* ---- DMAC6 ---- */
|
---|
473 | #define DMAC6_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
474 |
|
---|
475 | #define DMAC6_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
476 |
|
---|
477 | #define DMAC6_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
478 |
|
---|
479 | #define DMAC6_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
480 |
|
---|
481 | #define DMAC6_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
482 |
|
---|
483 | #define DMAC6_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
484 |
|
---|
485 | #define DMAC6_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
486 |
|
---|
487 | #define DMAC6_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
488 |
|
---|
489 | #define DMAC6_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
490 |
|
---|
491 | #define DMAC6_CHSTAT_n_EN (0x00000001uL)
|
---|
492 | #define DMAC6_CHSTAT_n_RQST (0x00000002uL)
|
---|
493 | #define DMAC6_CHSTAT_n_TACT (0x00000004uL)
|
---|
494 | #define DMAC6_CHSTAT_n_SUS (0x00000008uL)
|
---|
495 | #define DMAC6_CHSTAT_n_ER (0x00000010uL)
|
---|
496 | #define DMAC6_CHSTAT_n_END (0x00000020uL)
|
---|
497 | #define DMAC6_CHSTAT_n_TC (0x00000040uL)
|
---|
498 | #define DMAC6_CHSTAT_n_SR (0x00000080uL)
|
---|
499 | #define DMAC6_CHSTAT_n_DL (0x00000100uL)
|
---|
500 | #define DMAC6_CHSTAT_n_DW (0x00000200uL)
|
---|
501 | #define DMAC6_CHSTAT_n_DER (0x00000400uL)
|
---|
502 | #define DMAC6_CHSTAT_n_MODE (0x00000800uL)
|
---|
503 | #define DMAC6_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
504 |
|
---|
505 | #define DMAC6_CHCTRL_n_SETEN (0x00000001uL)
|
---|
506 | #define DMAC6_CHCTRL_n_CLREN (0x00000002uL)
|
---|
507 | #define DMAC6_CHCTRL_n_STG (0x00000004uL)
|
---|
508 | #define DMAC6_CHCTRL_n_SWRST (0x00000008uL)
|
---|
509 | #define DMAC6_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
510 | #define DMAC6_CHCTRL_n_CLREND (0x00000020uL)
|
---|
511 | #define DMAC6_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
512 | #define DMAC6_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
513 | #define DMAC6_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
514 | #define DMAC6_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
515 | #define DMAC6_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
516 |
|
---|
517 | #define DMAC6_CHCFG_n_SEL (0x00000007uL)
|
---|
518 | #define DMAC6_CHCFG_n_REQD (0x00000008uL)
|
---|
519 | #define DMAC6_CHCFG_n_LOEN (0x00000010uL)
|
---|
520 | #define DMAC6_CHCFG_n_HIEN (0x00000020uL)
|
---|
521 | #define DMAC6_CHCFG_n_LVL (0x00000040uL)
|
---|
522 | #define DMAC6_CHCFG_n_AM (0x00000700uL)
|
---|
523 | #define DMAC6_CHCFG_n_SDS (0x0000F000uL)
|
---|
524 | #define DMAC6_CHCFG_n_DDS (0x000F0000uL)
|
---|
525 | #define DMAC6_CHCFG_n_SAD (0x00100000uL)
|
---|
526 | #define DMAC6_CHCFG_n_DAD (0x00200000uL)
|
---|
527 | #define DMAC6_CHCFG_n_TM (0x00400000uL)
|
---|
528 | #define DMAC6_CHCFG_n_DEM (0x01000000uL)
|
---|
529 | #define DMAC6_CHCFG_n_TCM (0x02000000uL)
|
---|
530 | #define DMAC6_CHCFG_n_SBE (0x08000000uL)
|
---|
531 | #define DMAC6_CHCFG_n_RSEL (0x10000000uL)
|
---|
532 | #define DMAC6_CHCFG_n_RSW (0x20000000uL)
|
---|
533 | #define DMAC6_CHCFG_n_REN (0x40000000uL)
|
---|
534 | #define DMAC6_CHCFG_n_DMS (0x80000000uL)
|
---|
535 |
|
---|
536 | #define DMAC6_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
537 |
|
---|
538 | #define DMAC6_CHEXT_n_SCA (0x000000F0uL)
|
---|
539 | #define DMAC6_CHEXT_n_DCA (0x0000F000uL)
|
---|
540 |
|
---|
541 | #define DMAC6_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
542 |
|
---|
543 | #define DMAC6_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
544 |
|
---|
545 | /* ---- DMAC7 ---- */
|
---|
546 | #define DMAC7_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
547 |
|
---|
548 | #define DMAC7_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
549 |
|
---|
550 | #define DMAC7_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
551 |
|
---|
552 | #define DMAC7_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
553 |
|
---|
554 | #define DMAC7_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
555 |
|
---|
556 | #define DMAC7_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
557 |
|
---|
558 | #define DMAC7_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
559 |
|
---|
560 | #define DMAC7_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
561 |
|
---|
562 | #define DMAC7_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
563 |
|
---|
564 | #define DMAC7_CHSTAT_n_EN (0x00000001uL)
|
---|
565 | #define DMAC7_CHSTAT_n_RQST (0x00000002uL)
|
---|
566 | #define DMAC7_CHSTAT_n_TACT (0x00000004uL)
|
---|
567 | #define DMAC7_CHSTAT_n_SUS (0x00000008uL)
|
---|
568 | #define DMAC7_CHSTAT_n_ER (0x00000010uL)
|
---|
569 | #define DMAC7_CHSTAT_n_END (0x00000020uL)
|
---|
570 | #define DMAC7_CHSTAT_n_TC (0x00000040uL)
|
---|
571 | #define DMAC7_CHSTAT_n_SR (0x00000080uL)
|
---|
572 | #define DMAC7_CHSTAT_n_DL (0x00000100uL)
|
---|
573 | #define DMAC7_CHSTAT_n_DW (0x00000200uL)
|
---|
574 | #define DMAC7_CHSTAT_n_DER (0x00000400uL)
|
---|
575 | #define DMAC7_CHSTAT_n_MODE (0x00000800uL)
|
---|
576 | #define DMAC7_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
577 |
|
---|
578 | #define DMAC7_CHCTRL_n_SETEN (0x00000001uL)
|
---|
579 | #define DMAC7_CHCTRL_n_CLREN (0x00000002uL)
|
---|
580 | #define DMAC7_CHCTRL_n_STG (0x00000004uL)
|
---|
581 | #define DMAC7_CHCTRL_n_SWRST (0x00000008uL)
|
---|
582 | #define DMAC7_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
583 | #define DMAC7_CHCTRL_n_CLREND (0x00000020uL)
|
---|
584 | #define DMAC7_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
585 | #define DMAC7_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
586 | #define DMAC7_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
587 | #define DMAC7_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
588 | #define DMAC7_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
589 |
|
---|
590 | #define DMAC7_CHCFG_n_SEL (0x00000007uL)
|
---|
591 | #define DMAC7_CHCFG_n_REQD (0x00000008uL)
|
---|
592 | #define DMAC7_CHCFG_n_LOEN (0x00000010uL)
|
---|
593 | #define DMAC7_CHCFG_n_HIEN (0x00000020uL)
|
---|
594 | #define DMAC7_CHCFG_n_LVL (0x00000040uL)
|
---|
595 | #define DMAC7_CHCFG_n_AM (0x00000700uL)
|
---|
596 | #define DMAC7_CHCFG_n_SDS (0x0000F000uL)
|
---|
597 | #define DMAC7_CHCFG_n_DDS (0x000F0000uL)
|
---|
598 | #define DMAC7_CHCFG_n_SAD (0x00100000uL)
|
---|
599 | #define DMAC7_CHCFG_n_DAD (0x00200000uL)
|
---|
600 | #define DMAC7_CHCFG_n_TM (0x00400000uL)
|
---|
601 | #define DMAC7_CHCFG_n_DEM (0x01000000uL)
|
---|
602 | #define DMAC7_CHCFG_n_TCM (0x02000000uL)
|
---|
603 | #define DMAC7_CHCFG_n_SBE (0x08000000uL)
|
---|
604 | #define DMAC7_CHCFG_n_RSEL (0x10000000uL)
|
---|
605 | #define DMAC7_CHCFG_n_RSW (0x20000000uL)
|
---|
606 | #define DMAC7_CHCFG_n_REN (0x40000000uL)
|
---|
607 | #define DMAC7_CHCFG_n_DMS (0x80000000uL)
|
---|
608 |
|
---|
609 | #define DMAC7_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
610 |
|
---|
611 | #define DMAC7_CHEXT_n_SCA (0x000000F0uL)
|
---|
612 | #define DMAC7_CHEXT_n_DCA (0x0000F000uL)
|
---|
613 |
|
---|
614 | #define DMAC7_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
615 |
|
---|
616 | #define DMAC7_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
617 |
|
---|
618 | /* ---- DMAC0-7 ---- */
|
---|
619 | #define DMAC07_DCTRL_0_7_PR (0x00000001uL)
|
---|
620 | #define DMAC07_DCTRL_0_7_LVINT (0x00000002uL)
|
---|
621 | #define DMAC07_DCTRL_0_7_LDCA (0x0000003CuL)
|
---|
622 | #define DMAC07_DCTRL_0_7_LWCA (0x000003C0uL)
|
---|
623 |
|
---|
624 | #define DMAC07_DSTAT_EN_0_7_EN0 (0x00000001uL)
|
---|
625 | #define DMAC07_DSTAT_EN_0_7_EN1 (0x00000002uL)
|
---|
626 | #define DMAC07_DSTAT_EN_0_7_EN2 (0x00000004uL)
|
---|
627 | #define DMAC07_DSTAT_EN_0_7_EN3 (0x00000008uL)
|
---|
628 | #define DMAC07_DSTAT_EN_0_7_EN4 (0x00000010uL)
|
---|
629 | #define DMAC07_DSTAT_EN_0_7_EN5 (0x00000020uL)
|
---|
630 | #define DMAC07_DSTAT_EN_0_7_EN6 (0x00000040uL)
|
---|
631 | #define DMAC07_DSTAT_EN_0_7_EN7 (0x00000080uL)
|
---|
632 |
|
---|
633 | #define DMAC07_DSTAT_ER_0_7_ER0 (0x00000001uL)
|
---|
634 | #define DMAC07_DSTAT_ER_0_7_ER1 (0x00000002uL)
|
---|
635 | #define DMAC07_DSTAT_ER_0_7_ER2 (0x00000004uL)
|
---|
636 | #define DMAC07_DSTAT_ER_0_7_ER3 (0x00000008uL)
|
---|
637 | #define DMAC07_DSTAT_ER_0_7_ER4 (0x00000010uL)
|
---|
638 | #define DMAC07_DSTAT_ER_0_7_ER5 (0x00000020uL)
|
---|
639 | #define DMAC07_DSTAT_ER_0_7_ER6 (0x00000040uL)
|
---|
640 | #define DMAC07_DSTAT_ER_0_7_ER7 (0x00000080uL)
|
---|
641 |
|
---|
642 | #define DMAC07_DSTAT_END_0_7_END0 (0x00000001uL)
|
---|
643 | #define DMAC07_DSTAT_END_0_7_END1 (0x00000002uL)
|
---|
644 | #define DMAC07_DSTAT_END_0_7_END2 (0x00000004uL)
|
---|
645 | #define DMAC07_DSTAT_END_0_7_END3 (0x00000008uL)
|
---|
646 | #define DMAC07_DSTAT_END_0_7_END4 (0x00000010uL)
|
---|
647 | #define DMAC07_DSTAT_END_0_7_END5 (0x00000020uL)
|
---|
648 | #define DMAC07_DSTAT_END_0_7_END6 (0x00000040uL)
|
---|
649 | #define DMAC07_DSTAT_END_0_7_END7 (0x00000080uL)
|
---|
650 |
|
---|
651 | #define DMAC07_DSTAT_TC_0_7_TC0 (0x00000001uL)
|
---|
652 | #define DMAC07_DSTAT_TC_0_7_TC1 (0x00000002uL)
|
---|
653 | #define DMAC07_DSTAT_TC_0_7_TC2 (0x00000004uL)
|
---|
654 | #define DMAC07_DSTAT_TC_0_7_TC3 (0x00000008uL)
|
---|
655 | #define DMAC07_DSTAT_TC_0_7_TC4 (0x00000010uL)
|
---|
656 | #define DMAC07_DSTAT_TC_0_7_TC5 (0x00000020uL)
|
---|
657 | #define DMAC07_DSTAT_TC_0_7_TC6 (0x00000040uL)
|
---|
658 | #define DMAC07_DSTAT_TC_0_7_TC7 (0x00000080uL)
|
---|
659 |
|
---|
660 | #define DMAC07_DSTAT_SUS_0_7_SUS0 (0x00000001uL)
|
---|
661 | #define DMAC07_DSTAT_SUS_0_7_SUS1 (0x00000002uL)
|
---|
662 | #define DMAC07_DSTAT_SUS_0_7_SUS2 (0x00000004uL)
|
---|
663 | #define DMAC07_DSTAT_SUS_0_7_SUS3 (0x00000008uL)
|
---|
664 | #define DMAC07_DSTAT_SUS_0_7_SUS4 (0x00000010uL)
|
---|
665 | #define DMAC07_DSTAT_SUS_0_7_SUS5 (0x00000020uL)
|
---|
666 | #define DMAC07_DSTAT_SUS_0_7_SUS6 (0x00000040uL)
|
---|
667 | #define DMAC07_DSTAT_SUS_0_7_SUS7 (0x00000080uL)
|
---|
668 |
|
---|
669 | /* ---- DMAC8 ---- */
|
---|
670 | #define DMAC8_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
671 |
|
---|
672 | #define DMAC8_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
673 |
|
---|
674 | #define DMAC8_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
675 |
|
---|
676 | #define DMAC8_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
677 |
|
---|
678 | #define DMAC8_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
679 |
|
---|
680 | #define DMAC8_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
681 |
|
---|
682 | #define DMAC8_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
683 |
|
---|
684 | #define DMAC8_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
685 |
|
---|
686 | #define DMAC8_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
687 |
|
---|
688 | #define DMAC8_CHSTAT_n_EN (0x00000001uL)
|
---|
689 | #define DMAC8_CHSTAT_n_RQST (0x00000002uL)
|
---|
690 | #define DMAC8_CHSTAT_n_TACT (0x00000004uL)
|
---|
691 | #define DMAC8_CHSTAT_n_SUS (0x00000008uL)
|
---|
692 | #define DMAC8_CHSTAT_n_ER (0x00000010uL)
|
---|
693 | #define DMAC8_CHSTAT_n_END (0x00000020uL)
|
---|
694 | #define DMAC8_CHSTAT_n_TC (0x00000040uL)
|
---|
695 | #define DMAC8_CHSTAT_n_SR (0x00000080uL)
|
---|
696 | #define DMAC8_CHSTAT_n_DL (0x00000100uL)
|
---|
697 | #define DMAC8_CHSTAT_n_DW (0x00000200uL)
|
---|
698 | #define DMAC8_CHSTAT_n_DER (0x00000400uL)
|
---|
699 | #define DMAC8_CHSTAT_n_MODE (0x00000800uL)
|
---|
700 | #define DMAC8_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
701 |
|
---|
702 | #define DMAC8_CHCTRL_n_SETEN (0x00000001uL)
|
---|
703 | #define DMAC8_CHCTRL_n_CLREN (0x00000002uL)
|
---|
704 | #define DMAC8_CHCTRL_n_STG (0x00000004uL)
|
---|
705 | #define DMAC8_CHCTRL_n_SWRST (0x00000008uL)
|
---|
706 | #define DMAC8_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
707 | #define DMAC8_CHCTRL_n_CLREND (0x00000020uL)
|
---|
708 | #define DMAC8_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
709 | #define DMAC8_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
710 | #define DMAC8_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
711 | #define DMAC8_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
712 | #define DMAC8_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
713 |
|
---|
714 | #define DMAC8_CHCFG_n_SEL (0x00000007uL)
|
---|
715 | #define DMAC8_CHCFG_n_REQD (0x00000008uL)
|
---|
716 | #define DMAC8_CHCFG_n_LOEN (0x00000010uL)
|
---|
717 | #define DMAC8_CHCFG_n_HIEN (0x00000020uL)
|
---|
718 | #define DMAC8_CHCFG_n_LVL (0x00000040uL)
|
---|
719 | #define DMAC8_CHCFG_n_AM (0x00000700uL)
|
---|
720 | #define DMAC8_CHCFG_n_SDS (0x0000F000uL)
|
---|
721 | #define DMAC8_CHCFG_n_DDS (0x000F0000uL)
|
---|
722 | #define DMAC8_CHCFG_n_SAD (0x00100000uL)
|
---|
723 | #define DMAC8_CHCFG_n_DAD (0x00200000uL)
|
---|
724 | #define DMAC8_CHCFG_n_TM (0x00400000uL)
|
---|
725 | #define DMAC8_CHCFG_n_DEM (0x01000000uL)
|
---|
726 | #define DMAC8_CHCFG_n_TCM (0x02000000uL)
|
---|
727 | #define DMAC8_CHCFG_n_SBE (0x08000000uL)
|
---|
728 | #define DMAC8_CHCFG_n_RSEL (0x10000000uL)
|
---|
729 | #define DMAC8_CHCFG_n_RSW (0x20000000uL)
|
---|
730 | #define DMAC8_CHCFG_n_REN (0x40000000uL)
|
---|
731 | #define DMAC8_CHCFG_n_DMS (0x80000000uL)
|
---|
732 |
|
---|
733 | #define DMAC8_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
734 |
|
---|
735 | #define DMAC8_CHEXT_n_SCA (0x000000F0uL)
|
---|
736 | #define DMAC8_CHEXT_n_DCA (0x0000F000uL)
|
---|
737 |
|
---|
738 | #define DMAC8_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
739 |
|
---|
740 | #define DMAC8_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
741 |
|
---|
742 | /* ---- DMAC9 ---- */
|
---|
743 | #define DMAC9_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
744 |
|
---|
745 | #define DMAC9_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
746 |
|
---|
747 | #define DMAC9_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
748 |
|
---|
749 | #define DMAC9_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
750 |
|
---|
751 | #define DMAC9_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
752 |
|
---|
753 | #define DMAC9_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
754 |
|
---|
755 | #define DMAC9_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
756 |
|
---|
757 | #define DMAC9_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
758 |
|
---|
759 | #define DMAC9_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
760 |
|
---|
761 | #define DMAC9_CHSTAT_n_EN (0x00000001uL)
|
---|
762 | #define DMAC9_CHSTAT_n_RQST (0x00000002uL)
|
---|
763 | #define DMAC9_CHSTAT_n_TACT (0x00000004uL)
|
---|
764 | #define DMAC9_CHSTAT_n_SUS (0x00000008uL)
|
---|
765 | #define DMAC9_CHSTAT_n_ER (0x00000010uL)
|
---|
766 | #define DMAC9_CHSTAT_n_END (0x00000020uL)
|
---|
767 | #define DMAC9_CHSTAT_n_TC (0x00000040uL)
|
---|
768 | #define DMAC9_CHSTAT_n_SR (0x00000080uL)
|
---|
769 | #define DMAC9_CHSTAT_n_DL (0x00000100uL)
|
---|
770 | #define DMAC9_CHSTAT_n_DW (0x00000200uL)
|
---|
771 | #define DMAC9_CHSTAT_n_DER (0x00000400uL)
|
---|
772 | #define DMAC9_CHSTAT_n_MODE (0x00000800uL)
|
---|
773 | #define DMAC9_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
774 |
|
---|
775 | #define DMAC9_CHCTRL_n_SETEN (0x00000001uL)
|
---|
776 | #define DMAC9_CHCTRL_n_CLREN (0x00000002uL)
|
---|
777 | #define DMAC9_CHCTRL_n_STG (0x00000004uL)
|
---|
778 | #define DMAC9_CHCTRL_n_SWRST (0x00000008uL)
|
---|
779 | #define DMAC9_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
780 | #define DMAC9_CHCTRL_n_CLREND (0x00000020uL)
|
---|
781 | #define DMAC9_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
782 | #define DMAC9_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
783 | #define DMAC9_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
784 | #define DMAC9_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
785 | #define DMAC9_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
786 |
|
---|
787 | #define DMAC9_CHCFG_n_SEL (0x00000007uL)
|
---|
788 | #define DMAC9_CHCFG_n_REQD (0x00000008uL)
|
---|
789 | #define DMAC9_CHCFG_n_LOEN (0x00000010uL)
|
---|
790 | #define DMAC9_CHCFG_n_HIEN (0x00000020uL)
|
---|
791 | #define DMAC9_CHCFG_n_LVL (0x00000040uL)
|
---|
792 | #define DMAC9_CHCFG_n_AM (0x00000700uL)
|
---|
793 | #define DMAC9_CHCFG_n_SDS (0x0000F000uL)
|
---|
794 | #define DMAC9_CHCFG_n_DDS (0x000F0000uL)
|
---|
795 | #define DMAC9_CHCFG_n_SAD (0x00100000uL)
|
---|
796 | #define DMAC9_CHCFG_n_DAD (0x00200000uL)
|
---|
797 | #define DMAC9_CHCFG_n_TM (0x00400000uL)
|
---|
798 | #define DMAC9_CHCFG_n_DEM (0x01000000uL)
|
---|
799 | #define DMAC9_CHCFG_n_TCM (0x02000000uL)
|
---|
800 | #define DMAC9_CHCFG_n_SBE (0x08000000uL)
|
---|
801 | #define DMAC9_CHCFG_n_RSEL (0x10000000uL)
|
---|
802 | #define DMAC9_CHCFG_n_RSW (0x20000000uL)
|
---|
803 | #define DMAC9_CHCFG_n_REN (0x40000000uL)
|
---|
804 | #define DMAC9_CHCFG_n_DMS (0x80000000uL)
|
---|
805 |
|
---|
806 | #define DMAC9_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
807 |
|
---|
808 | #define DMAC9_CHEXT_n_SCA (0x000000F0uL)
|
---|
809 | #define DMAC9_CHEXT_n_DCA (0x0000F000uL)
|
---|
810 |
|
---|
811 | #define DMAC9_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
812 |
|
---|
813 | #define DMAC9_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
814 |
|
---|
815 | /* ---- DMAC10 ---- */
|
---|
816 | #define DMAC10_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
817 |
|
---|
818 | #define DMAC10_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
819 |
|
---|
820 | #define DMAC10_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
821 |
|
---|
822 | #define DMAC10_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
823 |
|
---|
824 | #define DMAC10_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
825 |
|
---|
826 | #define DMAC10_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
827 |
|
---|
828 | #define DMAC10_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
829 |
|
---|
830 | #define DMAC10_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
831 |
|
---|
832 | #define DMAC10_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
833 |
|
---|
834 | #define DMAC10_CHSTAT_n_EN (0x00000001uL)
|
---|
835 | #define DMAC10_CHSTAT_n_RQST (0x00000002uL)
|
---|
836 | #define DMAC10_CHSTAT_n_TACT (0x00000004uL)
|
---|
837 | #define DMAC10_CHSTAT_n_SUS (0x00000008uL)
|
---|
838 | #define DMAC10_CHSTAT_n_ER (0x00000010uL)
|
---|
839 | #define DMAC10_CHSTAT_n_END (0x00000020uL)
|
---|
840 | #define DMAC10_CHSTAT_n_TC (0x00000040uL)
|
---|
841 | #define DMAC10_CHSTAT_n_SR (0x00000080uL)
|
---|
842 | #define DMAC10_CHSTAT_n_DL (0x00000100uL)
|
---|
843 | #define DMAC10_CHSTAT_n_DW (0x00000200uL)
|
---|
844 | #define DMAC10_CHSTAT_n_DER (0x00000400uL)
|
---|
845 | #define DMAC10_CHSTAT_n_MODE (0x00000800uL)
|
---|
846 | #define DMAC10_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
847 |
|
---|
848 | #define DMAC10_CHCTRL_n_SETEN (0x00000001uL)
|
---|
849 | #define DMAC10_CHCTRL_n_CLREN (0x00000002uL)
|
---|
850 | #define DMAC10_CHCTRL_n_STG (0x00000004uL)
|
---|
851 | #define DMAC10_CHCTRL_n_SWRST (0x00000008uL)
|
---|
852 | #define DMAC10_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
853 | #define DMAC10_CHCTRL_n_CLREND (0x00000020uL)
|
---|
854 | #define DMAC10_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
855 | #define DMAC10_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
856 | #define DMAC10_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
857 | #define DMAC10_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
858 | #define DMAC10_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
859 |
|
---|
860 | #define DMAC10_CHCFG_n_SEL (0x00000007uL)
|
---|
861 | #define DMAC10_CHCFG_n_REQD (0x00000008uL)
|
---|
862 | #define DMAC10_CHCFG_n_LOEN (0x00000010uL)
|
---|
863 | #define DMAC10_CHCFG_n_HIEN (0x00000020uL)
|
---|
864 | #define DMAC10_CHCFG_n_LVL (0x00000040uL)
|
---|
865 | #define DMAC10_CHCFG_n_AM (0x00000700uL)
|
---|
866 | #define DMAC10_CHCFG_n_SDS (0x0000F000uL)
|
---|
867 | #define DMAC10_CHCFG_n_DDS (0x000F0000uL)
|
---|
868 | #define DMAC10_CHCFG_n_SAD (0x00100000uL)
|
---|
869 | #define DMAC10_CHCFG_n_DAD (0x00200000uL)
|
---|
870 | #define DMAC10_CHCFG_n_TM (0x00400000uL)
|
---|
871 | #define DMAC10_CHCFG_n_DEM (0x01000000uL)
|
---|
872 | #define DMAC10_CHCFG_n_TCM (0x02000000uL)
|
---|
873 | #define DMAC10_CHCFG_n_SBE (0x08000000uL)
|
---|
874 | #define DMAC10_CHCFG_n_RSEL (0x10000000uL)
|
---|
875 | #define DMAC10_CHCFG_n_RSW (0x20000000uL)
|
---|
876 | #define DMAC10_CHCFG_n_REN (0x40000000uL)
|
---|
877 | #define DMAC10_CHCFG_n_DMS (0x80000000uL)
|
---|
878 |
|
---|
879 | #define DMAC10_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
880 |
|
---|
881 | #define DMAC10_CHEXT_n_SCA (0x000000F0uL)
|
---|
882 | #define DMAC10_CHEXT_n_DCA (0x0000F000uL)
|
---|
883 |
|
---|
884 | #define DMAC10_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
885 |
|
---|
886 | #define DMAC10_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
887 |
|
---|
888 | /* ---- DMAC11 ---- */
|
---|
889 | #define DMAC11_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
890 |
|
---|
891 | #define DMAC11_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
892 |
|
---|
893 | #define DMAC11_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
894 |
|
---|
895 | #define DMAC11_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
896 |
|
---|
897 | #define DMAC11_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
898 |
|
---|
899 | #define DMAC11_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
900 |
|
---|
901 | #define DMAC11_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
902 |
|
---|
903 | #define DMAC11_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
904 |
|
---|
905 | #define DMAC11_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
906 |
|
---|
907 | #define DMAC11_CHSTAT_n_EN (0x00000001uL)
|
---|
908 | #define DMAC11_CHSTAT_n_RQST (0x00000002uL)
|
---|
909 | #define DMAC11_CHSTAT_n_TACT (0x00000004uL)
|
---|
910 | #define DMAC11_CHSTAT_n_SUS (0x00000008uL)
|
---|
911 | #define DMAC11_CHSTAT_n_ER (0x00000010uL)
|
---|
912 | #define DMAC11_CHSTAT_n_END (0x00000020uL)
|
---|
913 | #define DMAC11_CHSTAT_n_TC (0x00000040uL)
|
---|
914 | #define DMAC11_CHSTAT_n_SR (0x00000080uL)
|
---|
915 | #define DMAC11_CHSTAT_n_DL (0x00000100uL)
|
---|
916 | #define DMAC11_CHSTAT_n_DW (0x00000200uL)
|
---|
917 | #define DMAC11_CHSTAT_n_DER (0x00000400uL)
|
---|
918 | #define DMAC11_CHSTAT_n_MODE (0x00000800uL)
|
---|
919 | #define DMAC11_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
920 |
|
---|
921 | #define DMAC11_CHCTRL_n_SETEN (0x00000001uL)
|
---|
922 | #define DMAC11_CHCTRL_n_CLREN (0x00000002uL)
|
---|
923 | #define DMAC11_CHCTRL_n_STG (0x00000004uL)
|
---|
924 | #define DMAC11_CHCTRL_n_SWRST (0x00000008uL)
|
---|
925 | #define DMAC11_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
926 | #define DMAC11_CHCTRL_n_CLREND (0x00000020uL)
|
---|
927 | #define DMAC11_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
928 | #define DMAC11_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
929 | #define DMAC11_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
930 | #define DMAC11_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
931 | #define DMAC11_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
932 |
|
---|
933 | #define DMAC11_CHCFG_n_SEL (0x00000007uL)
|
---|
934 | #define DMAC11_CHCFG_n_REQD (0x00000008uL)
|
---|
935 | #define DMAC11_CHCFG_n_LOEN (0x00000010uL)
|
---|
936 | #define DMAC11_CHCFG_n_HIEN (0x00000020uL)
|
---|
937 | #define DMAC11_CHCFG_n_LVL (0x00000040uL)
|
---|
938 | #define DMAC11_CHCFG_n_AM (0x00000700uL)
|
---|
939 | #define DMAC11_CHCFG_n_SDS (0x0000F000uL)
|
---|
940 | #define DMAC11_CHCFG_n_DDS (0x000F0000uL)
|
---|
941 | #define DMAC11_CHCFG_n_SAD (0x00100000uL)
|
---|
942 | #define DMAC11_CHCFG_n_DAD (0x00200000uL)
|
---|
943 | #define DMAC11_CHCFG_n_TM (0x00400000uL)
|
---|
944 | #define DMAC11_CHCFG_n_DEM (0x01000000uL)
|
---|
945 | #define DMAC11_CHCFG_n_TCM (0x02000000uL)
|
---|
946 | #define DMAC11_CHCFG_n_SBE (0x08000000uL)
|
---|
947 | #define DMAC11_CHCFG_n_RSEL (0x10000000uL)
|
---|
948 | #define DMAC11_CHCFG_n_RSW (0x20000000uL)
|
---|
949 | #define DMAC11_CHCFG_n_REN (0x40000000uL)
|
---|
950 | #define DMAC11_CHCFG_n_DMS (0x80000000uL)
|
---|
951 |
|
---|
952 | #define DMAC11_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
953 |
|
---|
954 | #define DMAC11_CHEXT_n_SCA (0x000000F0uL)
|
---|
955 | #define DMAC11_CHEXT_n_DCA (0x0000F000uL)
|
---|
956 |
|
---|
957 | #define DMAC11_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
958 |
|
---|
959 | #define DMAC11_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
960 |
|
---|
961 | /* ---- DMAC12 ---- */
|
---|
962 | #define DMAC12_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
963 |
|
---|
964 | #define DMAC12_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
965 |
|
---|
966 | #define DMAC12_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
967 |
|
---|
968 | #define DMAC12_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
969 |
|
---|
970 | #define DMAC12_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
971 |
|
---|
972 | #define DMAC12_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
973 |
|
---|
974 | #define DMAC12_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
975 |
|
---|
976 | #define DMAC12_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
977 |
|
---|
978 | #define DMAC12_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
979 |
|
---|
980 | #define DMAC12_CHSTAT_n_EN (0x00000001uL)
|
---|
981 | #define DMAC12_CHSTAT_n_RQST (0x00000002uL)
|
---|
982 | #define DMAC12_CHSTAT_n_TACT (0x00000004uL)
|
---|
983 | #define DMAC12_CHSTAT_n_SUS (0x00000008uL)
|
---|
984 | #define DMAC12_CHSTAT_n_ER (0x00000010uL)
|
---|
985 | #define DMAC12_CHSTAT_n_END (0x00000020uL)
|
---|
986 | #define DMAC12_CHSTAT_n_TC (0x00000040uL)
|
---|
987 | #define DMAC12_CHSTAT_n_SR (0x00000080uL)
|
---|
988 | #define DMAC12_CHSTAT_n_DL (0x00000100uL)
|
---|
989 | #define DMAC12_CHSTAT_n_DW (0x00000200uL)
|
---|
990 | #define DMAC12_CHSTAT_n_DER (0x00000400uL)
|
---|
991 | #define DMAC12_CHSTAT_n_MODE (0x00000800uL)
|
---|
992 | #define DMAC12_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
993 |
|
---|
994 | #define DMAC12_CHCTRL_n_SETEN (0x00000001uL)
|
---|
995 | #define DMAC12_CHCTRL_n_CLREN (0x00000002uL)
|
---|
996 | #define DMAC12_CHCTRL_n_STG (0x00000004uL)
|
---|
997 | #define DMAC12_CHCTRL_n_SWRST (0x00000008uL)
|
---|
998 | #define DMAC12_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
999 | #define DMAC12_CHCTRL_n_CLREND (0x00000020uL)
|
---|
1000 | #define DMAC12_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
1001 | #define DMAC12_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
1002 | #define DMAC12_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
1003 | #define DMAC12_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
1004 | #define DMAC12_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
1005 |
|
---|
1006 | #define DMAC12_CHCFG_n_SEL (0x00000007uL)
|
---|
1007 | #define DMAC12_CHCFG_n_REQD (0x00000008uL)
|
---|
1008 | #define DMAC12_CHCFG_n_LOEN (0x00000010uL)
|
---|
1009 | #define DMAC12_CHCFG_n_HIEN (0x00000020uL)
|
---|
1010 | #define DMAC12_CHCFG_n_LVL (0x00000040uL)
|
---|
1011 | #define DMAC12_CHCFG_n_AM (0x00000700uL)
|
---|
1012 | #define DMAC12_CHCFG_n_SDS (0x0000F000uL)
|
---|
1013 | #define DMAC12_CHCFG_n_DDS (0x000F0000uL)
|
---|
1014 | #define DMAC12_CHCFG_n_SAD (0x00100000uL)
|
---|
1015 | #define DMAC12_CHCFG_n_DAD (0x00200000uL)
|
---|
1016 | #define DMAC12_CHCFG_n_TM (0x00400000uL)
|
---|
1017 | #define DMAC12_CHCFG_n_DEM (0x01000000uL)
|
---|
1018 | #define DMAC12_CHCFG_n_TCM (0x02000000uL)
|
---|
1019 | #define DMAC12_CHCFG_n_SBE (0x08000000uL)
|
---|
1020 | #define DMAC12_CHCFG_n_RSEL (0x10000000uL)
|
---|
1021 | #define DMAC12_CHCFG_n_RSW (0x20000000uL)
|
---|
1022 | #define DMAC12_CHCFG_n_REN (0x40000000uL)
|
---|
1023 | #define DMAC12_CHCFG_n_DMS (0x80000000uL)
|
---|
1024 |
|
---|
1025 | #define DMAC12_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
1026 |
|
---|
1027 | #define DMAC12_CHEXT_n_SCA (0x000000F0uL)
|
---|
1028 | #define DMAC12_CHEXT_n_DCA (0x0000F000uL)
|
---|
1029 |
|
---|
1030 | #define DMAC12_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
1031 |
|
---|
1032 | #define DMAC12_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
1033 |
|
---|
1034 | /* ---- DMAC13 ---- */
|
---|
1035 | #define DMAC13_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
1036 |
|
---|
1037 | #define DMAC13_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
1038 |
|
---|
1039 | #define DMAC13_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
1040 |
|
---|
1041 | #define DMAC13_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
1042 |
|
---|
1043 | #define DMAC13_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
1044 |
|
---|
1045 | #define DMAC13_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
1046 |
|
---|
1047 | #define DMAC13_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
1048 |
|
---|
1049 | #define DMAC13_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
1050 |
|
---|
1051 | #define DMAC13_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
1052 |
|
---|
1053 | #define DMAC13_CHSTAT_n_EN (0x00000001uL)
|
---|
1054 | #define DMAC13_CHSTAT_n_RQST (0x00000002uL)
|
---|
1055 | #define DMAC13_CHSTAT_n_TACT (0x00000004uL)
|
---|
1056 | #define DMAC13_CHSTAT_n_SUS (0x00000008uL)
|
---|
1057 | #define DMAC13_CHSTAT_n_ER (0x00000010uL)
|
---|
1058 | #define DMAC13_CHSTAT_n_END (0x00000020uL)
|
---|
1059 | #define DMAC13_CHSTAT_n_TC (0x00000040uL)
|
---|
1060 | #define DMAC13_CHSTAT_n_SR (0x00000080uL)
|
---|
1061 | #define DMAC13_CHSTAT_n_DL (0x00000100uL)
|
---|
1062 | #define DMAC13_CHSTAT_n_DW (0x00000200uL)
|
---|
1063 | #define DMAC13_CHSTAT_n_DER (0x00000400uL)
|
---|
1064 | #define DMAC13_CHSTAT_n_MODE (0x00000800uL)
|
---|
1065 | #define DMAC13_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
1066 |
|
---|
1067 | #define DMAC13_CHCTRL_n_SETEN (0x00000001uL)
|
---|
1068 | #define DMAC13_CHCTRL_n_CLREN (0x00000002uL)
|
---|
1069 | #define DMAC13_CHCTRL_n_STG (0x00000004uL)
|
---|
1070 | #define DMAC13_CHCTRL_n_SWRST (0x00000008uL)
|
---|
1071 | #define DMAC13_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
1072 | #define DMAC13_CHCTRL_n_CLREND (0x00000020uL)
|
---|
1073 | #define DMAC13_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
1074 | #define DMAC13_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
1075 | #define DMAC13_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
1076 | #define DMAC13_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
1077 | #define DMAC13_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
1078 |
|
---|
1079 | #define DMAC13_CHCFG_n_SEL (0x00000007uL)
|
---|
1080 | #define DMAC13_CHCFG_n_REQD (0x00000008uL)
|
---|
1081 | #define DMAC13_CHCFG_n_LOEN (0x00000010uL)
|
---|
1082 | #define DMAC13_CHCFG_n_HIEN (0x00000020uL)
|
---|
1083 | #define DMAC13_CHCFG_n_LVL (0x00000040uL)
|
---|
1084 | #define DMAC13_CHCFG_n_AM (0x00000700uL)
|
---|
1085 | #define DMAC13_CHCFG_n_SDS (0x0000F000uL)
|
---|
1086 | #define DMAC13_CHCFG_n_DDS (0x000F0000uL)
|
---|
1087 | #define DMAC13_CHCFG_n_SAD (0x00100000uL)
|
---|
1088 | #define DMAC13_CHCFG_n_DAD (0x00200000uL)
|
---|
1089 | #define DMAC13_CHCFG_n_TM (0x00400000uL)
|
---|
1090 | #define DMAC13_CHCFG_n_DEM (0x01000000uL)
|
---|
1091 | #define DMAC13_CHCFG_n_TCM (0x02000000uL)
|
---|
1092 | #define DMAC13_CHCFG_n_SBE (0x08000000uL)
|
---|
1093 | #define DMAC13_CHCFG_n_RSEL (0x10000000uL)
|
---|
1094 | #define DMAC13_CHCFG_n_RSW (0x20000000uL)
|
---|
1095 | #define DMAC13_CHCFG_n_REN (0x40000000uL)
|
---|
1096 | #define DMAC13_CHCFG_n_DMS (0x80000000uL)
|
---|
1097 |
|
---|
1098 | #define DMAC13_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
1099 |
|
---|
1100 | #define DMAC13_CHEXT_n_SCA (0x000000F0uL)
|
---|
1101 | #define DMAC13_CHEXT_n_DCA (0x0000F000uL)
|
---|
1102 |
|
---|
1103 | #define DMAC13_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
1104 |
|
---|
1105 | #define DMAC13_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
1106 |
|
---|
1107 | /* ---- DMAC14 ---- */
|
---|
1108 | #define DMAC14_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
1109 |
|
---|
1110 | #define DMAC14_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
1111 |
|
---|
1112 | #define DMAC14_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
1113 |
|
---|
1114 | #define DMAC14_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
1115 |
|
---|
1116 | #define DMAC14_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
1117 |
|
---|
1118 | #define DMAC14_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
1119 |
|
---|
1120 | #define DMAC14_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
1121 |
|
---|
1122 | #define DMAC14_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
1123 |
|
---|
1124 | #define DMAC14_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
1125 |
|
---|
1126 | #define DMAC14_CHSTAT_n_EN (0x00000001uL)
|
---|
1127 | #define DMAC14_CHSTAT_n_RQST (0x00000002uL)
|
---|
1128 | #define DMAC14_CHSTAT_n_TACT (0x00000004uL)
|
---|
1129 | #define DMAC14_CHSTAT_n_SUS (0x00000008uL)
|
---|
1130 | #define DMAC14_CHSTAT_n_ER (0x00000010uL)
|
---|
1131 | #define DMAC14_CHSTAT_n_END (0x00000020uL)
|
---|
1132 | #define DMAC14_CHSTAT_n_TC (0x00000040uL)
|
---|
1133 | #define DMAC14_CHSTAT_n_SR (0x00000080uL)
|
---|
1134 | #define DMAC14_CHSTAT_n_DL (0x00000100uL)
|
---|
1135 | #define DMAC14_CHSTAT_n_DW (0x00000200uL)
|
---|
1136 | #define DMAC14_CHSTAT_n_DER (0x00000400uL)
|
---|
1137 | #define DMAC14_CHSTAT_n_MODE (0x00000800uL)
|
---|
1138 | #define DMAC14_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
1139 |
|
---|
1140 | #define DMAC14_CHCTRL_n_SETEN (0x00000001uL)
|
---|
1141 | #define DMAC14_CHCTRL_n_CLREN (0x00000002uL)
|
---|
1142 | #define DMAC14_CHCTRL_n_STG (0x00000004uL)
|
---|
1143 | #define DMAC14_CHCTRL_n_SWRST (0x00000008uL)
|
---|
1144 | #define DMAC14_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
1145 | #define DMAC14_CHCTRL_n_CLREND (0x00000020uL)
|
---|
1146 | #define DMAC14_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
1147 | #define DMAC14_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
1148 | #define DMAC14_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
1149 | #define DMAC14_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
1150 | #define DMAC14_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
1151 |
|
---|
1152 | #define DMAC14_CHCFG_n_SEL (0x00000007uL)
|
---|
1153 | #define DMAC14_CHCFG_n_REQD (0x00000008uL)
|
---|
1154 | #define DMAC14_CHCFG_n_LOEN (0x00000010uL)
|
---|
1155 | #define DMAC14_CHCFG_n_HIEN (0x00000020uL)
|
---|
1156 | #define DMAC14_CHCFG_n_LVL (0x00000040uL)
|
---|
1157 | #define DMAC14_CHCFG_n_AM (0x00000700uL)
|
---|
1158 | #define DMAC14_CHCFG_n_SDS (0x0000F000uL)
|
---|
1159 | #define DMAC14_CHCFG_n_DDS (0x000F0000uL)
|
---|
1160 | #define DMAC14_CHCFG_n_SAD (0x00100000uL)
|
---|
1161 | #define DMAC14_CHCFG_n_DAD (0x00200000uL)
|
---|
1162 | #define DMAC14_CHCFG_n_TM (0x00400000uL)
|
---|
1163 | #define DMAC14_CHCFG_n_DEM (0x01000000uL)
|
---|
1164 | #define DMAC14_CHCFG_n_TCM (0x02000000uL)
|
---|
1165 | #define DMAC14_CHCFG_n_SBE (0x08000000uL)
|
---|
1166 | #define DMAC14_CHCFG_n_RSEL (0x10000000uL)
|
---|
1167 | #define DMAC14_CHCFG_n_RSW (0x20000000uL)
|
---|
1168 | #define DMAC14_CHCFG_n_REN (0x40000000uL)
|
---|
1169 | #define DMAC14_CHCFG_n_DMS (0x80000000uL)
|
---|
1170 |
|
---|
1171 | #define DMAC14_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
1172 |
|
---|
1173 | #define DMAC14_CHEXT_n_SCA (0x000000F0uL)
|
---|
1174 | #define DMAC14_CHEXT_n_DCA (0x0000F000uL)
|
---|
1175 |
|
---|
1176 | #define DMAC14_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
1177 |
|
---|
1178 | #define DMAC14_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
1179 |
|
---|
1180 | /* ---- DMAC15 ---- */
|
---|
1181 | #define DMAC15_N0SA_n_SA (0xFFFFFFFFuL)
|
---|
1182 |
|
---|
1183 | #define DMAC15_N0DA_n_DA (0xFFFFFFFFuL)
|
---|
1184 |
|
---|
1185 | #define DMAC15_N0TB_n_TB (0xFFFFFFFFuL)
|
---|
1186 |
|
---|
1187 | #define DMAC15_N1SA_n_SA (0xFFFFFFFFuL)
|
---|
1188 |
|
---|
1189 | #define DMAC15_N1DA_n_DA (0xFFFFFFFFuL)
|
---|
1190 |
|
---|
1191 | #define DMAC15_N1TB_n_TB (0xFFFFFFFFuL)
|
---|
1192 |
|
---|
1193 | #define DMAC15_CRSA_n_CRSA (0xFFFFFFFFuL)
|
---|
1194 |
|
---|
1195 | #define DMAC15_CRDA_n_CRDA (0xFFFFFFFFuL)
|
---|
1196 |
|
---|
1197 | #define DMAC15_CRTB_n_CRTB (0xFFFFFFFFuL)
|
---|
1198 |
|
---|
1199 | #define DMAC15_CHSTAT_n_EN (0x00000001uL)
|
---|
1200 | #define DMAC15_CHSTAT_n_RQST (0x00000002uL)
|
---|
1201 | #define DMAC15_CHSTAT_n_TACT (0x00000004uL)
|
---|
1202 | #define DMAC15_CHSTAT_n_SUS (0x00000008uL)
|
---|
1203 | #define DMAC15_CHSTAT_n_ER (0x00000010uL)
|
---|
1204 | #define DMAC15_CHSTAT_n_END (0x00000020uL)
|
---|
1205 | #define DMAC15_CHSTAT_n_TC (0x00000040uL)
|
---|
1206 | #define DMAC15_CHSTAT_n_SR (0x00000080uL)
|
---|
1207 | #define DMAC15_CHSTAT_n_DL (0x00000100uL)
|
---|
1208 | #define DMAC15_CHSTAT_n_DW (0x00000200uL)
|
---|
1209 | #define DMAC15_CHSTAT_n_DER (0x00000400uL)
|
---|
1210 | #define DMAC15_CHSTAT_n_MODE (0x00000800uL)
|
---|
1211 | #define DMAC15_CHSTAT_n_INTMSK (0x00010000uL)
|
---|
1212 |
|
---|
1213 | #define DMAC15_CHCTRL_n_SETEN (0x00000001uL)
|
---|
1214 | #define DMAC15_CHCTRL_n_CLREN (0x00000002uL)
|
---|
1215 | #define DMAC15_CHCTRL_n_STG (0x00000004uL)
|
---|
1216 | #define DMAC15_CHCTRL_n_SWRST (0x00000008uL)
|
---|
1217 | #define DMAC15_CHCTRL_n_CLRRQ (0x00000010uL)
|
---|
1218 | #define DMAC15_CHCTRL_n_CLREND (0x00000020uL)
|
---|
1219 | #define DMAC15_CHCTRL_n_CLRTC (0x00000040uL)
|
---|
1220 | #define DMAC15_CHCTRL_n_SETSUS (0x00000100uL)
|
---|
1221 | #define DMAC15_CHCTRL_n_CLRSUS (0x00000200uL)
|
---|
1222 | #define DMAC15_CHCTRL_n_SETINTMSK (0x00010000uL)
|
---|
1223 | #define DMAC15_CHCTRL_n_CLRINTMSK (0x00020000uL)
|
---|
1224 |
|
---|
1225 | #define DMAC15_CHCFG_n_SEL (0x00000007uL)
|
---|
1226 | #define DMAC15_CHCFG_n_REQD (0x00000008uL)
|
---|
1227 | #define DMAC15_CHCFG_n_LOEN (0x00000010uL)
|
---|
1228 | #define DMAC15_CHCFG_n_HIEN (0x00000020uL)
|
---|
1229 | #define DMAC15_CHCFG_n_LVL (0x00000040uL)
|
---|
1230 | #define DMAC15_CHCFG_n_AM (0x00000700uL)
|
---|
1231 | #define DMAC15_CHCFG_n_SDS (0x0000F000uL)
|
---|
1232 | #define DMAC15_CHCFG_n_DDS (0x000F0000uL)
|
---|
1233 | #define DMAC15_CHCFG_n_SAD (0x00100000uL)
|
---|
1234 | #define DMAC15_CHCFG_n_DAD (0x00200000uL)
|
---|
1235 | #define DMAC15_CHCFG_n_TM (0x00400000uL)
|
---|
1236 | #define DMAC15_CHCFG_n_DEM (0x01000000uL)
|
---|
1237 | #define DMAC15_CHCFG_n_TCM (0x02000000uL)
|
---|
1238 | #define DMAC15_CHCFG_n_SBE (0x08000000uL)
|
---|
1239 | #define DMAC15_CHCFG_n_RSEL (0x10000000uL)
|
---|
1240 | #define DMAC15_CHCFG_n_RSW (0x20000000uL)
|
---|
1241 | #define DMAC15_CHCFG_n_REN (0x40000000uL)
|
---|
1242 | #define DMAC15_CHCFG_n_DMS (0x80000000uL)
|
---|
1243 |
|
---|
1244 | #define DMAC15_CHITVL_n_ITVL (0x0000FFFFuL)
|
---|
1245 |
|
---|
1246 | #define DMAC15_CHEXT_n_SCA (0x000000F0uL)
|
---|
1247 | #define DMAC15_CHEXT_n_DCA (0x0000F000uL)
|
---|
1248 |
|
---|
1249 | #define DMAC15_NXLA_n_NXLA (0xFFFFFFFFuL)
|
---|
1250 |
|
---|
1251 | #define DMAC15_CRLA_n_CRLA (0xFFFFFFFFuL)
|
---|
1252 |
|
---|
1253 | /* ---- DMAC8-15 ---- */
|
---|
1254 | #define DMAC815_DCTRL_8_15_PR (0x00000001uL)
|
---|
1255 | #define DMAC815_DCTRL_8_15_LVINT (0x00000002uL)
|
---|
1256 | #define DMAC815_DCTRL_8_15_LDCA (0x0000003CuL)
|
---|
1257 | #define DMAC815_DCTRL_8_15_LWCA (0x00003C00uL)
|
---|
1258 |
|
---|
1259 | #define DMAC815_DSTAT_EN_8_15_EN8 (0x00000001uL)
|
---|
1260 | #define DMAC815_DSTAT_EN_8_15_EN9 (0x00000002uL)
|
---|
1261 | #define DMAC815_DSTAT_EN_8_15_EN10 (0x00000004uL)
|
---|
1262 | #define DMAC815_DSTAT_EN_8_15_EN11 (0x00000008uL)
|
---|
1263 | #define DMAC815_DSTAT_EN_8_15_EN12 (0x00000010uL)
|
---|
1264 | #define DMAC815_DSTAT_EN_8_15_EN13 (0x00000020uL)
|
---|
1265 | #define DMAC815_DSTAT_EN_8_15_EN14 (0x00000040uL)
|
---|
1266 | #define DMAC815_DSTAT_EN_8_15_EN15 (0x00000080uL)
|
---|
1267 |
|
---|
1268 | #define DMAC815_DSTAT_ER_8_15_ER8 (0x00000001uL)
|
---|
1269 | #define DMAC815_DSTAT_ER_8_15_ER9 (0x00000002uL)
|
---|
1270 | #define DMAC815_DSTAT_ER_8_15_ER10 (0x00000004uL)
|
---|
1271 | #define DMAC815_DSTAT_ER_8_15_ER11 (0x00000008uL)
|
---|
1272 | #define DMAC815_DSTAT_ER_8_15_ER12 (0x00000010uL)
|
---|
1273 | #define DMAC815_DSTAT_ER_8_15_ER13 (0x00000020uL)
|
---|
1274 | #define DMAC815_DSTAT_ER_8_15_ER14 (0x00000040uL)
|
---|
1275 | #define DMAC815_DSTAT_ER_8_15_ER15 (0x00000080uL)
|
---|
1276 |
|
---|
1277 | #define DMAC815_DSTAT_END_8_15_END8 (0x00000001uL)
|
---|
1278 | #define DMAC815_DSTAT_END_8_15_END9 (0x00000002uL)
|
---|
1279 | #define DMAC815_DSTAT_END_8_15_END10 (0x00000004uL)
|
---|
1280 | #define DMAC815_DSTAT_END_8_15_END11 (0x00000008uL)
|
---|
1281 | #define DMAC815_DSTAT_END_8_15_END12 (0x00000010uL)
|
---|
1282 | #define DMAC815_DSTAT_END_8_15_END13 (0x00000020uL)
|
---|
1283 | #define DMAC815_DSTAT_END_8_15_END14 (0x00000040uL)
|
---|
1284 | #define DMAC815_DSTAT_END_8_15_END15 (0x00000080uL)
|
---|
1285 |
|
---|
1286 | #define DMAC815_DSTAT_TC_8_15_TC8 (0x00000001uL)
|
---|
1287 | #define DMAC815_DSTAT_TC_8_15_TC9 (0x00000002uL)
|
---|
1288 | #define DMAC815_DSTAT_TC_8_15_TC10 (0x00000004uL)
|
---|
1289 | #define DMAC815_DSTAT_TC_8_15_TC11 (0x00000008uL)
|
---|
1290 | #define DMAC815_DSTAT_TC_8_15_TC12 (0x00000010uL)
|
---|
1291 | #define DMAC815_DSTAT_TC_8_15_TC13 (0x00000020uL)
|
---|
1292 | #define DMAC815_DSTAT_TC_8_15_TC14 (0x00000040uL)
|
---|
1293 | #define DMAC815_DSTAT_TC_8_15_TC15 (0x00000080uL)
|
---|
1294 |
|
---|
1295 | #define DMAC815_DSTAT_SUS_8_15_SUS8 (0x00000001uL)
|
---|
1296 | #define DMAC815_DSTAT_SUS_8_15_SUS9 (0x00000002uL)
|
---|
1297 | #define DMAC815_DSTAT_SUS_8_15_SUS10 (0x00000004uL)
|
---|
1298 | #define DMAC815_DSTAT_SUS_8_15_SUS11 (0x00000008uL)
|
---|
1299 | #define DMAC815_DSTAT_SUS_8_15_SUS12 (0x00000010uL)
|
---|
1300 | #define DMAC815_DSTAT_SUS_8_15_SUS13 (0x00000020uL)
|
---|
1301 | #define DMAC815_DSTAT_SUS_8_15_SUS14 (0x00000040uL)
|
---|
1302 | #define DMAC815_DSTAT_SUS_8_15_SUS15 (0x00000080uL)
|
---|
1303 |
|
---|
1304 | /* ---- DMAC0-1 ---- */
|
---|
1305 | #define DMAC01_DMARS_CH0_RID (0x00000003uL)
|
---|
1306 | #define DMAC01_DMARS_CH0_MID (0x000001FCuL)
|
---|
1307 | #define DMAC01_DMARS_CH1_RID (0x00030000uL)
|
---|
1308 | #define DMAC01_DMARS_CH1_MID (0x01FC0000uL)
|
---|
1309 |
|
---|
1310 | /* ---- DMAC2-3 ---- */
|
---|
1311 | #define DMAC23_DMARS_CH2_RID (0x00000003uL)
|
---|
1312 | #define DMAC23_DMARS_CH2_MID (0x000001FCuL)
|
---|
1313 | #define DMAC23_DMARS_CH3_RID (0x00030000uL)
|
---|
1314 | #define DMAC23_DMARS_CH3_MID (0x01FC0000uL)
|
---|
1315 |
|
---|
1316 | /* ---- DMAC4-5 ---- */
|
---|
1317 | #define DMAC45_DMARS_CH4_RID (0x00000003uL)
|
---|
1318 | #define DMAC45_DMARS_CH4_MID (0x000001FCuL)
|
---|
1319 | #define DMAC45_DMARS_CH5_RID (0x00030000uL)
|
---|
1320 | #define DMAC45_DMARS_CH5_MID (0x01FC0000uL)
|
---|
1321 |
|
---|
1322 | /* ---- DMAC6-7 ---- */
|
---|
1323 | #define DMAC67_DMARS_CH6_RID (0x00000003uL)
|
---|
1324 | #define DMAC67_DMARS_CH6_MID (0x000001FCuL)
|
---|
1325 | #define DMAC67_DMARS_CH7_RID (0x00030000uL)
|
---|
1326 | #define DMAC67_DMARS_CH7_MID (0x01FC0000uL)
|
---|
1327 |
|
---|
1328 | /* ---- DMAC8-9 ---- */
|
---|
1329 | #define DMAC89_DMARS_CH8_RID (0x00000003uL)
|
---|
1330 | #define DMAC89_DMARS_CH8_MID (0x000001FCuL)
|
---|
1331 | #define DMAC89_DMARS_CH9_RID (0x00030000uL)
|
---|
1332 | #define DMAC89_DMARS_CH9_MID (0x01FC0000uL)
|
---|
1333 |
|
---|
1334 | /* ---- DMAC10-11 ---- */
|
---|
1335 | #define DMAC1011_DMARS_CH10_RID (0x00000003uL)
|
---|
1336 | #define DMAC1011_DMARS_CH10_MID (0x000001FCuL)
|
---|
1337 | #define DMAC1011_DMARS_CH11_RID (0x00030000uL)
|
---|
1338 | #define DMAC1011_DMARS_CH11_MID (0x01FC0000uL)
|
---|
1339 |
|
---|
1340 | /* ---- DMAC12-13 ---- */
|
---|
1341 | #define DMAC1213_DMARS_CH12_RID (0x00000003uL)
|
---|
1342 | #define DMAC1213_DMARS_CH12_MID (0x000001FCuL)
|
---|
1343 | #define DMAC1213_DMARS_CH13_RID (0x00030000uL)
|
---|
1344 | #define DMAC1213_DMARS_CH13_MID (0x01FC0000uL)
|
---|
1345 |
|
---|
1346 | /* ---- DMAC14-15 ---- */
|
---|
1347 | #define DMAC1415_DMARS_CH14_RID (0x00000003uL)
|
---|
1348 | #define DMAC1415_DMARS_CH14_MID (0x000001FCuL)
|
---|
1349 | #define DMAC1415_DMARS_CH15_RID (0x00030000uL)
|
---|
1350 | #define DMAC1415_DMARS_CH15_MID (0x01FC0000uL)
|
---|
1351 |
|
---|
1352 |
|
---|
1353 | /* ==== Shift values for IO registers ==== */
|
---|
1354 | /* ---- DMAC0 ---- */
|
---|
1355 | #define DMAC0_N0SA_n_SA_SHIFT (0u)
|
---|
1356 |
|
---|
1357 | #define DMAC0_N0DA_n_DA_SHIFT (0u)
|
---|
1358 |
|
---|
1359 | #define DMAC0_N0TB_n_TB_SHIFT (0u)
|
---|
1360 |
|
---|
1361 | #define DMAC0_N1SA_n_SA_SHIFT (0u)
|
---|
1362 |
|
---|
1363 | #define DMAC0_N1DA_n_DA_SHIFT (0u)
|
---|
1364 |
|
---|
1365 | #define DMAC0_N1TB_n_TB_SHIFT (0u)
|
---|
1366 |
|
---|
1367 | #define DMAC0_CRSA_n_CRSA_SHIFT (0u)
|
---|
1368 |
|
---|
1369 | #define DMAC0_CRDA_n_CRDA_SHIFT (0u)
|
---|
1370 |
|
---|
1371 | #define DMAC0_CRTB_n_CRTB_SHIFT (0u)
|
---|
1372 |
|
---|
1373 | #define DMAC0_CHSTAT_n_EN_SHIFT (0u)
|
---|
1374 | #define DMAC0_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1375 | #define DMAC0_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1376 | #define DMAC0_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1377 | #define DMAC0_CHSTAT_n_ER_SHIFT (4u)
|
---|
1378 | #define DMAC0_CHSTAT_n_END_SHIFT (5u)
|
---|
1379 | #define DMAC0_CHSTAT_n_TC_SHIFT (6u)
|
---|
1380 | #define DMAC0_CHSTAT_n_SR_SHIFT (7u)
|
---|
1381 | #define DMAC0_CHSTAT_n_DL_SHIFT (8u)
|
---|
1382 | #define DMAC0_CHSTAT_n_DW_SHIFT (9u)
|
---|
1383 | #define DMAC0_CHSTAT_n_DER_SHIFT (10u)
|
---|
1384 | #define DMAC0_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1385 | #define DMAC0_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1386 |
|
---|
1387 | #define DMAC0_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1388 | #define DMAC0_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1389 | #define DMAC0_CHCTRL_n_STG_SHIFT (2u)
|
---|
1390 | #define DMAC0_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1391 | #define DMAC0_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1392 | #define DMAC0_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1393 | #define DMAC0_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1394 | #define DMAC0_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1395 | #define DMAC0_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1396 | #define DMAC0_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1397 | #define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1398 |
|
---|
1399 | #define DMAC0_CHCFG_n_SEL_SHIFT (0u)
|
---|
1400 | #define DMAC0_CHCFG_n_REQD_SHIFT (3u)
|
---|
1401 | #define DMAC0_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1402 | #define DMAC0_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1403 | #define DMAC0_CHCFG_n_LVL_SHIFT (6u)
|
---|
1404 | #define DMAC0_CHCFG_n_AM_SHIFT (8u)
|
---|
1405 | #define DMAC0_CHCFG_n_SDS_SHIFT (12u)
|
---|
1406 | #define DMAC0_CHCFG_n_DDS_SHIFT (16u)
|
---|
1407 | #define DMAC0_CHCFG_n_SAD_SHIFT (20u)
|
---|
1408 | #define DMAC0_CHCFG_n_DAD_SHIFT (21u)
|
---|
1409 | #define DMAC0_CHCFG_n_TM_SHIFT (22u)
|
---|
1410 | #define DMAC0_CHCFG_n_DEM_SHIFT (24u)
|
---|
1411 | #define DMAC0_CHCFG_n_TCM_SHIFT (25u)
|
---|
1412 | #define DMAC0_CHCFG_n_SBE_SHIFT (27u)
|
---|
1413 | #define DMAC0_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1414 | #define DMAC0_CHCFG_n_RSW_SHIFT (29u)
|
---|
1415 | #define DMAC0_CHCFG_n_REN_SHIFT (30u)
|
---|
1416 | #define DMAC0_CHCFG_n_DMS_SHIFT (31u)
|
---|
1417 |
|
---|
1418 | #define DMAC0_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1419 |
|
---|
1420 | #define DMAC0_CHEXT_n_SCA_SHIFT (4u)
|
---|
1421 | #define DMAC0_CHEXT_n_DCA_SHIFT (12u)
|
---|
1422 |
|
---|
1423 | #define DMAC0_NXLA_n_NXLA_SHIFT (0u)
|
---|
1424 |
|
---|
1425 | #define DMAC0_CRLA_n_CRLA_SHIFT (0u)
|
---|
1426 |
|
---|
1427 | /* ---- DMAC1 ---- */
|
---|
1428 | #define DMAC1_N0SA_n_SA_SHIFT (0u)
|
---|
1429 |
|
---|
1430 | #define DMAC1_N0DA_n_DA_SHIFT (0u)
|
---|
1431 |
|
---|
1432 | #define DMAC1_N0TB_n_TB_SHIFT (0u)
|
---|
1433 |
|
---|
1434 | #define DMAC1_N1SA_n_SA_SHIFT (0u)
|
---|
1435 |
|
---|
1436 | #define DMAC1_N1DA_n_DA_SHIFT (0u)
|
---|
1437 |
|
---|
1438 | #define DMAC1_N1TB_n_TB_SHIFT (0u)
|
---|
1439 |
|
---|
1440 | #define DMAC1_CRSA_n_CRSA_SHIFT (0u)
|
---|
1441 |
|
---|
1442 | #define DMAC1_CRDA_n_CRDA_SHIFT (0u)
|
---|
1443 |
|
---|
1444 | #define DMAC1_CRTB_n_CRTB_SHIFT (0u)
|
---|
1445 |
|
---|
1446 | #define DMAC1_CHSTAT_n_EN_SHIFT (0u)
|
---|
1447 | #define DMAC1_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1448 | #define DMAC1_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1449 | #define DMAC1_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1450 | #define DMAC1_CHSTAT_n_ER_SHIFT (4u)
|
---|
1451 | #define DMAC1_CHSTAT_n_END_SHIFT (5u)
|
---|
1452 | #define DMAC1_CHSTAT_n_TC_SHIFT (6u)
|
---|
1453 | #define DMAC1_CHSTAT_n_SR_SHIFT (7u)
|
---|
1454 | #define DMAC1_CHSTAT_n_DL_SHIFT (8u)
|
---|
1455 | #define DMAC1_CHSTAT_n_DW_SHIFT (9u)
|
---|
1456 | #define DMAC1_CHSTAT_n_DER_SHIFT (10u)
|
---|
1457 | #define DMAC1_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1458 | #define DMAC1_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1459 |
|
---|
1460 | #define DMAC1_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1461 | #define DMAC1_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1462 | #define DMAC1_CHCTRL_n_STG_SHIFT (2u)
|
---|
1463 | #define DMAC1_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1464 | #define DMAC1_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1465 | #define DMAC1_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1466 | #define DMAC1_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1467 | #define DMAC1_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1468 | #define DMAC1_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1469 | #define DMAC1_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1470 | #define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1471 |
|
---|
1472 | #define DMAC1_CHCFG_n_SEL_SHIFT (0u)
|
---|
1473 | #define DMAC1_CHCFG_n_REQD_SHIFT (3u)
|
---|
1474 | #define DMAC1_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1475 | #define DMAC1_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1476 | #define DMAC1_CHCFG_n_LVL_SHIFT (6u)
|
---|
1477 | #define DMAC1_CHCFG_n_AM_SHIFT (8u)
|
---|
1478 | #define DMAC1_CHCFG_n_SDS_SHIFT (12u)
|
---|
1479 | #define DMAC1_CHCFG_n_DDS_SHIFT (16u)
|
---|
1480 | #define DMAC1_CHCFG_n_SAD_SHIFT (20u)
|
---|
1481 | #define DMAC1_CHCFG_n_DAD_SHIFT (21u)
|
---|
1482 | #define DMAC1_CHCFG_n_TM_SHIFT (22u)
|
---|
1483 | #define DMAC1_CHCFG_n_DEM_SHIFT (24u)
|
---|
1484 | #define DMAC1_CHCFG_n_TCM_SHIFT (25u)
|
---|
1485 | #define DMAC1_CHCFG_n_SBE_SHIFT (27u)
|
---|
1486 | #define DMAC1_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1487 | #define DMAC1_CHCFG_n_RSW_SHIFT (29u)
|
---|
1488 | #define DMAC1_CHCFG_n_REN_SHIFT (30u)
|
---|
1489 | #define DMAC1_CHCFG_n_DMS_SHIFT (31u)
|
---|
1490 |
|
---|
1491 | #define DMAC1_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1492 |
|
---|
1493 | #define DMAC1_CHEXT_n_SCA_SHIFT (4u)
|
---|
1494 | #define DMAC1_CHEXT_n_DCA_SHIFT (12u)
|
---|
1495 |
|
---|
1496 | #define DMAC1_NXLA_n_NXLA_SHIFT (0u)
|
---|
1497 |
|
---|
1498 | #define DMAC1_CRLA_n_CRLA_SHIFT (0u)
|
---|
1499 |
|
---|
1500 | /* ---- DMAC2 ---- */
|
---|
1501 | #define DMAC2_N0SA_n_SA_SHIFT (0u)
|
---|
1502 |
|
---|
1503 | #define DMAC2_N0DA_n_DA_SHIFT (0u)
|
---|
1504 |
|
---|
1505 | #define DMAC2_N0TB_n_TB_SHIFT (0u)
|
---|
1506 |
|
---|
1507 | #define DMAC2_N1SA_n_SA_SHIFT (0u)
|
---|
1508 |
|
---|
1509 | #define DMAC2_N1DA_n_DA_SHIFT (0u)
|
---|
1510 |
|
---|
1511 | #define DMAC2_N1TB_n_TB_SHIFT (0u)
|
---|
1512 |
|
---|
1513 | #define DMAC2_CRSA_n_CRSA_SHIFT (0u)
|
---|
1514 |
|
---|
1515 | #define DMAC2_CRDA_n_CRDA_SHIFT (0u)
|
---|
1516 |
|
---|
1517 | #define DMAC2_CRTB_n_CRTB_SHIFT (0u)
|
---|
1518 |
|
---|
1519 | #define DMAC2_CHSTAT_n_EN_SHIFT (0u)
|
---|
1520 | #define DMAC2_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1521 | #define DMAC2_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1522 | #define DMAC2_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1523 | #define DMAC2_CHSTAT_n_ER_SHIFT (4u)
|
---|
1524 | #define DMAC2_CHSTAT_n_END_SHIFT (5u)
|
---|
1525 | #define DMAC2_CHSTAT_n_TC_SHIFT (6u)
|
---|
1526 | #define DMAC2_CHSTAT_n_SR_SHIFT (7u)
|
---|
1527 | #define DMAC2_CHSTAT_n_DL_SHIFT (8u)
|
---|
1528 | #define DMAC2_CHSTAT_n_DW_SHIFT (9u)
|
---|
1529 | #define DMAC2_CHSTAT_n_DER_SHIFT (10u)
|
---|
1530 | #define DMAC2_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1531 | #define DMAC2_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1532 |
|
---|
1533 | #define DMAC2_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1534 | #define DMAC2_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1535 | #define DMAC2_CHCTRL_n_STG_SHIFT (2u)
|
---|
1536 | #define DMAC2_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1537 | #define DMAC2_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1538 | #define DMAC2_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1539 | #define DMAC2_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1540 | #define DMAC2_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1541 | #define DMAC2_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1542 | #define DMAC2_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1543 | #define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1544 |
|
---|
1545 | #define DMAC2_CHCFG_n_SEL_SHIFT (0u)
|
---|
1546 | #define DMAC2_CHCFG_n_REQD_SHIFT (3u)
|
---|
1547 | #define DMAC2_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1548 | #define DMAC2_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1549 | #define DMAC2_CHCFG_n_LVL_SHIFT (6u)
|
---|
1550 | #define DMAC2_CHCFG_n_AM_SHIFT (8u)
|
---|
1551 | #define DMAC2_CHCFG_n_SDS_SHIFT (12u)
|
---|
1552 | #define DMAC2_CHCFG_n_DDS_SHIFT (16u)
|
---|
1553 | #define DMAC2_CHCFG_n_SAD_SHIFT (20u)
|
---|
1554 | #define DMAC2_CHCFG_n_DAD_SHIFT (21u)
|
---|
1555 | #define DMAC2_CHCFG_n_TM_SHIFT (22u)
|
---|
1556 | #define DMAC2_CHCFG_n_DEM_SHIFT (24u)
|
---|
1557 | #define DMAC2_CHCFG_n_TCM_SHIFT (25u)
|
---|
1558 | #define DMAC2_CHCFG_n_SBE_SHIFT (27u)
|
---|
1559 | #define DMAC2_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1560 | #define DMAC2_CHCFG_n_RSW_SHIFT (29u)
|
---|
1561 | #define DMAC2_CHCFG_n_REN_SHIFT (30u)
|
---|
1562 | #define DMAC2_CHCFG_n_DMS_SHIFT (31u)
|
---|
1563 |
|
---|
1564 | #define DMAC2_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1565 |
|
---|
1566 | #define DMAC2_CHEXT_n_SCA_SHIFT (4u)
|
---|
1567 | #define DMAC2_CHEXT_n_DCA_SHIFT (12u)
|
---|
1568 |
|
---|
1569 | #define DMAC2_NXLA_n_NXLA_SHIFT (0u)
|
---|
1570 |
|
---|
1571 | #define DMAC2_CRLA_n_CRLA_SHIFT (0u)
|
---|
1572 |
|
---|
1573 | /* ---- DMAC3 ---- */
|
---|
1574 | #define DMAC3_N0SA_n_SA_SHIFT (0u)
|
---|
1575 |
|
---|
1576 | #define DMAC3_N0DA_n_DA_SHIFT (0u)
|
---|
1577 |
|
---|
1578 | #define DMAC3_N0TB_n_TB_SHIFT (0u)
|
---|
1579 |
|
---|
1580 | #define DMAC3_N1SA_n_SA_SHIFT (0u)
|
---|
1581 |
|
---|
1582 | #define DMAC3_N1DA_n_DA_SHIFT (0u)
|
---|
1583 |
|
---|
1584 | #define DMAC3_N1TB_n_TB_SHIFT (0u)
|
---|
1585 |
|
---|
1586 | #define DMAC3_CRSA_n_CRSA_SHIFT (0u)
|
---|
1587 |
|
---|
1588 | #define DMAC3_CRDA_n_CRDA_SHIFT (0u)
|
---|
1589 |
|
---|
1590 | #define DMAC3_CRTB_n_CRTB_SHIFT (0u)
|
---|
1591 |
|
---|
1592 | #define DMAC3_CHSTAT_n_EN_SHIFT (0u)
|
---|
1593 | #define DMAC3_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1594 | #define DMAC3_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1595 | #define DMAC3_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1596 | #define DMAC3_CHSTAT_n_ER_SHIFT (4u)
|
---|
1597 | #define DMAC3_CHSTAT_n_END_SHIFT (5u)
|
---|
1598 | #define DMAC3_CHSTAT_n_TC_SHIFT (6u)
|
---|
1599 | #define DMAC3_CHSTAT_n_SR_SHIFT (7u)
|
---|
1600 | #define DMAC3_CHSTAT_n_DL_SHIFT (8u)
|
---|
1601 | #define DMAC3_CHSTAT_n_DW_SHIFT (9u)
|
---|
1602 | #define DMAC3_CHSTAT_n_DER_SHIFT (10u)
|
---|
1603 | #define DMAC3_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1604 | #define DMAC3_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1605 |
|
---|
1606 | #define DMAC3_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1607 | #define DMAC3_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1608 | #define DMAC3_CHCTRL_n_STG_SHIFT (2u)
|
---|
1609 | #define DMAC3_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1610 | #define DMAC3_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1611 | #define DMAC3_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1612 | #define DMAC3_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1613 | #define DMAC3_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1614 | #define DMAC3_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1615 | #define DMAC3_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1616 | #define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1617 |
|
---|
1618 | #define DMAC3_CHCFG_n_SEL_SHIFT (0u)
|
---|
1619 | #define DMAC3_CHCFG_n_REQD_SHIFT (3u)
|
---|
1620 | #define DMAC3_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1621 | #define DMAC3_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1622 | #define DMAC3_CHCFG_n_LVL_SHIFT (6u)
|
---|
1623 | #define DMAC3_CHCFG_n_AM_SHIFT (8u)
|
---|
1624 | #define DMAC3_CHCFG_n_SDS_SHIFT (12u)
|
---|
1625 | #define DMAC3_CHCFG_n_DDS_SHIFT (16u)
|
---|
1626 | #define DMAC3_CHCFG_n_SAD_SHIFT (20u)
|
---|
1627 | #define DMAC3_CHCFG_n_DAD_SHIFT (21u)
|
---|
1628 | #define DMAC3_CHCFG_n_TM_SHIFT (22u)
|
---|
1629 | #define DMAC3_CHCFG_n_DEM_SHIFT (24u)
|
---|
1630 | #define DMAC3_CHCFG_n_TCM_SHIFT (25u)
|
---|
1631 | #define DMAC3_CHCFG_n_SBE_SHIFT (27u)
|
---|
1632 | #define DMAC3_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1633 | #define DMAC3_CHCFG_n_RSW_SHIFT (29u)
|
---|
1634 | #define DMAC3_CHCFG_n_REN_SHIFT (30u)
|
---|
1635 | #define DMAC3_CHCFG_n_DMS_SHIFT (31u)
|
---|
1636 |
|
---|
1637 | #define DMAC3_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1638 |
|
---|
1639 | #define DMAC3_CHEXT_n_SCA_SHIFT (4u)
|
---|
1640 | #define DMAC3_CHEXT_n_DCA_SHIFT (12u)
|
---|
1641 |
|
---|
1642 | #define DMAC3_NXLA_n_NXLA_SHIFT (0u)
|
---|
1643 |
|
---|
1644 | #define DMAC3_CRLA_n_CRLA_SHIFT (0u)
|
---|
1645 |
|
---|
1646 | /* ---- DMAC4 ---- */
|
---|
1647 | #define DMAC4_N0SA_n_SA_SHIFT (0u)
|
---|
1648 |
|
---|
1649 | #define DMAC4_N0DA_n_DA_SHIFT (0u)
|
---|
1650 |
|
---|
1651 | #define DMAC4_N0TB_n_TB_SHIFT (0u)
|
---|
1652 |
|
---|
1653 | #define DMAC4_N1SA_n_SA_SHIFT (0u)
|
---|
1654 |
|
---|
1655 | #define DMAC4_N1DA_n_DA_SHIFT (0u)
|
---|
1656 |
|
---|
1657 | #define DMAC4_N1TB_n_TB_SHIFT (0u)
|
---|
1658 |
|
---|
1659 | #define DMAC4_CRSA_n_CRSA_SHIFT (0u)
|
---|
1660 |
|
---|
1661 | #define DMAC4_CRDA_n_CRDA_SHIFT (0u)
|
---|
1662 |
|
---|
1663 | #define DMAC4_CRTB_n_CRTB_SHIFT (0u)
|
---|
1664 |
|
---|
1665 | #define DMAC4_CHSTAT_n_EN_SHIFT (0u)
|
---|
1666 | #define DMAC4_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1667 | #define DMAC4_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1668 | #define DMAC4_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1669 | #define DMAC4_CHSTAT_n_ER_SHIFT (4u)
|
---|
1670 | #define DMAC4_CHSTAT_n_END_SHIFT (5u)
|
---|
1671 | #define DMAC4_CHSTAT_n_TC_SHIFT (6u)
|
---|
1672 | #define DMAC4_CHSTAT_n_SR_SHIFT (7u)
|
---|
1673 | #define DMAC4_CHSTAT_n_DL_SHIFT (8u)
|
---|
1674 | #define DMAC4_CHSTAT_n_DW_SHIFT (9u)
|
---|
1675 | #define DMAC4_CHSTAT_n_DER_SHIFT (10u)
|
---|
1676 | #define DMAC4_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1677 | #define DMAC4_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1678 |
|
---|
1679 | #define DMAC4_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1680 | #define DMAC4_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1681 | #define DMAC4_CHCTRL_n_STG_SHIFT (2u)
|
---|
1682 | #define DMAC4_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1683 | #define DMAC4_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1684 | #define DMAC4_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1685 | #define DMAC4_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1686 | #define DMAC4_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1687 | #define DMAC4_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1688 | #define DMAC4_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1689 | #define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1690 |
|
---|
1691 | #define DMAC4_CHCFG_n_SEL_SHIFT (0u)
|
---|
1692 | #define DMAC4_CHCFG_n_REQD_SHIFT (3u)
|
---|
1693 | #define DMAC4_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1694 | #define DMAC4_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1695 | #define DMAC4_CHCFG_n_LVL_SHIFT (6u)
|
---|
1696 | #define DMAC4_CHCFG_n_AM_SHIFT (8u)
|
---|
1697 | #define DMAC4_CHCFG_n_SDS_SHIFT (12u)
|
---|
1698 | #define DMAC4_CHCFG_n_DDS_SHIFT (16u)
|
---|
1699 | #define DMAC4_CHCFG_n_SAD_SHIFT (20u)
|
---|
1700 | #define DMAC4_CHCFG_n_DAD_SHIFT (21u)
|
---|
1701 | #define DMAC4_CHCFG_n_TM_SHIFT (22u)
|
---|
1702 | #define DMAC4_CHCFG_n_DEM_SHIFT (24u)
|
---|
1703 | #define DMAC4_CHCFG_n_TCM_SHIFT (25u)
|
---|
1704 | #define DMAC4_CHCFG_n_SBE_SHIFT (27u)
|
---|
1705 | #define DMAC4_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1706 | #define DMAC4_CHCFG_n_RSW_SHIFT (29u)
|
---|
1707 | #define DMAC4_CHCFG_n_REN_SHIFT (30u)
|
---|
1708 | #define DMAC4_CHCFG_n_DMS_SHIFT (31u)
|
---|
1709 |
|
---|
1710 | #define DMAC4_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1711 |
|
---|
1712 | #define DMAC4_CHEXT_n_SCA_SHIFT (4u)
|
---|
1713 | #define DMAC4_CHEXT_n_DCA_SHIFT (12u)
|
---|
1714 |
|
---|
1715 | #define DMAC4_NXLA_n_NXLA_SHIFT (0u)
|
---|
1716 |
|
---|
1717 | #define DMAC4_CRLA_n_CRLA_SHIFT (0u)
|
---|
1718 |
|
---|
1719 | /* ---- DMAC5 ---- */
|
---|
1720 | #define DMAC5_N0SA_n_SA_SHIFT (0u)
|
---|
1721 |
|
---|
1722 | #define DMAC5_N0DA_n_DA_SHIFT (0u)
|
---|
1723 |
|
---|
1724 | #define DMAC5_N0TB_n_TB_SHIFT (0u)
|
---|
1725 |
|
---|
1726 | #define DMAC5_N1SA_n_SA_SHIFT (0u)
|
---|
1727 |
|
---|
1728 | #define DMAC5_N1DA_n_DA_SHIFT (0u)
|
---|
1729 |
|
---|
1730 | #define DMAC5_N1TB_n_TB_SHIFT (0u)
|
---|
1731 |
|
---|
1732 | #define DMAC5_CRSA_n_CRSA_SHIFT (0u)
|
---|
1733 |
|
---|
1734 | #define DMAC5_CRDA_n_CRDA_SHIFT (0u)
|
---|
1735 |
|
---|
1736 | #define DMAC5_CRTB_n_CRTB_SHIFT (0u)
|
---|
1737 |
|
---|
1738 | #define DMAC5_CHSTAT_n_EN_SHIFT (0u)
|
---|
1739 | #define DMAC5_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1740 | #define DMAC5_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1741 | #define DMAC5_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1742 | #define DMAC5_CHSTAT_n_ER_SHIFT (4u)
|
---|
1743 | #define DMAC5_CHSTAT_n_END_SHIFT (5u)
|
---|
1744 | #define DMAC5_CHSTAT_n_TC_SHIFT (6u)
|
---|
1745 | #define DMAC5_CHSTAT_n_SR_SHIFT (7u)
|
---|
1746 | #define DMAC5_CHSTAT_n_DL_SHIFT (8u)
|
---|
1747 | #define DMAC5_CHSTAT_n_DW_SHIFT (9u)
|
---|
1748 | #define DMAC5_CHSTAT_n_DER_SHIFT (10u)
|
---|
1749 | #define DMAC5_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1750 | #define DMAC5_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1751 |
|
---|
1752 | #define DMAC5_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1753 | #define DMAC5_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1754 | #define DMAC5_CHCTRL_n_STG_SHIFT (2u)
|
---|
1755 | #define DMAC5_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1756 | #define DMAC5_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1757 | #define DMAC5_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1758 | #define DMAC5_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1759 | #define DMAC5_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1760 | #define DMAC5_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1761 | #define DMAC5_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1762 | #define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1763 |
|
---|
1764 | #define DMAC5_CHCFG_n_SEL_SHIFT (0u)
|
---|
1765 | #define DMAC5_CHCFG_n_REQD_SHIFT (3u)
|
---|
1766 | #define DMAC5_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1767 | #define DMAC5_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1768 | #define DMAC5_CHCFG_n_LVL_SHIFT (6u)
|
---|
1769 | #define DMAC5_CHCFG_n_AM_SHIFT (8u)
|
---|
1770 | #define DMAC5_CHCFG_n_SDS_SHIFT (12u)
|
---|
1771 | #define DMAC5_CHCFG_n_DDS_SHIFT (16u)
|
---|
1772 | #define DMAC5_CHCFG_n_SAD_SHIFT (20u)
|
---|
1773 | #define DMAC5_CHCFG_n_DAD_SHIFT (21u)
|
---|
1774 | #define DMAC5_CHCFG_n_TM_SHIFT (22u)
|
---|
1775 | #define DMAC5_CHCFG_n_DEM_SHIFT (24u)
|
---|
1776 | #define DMAC5_CHCFG_n_TCM_SHIFT (25u)
|
---|
1777 | #define DMAC5_CHCFG_n_SBE_SHIFT (27u)
|
---|
1778 | #define DMAC5_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1779 | #define DMAC5_CHCFG_n_RSW_SHIFT (29u)
|
---|
1780 | #define DMAC5_CHCFG_n_REN_SHIFT (30u)
|
---|
1781 | #define DMAC5_CHCFG_n_DMS_SHIFT (31u)
|
---|
1782 |
|
---|
1783 | #define DMAC5_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1784 |
|
---|
1785 | #define DMAC5_CHEXT_n_SCA_SHIFT (4u)
|
---|
1786 | #define DMAC5_CHEXT_n_DCA_SHIFT (12u)
|
---|
1787 |
|
---|
1788 | #define DMAC5_NXLA_n_NXLA_SHIFT (0u)
|
---|
1789 |
|
---|
1790 | #define DMAC5_CRLA_n_CRLA_SHIFT (0u)
|
---|
1791 |
|
---|
1792 | /* ---- DMAC6 ---- */
|
---|
1793 | #define DMAC6_N0SA_n_SA_SHIFT (0u)
|
---|
1794 |
|
---|
1795 | #define DMAC6_N0DA_n_DA_SHIFT (0u)
|
---|
1796 |
|
---|
1797 | #define DMAC6_N0TB_n_TB_SHIFT (0u)
|
---|
1798 |
|
---|
1799 | #define DMAC6_N1SA_n_SA_SHIFT (0u)
|
---|
1800 |
|
---|
1801 | #define DMAC6_N1DA_n_DA_SHIFT (0u)
|
---|
1802 |
|
---|
1803 | #define DMAC6_N1TB_n_TB_SHIFT (0u)
|
---|
1804 |
|
---|
1805 | #define DMAC6_CRSA_n_CRSA_SHIFT (0u)
|
---|
1806 |
|
---|
1807 | #define DMAC6_CRDA_n_CRDA_SHIFT (0u)
|
---|
1808 |
|
---|
1809 | #define DMAC6_CRTB_n_CRTB_SHIFT (0u)
|
---|
1810 |
|
---|
1811 | #define DMAC6_CHSTAT_n_EN_SHIFT (0u)
|
---|
1812 | #define DMAC6_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1813 | #define DMAC6_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1814 | #define DMAC6_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1815 | #define DMAC6_CHSTAT_n_ER_SHIFT (4u)
|
---|
1816 | #define DMAC6_CHSTAT_n_END_SHIFT (5u)
|
---|
1817 | #define DMAC6_CHSTAT_n_TC_SHIFT (6u)
|
---|
1818 | #define DMAC6_CHSTAT_n_SR_SHIFT (7u)
|
---|
1819 | #define DMAC6_CHSTAT_n_DL_SHIFT (8u)
|
---|
1820 | #define DMAC6_CHSTAT_n_DW_SHIFT (9u)
|
---|
1821 | #define DMAC6_CHSTAT_n_DER_SHIFT (10u)
|
---|
1822 | #define DMAC6_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1823 | #define DMAC6_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1824 |
|
---|
1825 | #define DMAC6_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1826 | #define DMAC6_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1827 | #define DMAC6_CHCTRL_n_STG_SHIFT (2u)
|
---|
1828 | #define DMAC6_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1829 | #define DMAC6_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1830 | #define DMAC6_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1831 | #define DMAC6_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1832 | #define DMAC6_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1833 | #define DMAC6_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1834 | #define DMAC6_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1835 | #define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1836 |
|
---|
1837 | #define DMAC6_CHCFG_n_SEL_SHIFT (0u)
|
---|
1838 | #define DMAC6_CHCFG_n_REQD_SHIFT (3u)
|
---|
1839 | #define DMAC6_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1840 | #define DMAC6_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1841 | #define DMAC6_CHCFG_n_LVL_SHIFT (6u)
|
---|
1842 | #define DMAC6_CHCFG_n_AM_SHIFT (8u)
|
---|
1843 | #define DMAC6_CHCFG_n_SDS_SHIFT (12u)
|
---|
1844 | #define DMAC6_CHCFG_n_DDS_SHIFT (16u)
|
---|
1845 | #define DMAC6_CHCFG_n_SAD_SHIFT (20u)
|
---|
1846 | #define DMAC6_CHCFG_n_DAD_SHIFT (21u)
|
---|
1847 | #define DMAC6_CHCFG_n_TM_SHIFT (22u)
|
---|
1848 | #define DMAC6_CHCFG_n_DEM_SHIFT (24u)
|
---|
1849 | #define DMAC6_CHCFG_n_TCM_SHIFT (25u)
|
---|
1850 | #define DMAC6_CHCFG_n_SBE_SHIFT (27u)
|
---|
1851 | #define DMAC6_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1852 | #define DMAC6_CHCFG_n_RSW_SHIFT (29u)
|
---|
1853 | #define DMAC6_CHCFG_n_REN_SHIFT (30u)
|
---|
1854 | #define DMAC6_CHCFG_n_DMS_SHIFT (31u)
|
---|
1855 |
|
---|
1856 | #define DMAC6_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1857 |
|
---|
1858 | #define DMAC6_CHEXT_n_SCA_SHIFT (4u)
|
---|
1859 | #define DMAC6_CHEXT_n_DCA_SHIFT (12u)
|
---|
1860 |
|
---|
1861 | #define DMAC6_NXLA_n_NXLA_SHIFT (0u)
|
---|
1862 |
|
---|
1863 | #define DMAC6_CRLA_n_CRLA_SHIFT (0u)
|
---|
1864 |
|
---|
1865 | /* ---- DMAC7 ---- */
|
---|
1866 | #define DMAC7_N0SA_n_SA_SHIFT (0u)
|
---|
1867 |
|
---|
1868 | #define DMAC7_N0DA_n_DA_SHIFT (0u)
|
---|
1869 |
|
---|
1870 | #define DMAC7_N0TB_n_TB_SHIFT (0u)
|
---|
1871 |
|
---|
1872 | #define DMAC7_N1SA_n_SA_SHIFT (0u)
|
---|
1873 |
|
---|
1874 | #define DMAC7_N1DA_n_DA_SHIFT (0u)
|
---|
1875 |
|
---|
1876 | #define DMAC7_N1TB_n_TB_SHIFT (0u)
|
---|
1877 |
|
---|
1878 | #define DMAC7_CRSA_n_CRSA_SHIFT (0u)
|
---|
1879 |
|
---|
1880 | #define DMAC7_CRDA_n_CRDA_SHIFT (0u)
|
---|
1881 |
|
---|
1882 | #define DMAC7_CRTB_n_CRTB_SHIFT (0u)
|
---|
1883 |
|
---|
1884 | #define DMAC7_CHSTAT_n_EN_SHIFT (0u)
|
---|
1885 | #define DMAC7_CHSTAT_n_RQST_SHIFT (1u)
|
---|
1886 | #define DMAC7_CHSTAT_n_TACT_SHIFT (2u)
|
---|
1887 | #define DMAC7_CHSTAT_n_SUS_SHIFT (3u)
|
---|
1888 | #define DMAC7_CHSTAT_n_ER_SHIFT (4u)
|
---|
1889 | #define DMAC7_CHSTAT_n_END_SHIFT (5u)
|
---|
1890 | #define DMAC7_CHSTAT_n_TC_SHIFT (6u)
|
---|
1891 | #define DMAC7_CHSTAT_n_SR_SHIFT (7u)
|
---|
1892 | #define DMAC7_CHSTAT_n_DL_SHIFT (8u)
|
---|
1893 | #define DMAC7_CHSTAT_n_DW_SHIFT (9u)
|
---|
1894 | #define DMAC7_CHSTAT_n_DER_SHIFT (10u)
|
---|
1895 | #define DMAC7_CHSTAT_n_MODE_SHIFT (11u)
|
---|
1896 | #define DMAC7_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
1897 |
|
---|
1898 | #define DMAC7_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
1899 | #define DMAC7_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
1900 | #define DMAC7_CHCTRL_n_STG_SHIFT (2u)
|
---|
1901 | #define DMAC7_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
1902 | #define DMAC7_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
1903 | #define DMAC7_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
1904 | #define DMAC7_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
1905 | #define DMAC7_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
1906 | #define DMAC7_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
1907 | #define DMAC7_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
1908 | #define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
1909 |
|
---|
1910 | #define DMAC7_CHCFG_n_SEL_SHIFT (0u)
|
---|
1911 | #define DMAC7_CHCFG_n_REQD_SHIFT (3u)
|
---|
1912 | #define DMAC7_CHCFG_n_LOEN_SHIFT (4u)
|
---|
1913 | #define DMAC7_CHCFG_n_HIEN_SHIFT (5u)
|
---|
1914 | #define DMAC7_CHCFG_n_LVL_SHIFT (6u)
|
---|
1915 | #define DMAC7_CHCFG_n_AM_SHIFT (8u)
|
---|
1916 | #define DMAC7_CHCFG_n_SDS_SHIFT (12u)
|
---|
1917 | #define DMAC7_CHCFG_n_DDS_SHIFT (16u)
|
---|
1918 | #define DMAC7_CHCFG_n_SAD_SHIFT (20u)
|
---|
1919 | #define DMAC7_CHCFG_n_DAD_SHIFT (21u)
|
---|
1920 | #define DMAC7_CHCFG_n_TM_SHIFT (22u)
|
---|
1921 | #define DMAC7_CHCFG_n_DEM_SHIFT (24u)
|
---|
1922 | #define DMAC7_CHCFG_n_TCM_SHIFT (25u)
|
---|
1923 | #define DMAC7_CHCFG_n_SBE_SHIFT (27u)
|
---|
1924 | #define DMAC7_CHCFG_n_RSEL_SHIFT (28u)
|
---|
1925 | #define DMAC7_CHCFG_n_RSW_SHIFT (29u)
|
---|
1926 | #define DMAC7_CHCFG_n_REN_SHIFT (30u)
|
---|
1927 | #define DMAC7_CHCFG_n_DMS_SHIFT (31u)
|
---|
1928 |
|
---|
1929 | #define DMAC7_CHITVL_n_ITVL_SHIFT (0u)
|
---|
1930 |
|
---|
1931 | #define DMAC7_CHEXT_n_SCA_SHIFT (4u)
|
---|
1932 | #define DMAC7_CHEXT_n_DCA_SHIFT (12u)
|
---|
1933 |
|
---|
1934 | #define DMAC7_NXLA_n_NXLA_SHIFT (0u)
|
---|
1935 |
|
---|
1936 | #define DMAC7_CRLA_n_CRLA_SHIFT (0u)
|
---|
1937 |
|
---|
1938 | /* ---- DMAC0-7 ---- */
|
---|
1939 | #define DMAC07_DCTRL_0_7_PR_SHIFT (0u)
|
---|
1940 | #define DMAC07_DCTRL_0_7_LVINT_SHIFT (1u)
|
---|
1941 | #define DMAC07_DCTRL_0_7_LDCA_SHIFT (2u)
|
---|
1942 | #define DMAC07_DCTRL_0_7_LWCA_SHIFT (6u)
|
---|
1943 |
|
---|
1944 | #define DMAC07_DSTAT_EN_0_7_EN0_SHIFT (0u)
|
---|
1945 | #define DMAC07_DSTAT_EN_0_7_EN1_SHIFT (1u)
|
---|
1946 | #define DMAC07_DSTAT_EN_0_7_EN2_SHIFT (2u)
|
---|
1947 | #define DMAC07_DSTAT_EN_0_7_EN3_SHIFT (3u)
|
---|
1948 | #define DMAC07_DSTAT_EN_0_7_EN4_SHIFT (4u)
|
---|
1949 | #define DMAC07_DSTAT_EN_0_7_EN5_SHIFT (5u)
|
---|
1950 | #define DMAC07_DSTAT_EN_0_7_EN6_SHIFT (6u)
|
---|
1951 | #define DMAC07_DSTAT_EN_0_7_EN7_SHIFT (7u)
|
---|
1952 |
|
---|
1953 | #define DMAC07_DSTAT_ER_0_7_ER0_SHIFT (0u)
|
---|
1954 | #define DMAC07_DSTAT_ER_0_7_ER1_SHIFT (1u)
|
---|
1955 | #define DMAC07_DSTAT_ER_0_7_ER2_SHIFT (2u)
|
---|
1956 | #define DMAC07_DSTAT_ER_0_7_ER3_SHIFT (3u)
|
---|
1957 | #define DMAC07_DSTAT_ER_0_7_ER4_SHIFT (4u)
|
---|
1958 | #define DMAC07_DSTAT_ER_0_7_ER5_SHIFT (5u)
|
---|
1959 | #define DMAC07_DSTAT_ER_0_7_ER6_SHIFT (6u)
|
---|
1960 | #define DMAC07_DSTAT_ER_0_7_ER7_SHIFT (7u)
|
---|
1961 |
|
---|
1962 | #define DMAC07_DSTAT_END_0_7_END0_SHIFT (0u)
|
---|
1963 | #define DMAC07_DSTAT_END_0_7_END1_SHIFT (1u)
|
---|
1964 | #define DMAC07_DSTAT_END_0_7_END2_SHIFT (2u)
|
---|
1965 | #define DMAC07_DSTAT_END_0_7_END3_SHIFT (3u)
|
---|
1966 | #define DMAC07_DSTAT_END_0_7_END4_SHIFT (4u)
|
---|
1967 | #define DMAC07_DSTAT_END_0_7_END5_SHIFT (5u)
|
---|
1968 | #define DMAC07_DSTAT_END_0_7_END6_SHIFT (6u)
|
---|
1969 | #define DMAC07_DSTAT_END_0_7_END7_SHIFT (7u)
|
---|
1970 |
|
---|
1971 | #define DMAC07_DSTAT_TC_0_7_TC0_SHIFT (0u)
|
---|
1972 | #define DMAC07_DSTAT_TC_0_7_TC1_SHIFT (1u)
|
---|
1973 | #define DMAC07_DSTAT_TC_0_7_TC2_SHIFT (2u)
|
---|
1974 | #define DMAC07_DSTAT_TC_0_7_TC3_SHIFT (3u)
|
---|
1975 | #define DMAC07_DSTAT_TC_0_7_TC4_SHIFT (4u)
|
---|
1976 | #define DMAC07_DSTAT_TC_0_7_TC5_SHIFT (5u)
|
---|
1977 | #define DMAC07_DSTAT_TC_0_7_TC6_SHIFT (6u)
|
---|
1978 | #define DMAC07_DSTAT_TC_0_7_TC7_SHIFT (7u)
|
---|
1979 |
|
---|
1980 | #define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT (0u)
|
---|
1981 | #define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT (1u)
|
---|
1982 | #define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT (2u)
|
---|
1983 | #define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT (3u)
|
---|
1984 | #define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT (4u)
|
---|
1985 | #define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT (5u)
|
---|
1986 | #define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT (6u)
|
---|
1987 | #define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT (7u)
|
---|
1988 |
|
---|
1989 | /* ---- DMAC8 ---- */
|
---|
1990 | #define DMAC8_N0SA_n_SA_SHIFT (0u)
|
---|
1991 |
|
---|
1992 | #define DMAC8_N0DA_n_DA_SHIFT (0u)
|
---|
1993 |
|
---|
1994 | #define DMAC8_N0TB_n_TB_SHIFT (0u)
|
---|
1995 |
|
---|
1996 | #define DMAC8_N1SA_n_SA_SHIFT (0u)
|
---|
1997 |
|
---|
1998 | #define DMAC8_N1DA_n_DA_SHIFT (0u)
|
---|
1999 |
|
---|
2000 | #define DMAC8_N1TB_n_TB_SHIFT (0u)
|
---|
2001 |
|
---|
2002 | #define DMAC8_CRSA_n_CRSA_SHIFT (0u)
|
---|
2003 |
|
---|
2004 | #define DMAC8_CRDA_n_CRDA_SHIFT (0u)
|
---|
2005 |
|
---|
2006 | #define DMAC8_CRTB_n_CRTB_SHIFT (0u)
|
---|
2007 |
|
---|
2008 | #define DMAC8_CHSTAT_n_EN_SHIFT (0u)
|
---|
2009 | #define DMAC8_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2010 | #define DMAC8_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2011 | #define DMAC8_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2012 | #define DMAC8_CHSTAT_n_ER_SHIFT (4u)
|
---|
2013 | #define DMAC8_CHSTAT_n_END_SHIFT (5u)
|
---|
2014 | #define DMAC8_CHSTAT_n_TC_SHIFT (6u)
|
---|
2015 | #define DMAC8_CHSTAT_n_SR_SHIFT (7u)
|
---|
2016 | #define DMAC8_CHSTAT_n_DL_SHIFT (8u)
|
---|
2017 | #define DMAC8_CHSTAT_n_DW_SHIFT (9u)
|
---|
2018 | #define DMAC8_CHSTAT_n_DER_SHIFT (10u)
|
---|
2019 | #define DMAC8_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2020 | #define DMAC8_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2021 |
|
---|
2022 | #define DMAC8_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2023 | #define DMAC8_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2024 | #define DMAC8_CHCTRL_n_STG_SHIFT (2u)
|
---|
2025 | #define DMAC8_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2026 | #define DMAC8_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2027 | #define DMAC8_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2028 | #define DMAC8_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2029 | #define DMAC8_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2030 | #define DMAC8_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2031 | #define DMAC8_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2032 | #define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2033 |
|
---|
2034 | #define DMAC8_CHCFG_n_SEL_SHIFT (0u)
|
---|
2035 | #define DMAC8_CHCFG_n_REQD_SHIFT (3u)
|
---|
2036 | #define DMAC8_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2037 | #define DMAC8_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2038 | #define DMAC8_CHCFG_n_LVL_SHIFT (6u)
|
---|
2039 | #define DMAC8_CHCFG_n_AM_SHIFT (8u)
|
---|
2040 | #define DMAC8_CHCFG_n_SDS_SHIFT (12u)
|
---|
2041 | #define DMAC8_CHCFG_n_DDS_SHIFT (16u)
|
---|
2042 | #define DMAC8_CHCFG_n_SAD_SHIFT (20u)
|
---|
2043 | #define DMAC8_CHCFG_n_DAD_SHIFT (21u)
|
---|
2044 | #define DMAC8_CHCFG_n_TM_SHIFT (22u)
|
---|
2045 | #define DMAC8_CHCFG_n_DEM_SHIFT (24u)
|
---|
2046 | #define DMAC8_CHCFG_n_TCM_SHIFT (25u)
|
---|
2047 | #define DMAC8_CHCFG_n_SBE_SHIFT (27u)
|
---|
2048 | #define DMAC8_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2049 | #define DMAC8_CHCFG_n_RSW_SHIFT (29u)
|
---|
2050 | #define DMAC8_CHCFG_n_REN_SHIFT (30u)
|
---|
2051 | #define DMAC8_CHCFG_n_DMS_SHIFT (31u)
|
---|
2052 |
|
---|
2053 | #define DMAC8_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2054 |
|
---|
2055 | #define DMAC8_CHEXT_n_SCA_SHIFT (4u)
|
---|
2056 | #define DMAC8_CHEXT_n_DCA_SHIFT (12u)
|
---|
2057 |
|
---|
2058 | #define DMAC8_NXLA_n_NXLA_SHIFT (0u)
|
---|
2059 |
|
---|
2060 | #define DMAC8_CRLA_n_CRLA_SHIFT (0u)
|
---|
2061 |
|
---|
2062 | /* ---- DMAC9 ---- */
|
---|
2063 | #define DMAC9_N0SA_n_SA_SHIFT (0u)
|
---|
2064 |
|
---|
2065 | #define DMAC9_N0DA_n_DA_SHIFT (0u)
|
---|
2066 |
|
---|
2067 | #define DMAC9_N0TB_n_TB_SHIFT (0u)
|
---|
2068 |
|
---|
2069 | #define DMAC9_N1SA_n_SA_SHIFT (0u)
|
---|
2070 |
|
---|
2071 | #define DMAC9_N1DA_n_DA_SHIFT (0u)
|
---|
2072 |
|
---|
2073 | #define DMAC9_N1TB_n_TB_SHIFT (0u)
|
---|
2074 |
|
---|
2075 | #define DMAC9_CRSA_n_CRSA_SHIFT (0u)
|
---|
2076 |
|
---|
2077 | #define DMAC9_CRDA_n_CRDA_SHIFT (0u)
|
---|
2078 |
|
---|
2079 | #define DMAC9_CRTB_n_CRTB_SHIFT (0u)
|
---|
2080 |
|
---|
2081 | #define DMAC9_CHSTAT_n_EN_SHIFT (0u)
|
---|
2082 | #define DMAC9_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2083 | #define DMAC9_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2084 | #define DMAC9_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2085 | #define DMAC9_CHSTAT_n_ER_SHIFT (4u)
|
---|
2086 | #define DMAC9_CHSTAT_n_END_SHIFT (5u)
|
---|
2087 | #define DMAC9_CHSTAT_n_TC_SHIFT (6u)
|
---|
2088 | #define DMAC9_CHSTAT_n_SR_SHIFT (7u)
|
---|
2089 | #define DMAC9_CHSTAT_n_DL_SHIFT (8u)
|
---|
2090 | #define DMAC9_CHSTAT_n_DW_SHIFT (9u)
|
---|
2091 | #define DMAC9_CHSTAT_n_DER_SHIFT (10u)
|
---|
2092 | #define DMAC9_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2093 | #define DMAC9_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2094 |
|
---|
2095 | #define DMAC9_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2096 | #define DMAC9_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2097 | #define DMAC9_CHCTRL_n_STG_SHIFT (2u)
|
---|
2098 | #define DMAC9_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2099 | #define DMAC9_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2100 | #define DMAC9_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2101 | #define DMAC9_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2102 | #define DMAC9_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2103 | #define DMAC9_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2104 | #define DMAC9_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2105 | #define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2106 |
|
---|
2107 | #define DMAC9_CHCFG_n_SEL_SHIFT (0u)
|
---|
2108 | #define DMAC9_CHCFG_n_REQD_SHIFT (3u)
|
---|
2109 | #define DMAC9_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2110 | #define DMAC9_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2111 | #define DMAC9_CHCFG_n_LVL_SHIFT (6u)
|
---|
2112 | #define DMAC9_CHCFG_n_AM_SHIFT (8u)
|
---|
2113 | #define DMAC9_CHCFG_n_SDS_SHIFT (12u)
|
---|
2114 | #define DMAC9_CHCFG_n_DDS_SHIFT (16u)
|
---|
2115 | #define DMAC9_CHCFG_n_SAD_SHIFT (20u)
|
---|
2116 | #define DMAC9_CHCFG_n_DAD_SHIFT (21u)
|
---|
2117 | #define DMAC9_CHCFG_n_TM_SHIFT (22u)
|
---|
2118 | #define DMAC9_CHCFG_n_DEM_SHIFT (24u)
|
---|
2119 | #define DMAC9_CHCFG_n_TCM_SHIFT (25u)
|
---|
2120 | #define DMAC9_CHCFG_n_SBE_SHIFT (27u)
|
---|
2121 | #define DMAC9_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2122 | #define DMAC9_CHCFG_n_RSW_SHIFT (29u)
|
---|
2123 | #define DMAC9_CHCFG_n_REN_SHIFT (30u)
|
---|
2124 | #define DMAC9_CHCFG_n_DMS_SHIFT (31u)
|
---|
2125 |
|
---|
2126 | #define DMAC9_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2127 |
|
---|
2128 | #define DMAC9_CHEXT_n_SCA_SHIFT (4u)
|
---|
2129 | #define DMAC9_CHEXT_n_DCA_SHIFT (12u)
|
---|
2130 |
|
---|
2131 | #define DMAC9_NXLA_n_NXLA_SHIFT (0u)
|
---|
2132 |
|
---|
2133 | #define DMAC9_CRLA_n_CRLA_SHIFT (0u)
|
---|
2134 |
|
---|
2135 | /* ---- DMAC10 ---- */
|
---|
2136 | #define DMAC10_N0SA_n_SA_SHIFT (0u)
|
---|
2137 |
|
---|
2138 | #define DMAC10_N0DA_n_DA_SHIFT (0u)
|
---|
2139 |
|
---|
2140 | #define DMAC10_N0TB_n_TB_SHIFT (0u)
|
---|
2141 |
|
---|
2142 | #define DMAC10_N1SA_n_SA_SHIFT (0u)
|
---|
2143 |
|
---|
2144 | #define DMAC10_N1DA_n_DA_SHIFT (0u)
|
---|
2145 |
|
---|
2146 | #define DMAC10_N1TB_n_TB_SHIFT (0u)
|
---|
2147 |
|
---|
2148 | #define DMAC10_CRSA_n_CRSA_SHIFT (0u)
|
---|
2149 |
|
---|
2150 | #define DMAC10_CRDA_n_CRDA_SHIFT (0u)
|
---|
2151 |
|
---|
2152 | #define DMAC10_CRTB_n_CRTB_SHIFT (0u)
|
---|
2153 |
|
---|
2154 | #define DMAC10_CHSTAT_n_EN_SHIFT (0u)
|
---|
2155 | #define DMAC10_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2156 | #define DMAC10_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2157 | #define DMAC10_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2158 | #define DMAC10_CHSTAT_n_ER_SHIFT (4u)
|
---|
2159 | #define DMAC10_CHSTAT_n_END_SHIFT (5u)
|
---|
2160 | #define DMAC10_CHSTAT_n_TC_SHIFT (6u)
|
---|
2161 | #define DMAC10_CHSTAT_n_SR_SHIFT (7u)
|
---|
2162 | #define DMAC10_CHSTAT_n_DL_SHIFT (8u)
|
---|
2163 | #define DMAC10_CHSTAT_n_DW_SHIFT (9u)
|
---|
2164 | #define DMAC10_CHSTAT_n_DER_SHIFT (10u)
|
---|
2165 | #define DMAC10_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2166 | #define DMAC10_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2167 |
|
---|
2168 | #define DMAC10_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2169 | #define DMAC10_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2170 | #define DMAC10_CHCTRL_n_STG_SHIFT (2u)
|
---|
2171 | #define DMAC10_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2172 | #define DMAC10_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2173 | #define DMAC10_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2174 | #define DMAC10_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2175 | #define DMAC10_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2176 | #define DMAC10_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2177 | #define DMAC10_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2178 | #define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2179 |
|
---|
2180 | #define DMAC10_CHCFG_n_SEL_SHIFT (0u)
|
---|
2181 | #define DMAC10_CHCFG_n_REQD_SHIFT (3u)
|
---|
2182 | #define DMAC10_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2183 | #define DMAC10_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2184 | #define DMAC10_CHCFG_n_LVL_SHIFT (6u)
|
---|
2185 | #define DMAC10_CHCFG_n_AM_SHIFT (8u)
|
---|
2186 | #define DMAC10_CHCFG_n_SDS_SHIFT (12u)
|
---|
2187 | #define DMAC10_CHCFG_n_DDS_SHIFT (16u)
|
---|
2188 | #define DMAC10_CHCFG_n_SAD_SHIFT (20u)
|
---|
2189 | #define DMAC10_CHCFG_n_DAD_SHIFT (21u)
|
---|
2190 | #define DMAC10_CHCFG_n_TM_SHIFT (22u)
|
---|
2191 | #define DMAC10_CHCFG_n_DEM_SHIFT (24u)
|
---|
2192 | #define DMAC10_CHCFG_n_TCM_SHIFT (25u)
|
---|
2193 | #define DMAC10_CHCFG_n_SBE_SHIFT (27u)
|
---|
2194 | #define DMAC10_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2195 | #define DMAC10_CHCFG_n_RSW_SHIFT (29u)
|
---|
2196 | #define DMAC10_CHCFG_n_REN_SHIFT (30u)
|
---|
2197 | #define DMAC10_CHCFG_n_DMS_SHIFT (31u)
|
---|
2198 |
|
---|
2199 | #define DMAC10_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2200 |
|
---|
2201 | #define DMAC10_CHEXT_n_SCA_SHIFT (4u)
|
---|
2202 | #define DMAC10_CHEXT_n_DCA_SHIFT (12u)
|
---|
2203 |
|
---|
2204 | #define DMAC10_NXLA_n_NXLA_SHIFT (0u)
|
---|
2205 |
|
---|
2206 | #define DMAC10_CRLA_n_CRLA_SHIFT (0u)
|
---|
2207 |
|
---|
2208 | /* ---- DMAC11 ---- */
|
---|
2209 | #define DMAC11_N0SA_n_SA_SHIFT (0u)
|
---|
2210 |
|
---|
2211 | #define DMAC11_N0DA_n_DA_SHIFT (0u)
|
---|
2212 |
|
---|
2213 | #define DMAC11_N0TB_n_TB_SHIFT (0u)
|
---|
2214 |
|
---|
2215 | #define DMAC11_N1SA_n_SA_SHIFT (0u)
|
---|
2216 |
|
---|
2217 | #define DMAC11_N1DA_n_DA_SHIFT (0u)
|
---|
2218 |
|
---|
2219 | #define DMAC11_N1TB_n_TB_SHIFT (0u)
|
---|
2220 |
|
---|
2221 | #define DMAC11_CRSA_n_CRSA_SHIFT (0u)
|
---|
2222 |
|
---|
2223 | #define DMAC11_CRDA_n_CRDA_SHIFT (0u)
|
---|
2224 |
|
---|
2225 | #define DMAC11_CRTB_n_CRTB_SHIFT (0u)
|
---|
2226 |
|
---|
2227 | #define DMAC11_CHSTAT_n_EN_SHIFT (0u)
|
---|
2228 | #define DMAC11_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2229 | #define DMAC11_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2230 | #define DMAC11_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2231 | #define DMAC11_CHSTAT_n_ER_SHIFT (4u)
|
---|
2232 | #define DMAC11_CHSTAT_n_END_SHIFT (5u)
|
---|
2233 | #define DMAC11_CHSTAT_n_TC_SHIFT (6u)
|
---|
2234 | #define DMAC11_CHSTAT_n_SR_SHIFT (7u)
|
---|
2235 | #define DMAC11_CHSTAT_n_DL_SHIFT (8u)
|
---|
2236 | #define DMAC11_CHSTAT_n_DW_SHIFT (9u)
|
---|
2237 | #define DMAC11_CHSTAT_n_DER_SHIFT (10u)
|
---|
2238 | #define DMAC11_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2239 | #define DMAC11_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2240 |
|
---|
2241 | #define DMAC11_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2242 | #define DMAC11_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2243 | #define DMAC11_CHCTRL_n_STG_SHIFT (2u)
|
---|
2244 | #define DMAC11_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2245 | #define DMAC11_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2246 | #define DMAC11_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2247 | #define DMAC11_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2248 | #define DMAC11_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2249 | #define DMAC11_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2250 | #define DMAC11_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2251 | #define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2252 |
|
---|
2253 | #define DMAC11_CHCFG_n_SEL_SHIFT (0u)
|
---|
2254 | #define DMAC11_CHCFG_n_REQD_SHIFT (3u)
|
---|
2255 | #define DMAC11_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2256 | #define DMAC11_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2257 | #define DMAC11_CHCFG_n_LVL_SHIFT (6u)
|
---|
2258 | #define DMAC11_CHCFG_n_AM_SHIFT (8u)
|
---|
2259 | #define DMAC11_CHCFG_n_SDS_SHIFT (12u)
|
---|
2260 | #define DMAC11_CHCFG_n_DDS_SHIFT (16u)
|
---|
2261 | #define DMAC11_CHCFG_n_SAD_SHIFT (20u)
|
---|
2262 | #define DMAC11_CHCFG_n_DAD_SHIFT (21u)
|
---|
2263 | #define DMAC11_CHCFG_n_TM_SHIFT (22u)
|
---|
2264 | #define DMAC11_CHCFG_n_DEM_SHIFT (24u)
|
---|
2265 | #define DMAC11_CHCFG_n_TCM_SHIFT (25u)
|
---|
2266 | #define DMAC11_CHCFG_n_SBE_SHIFT (27u)
|
---|
2267 | #define DMAC11_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2268 | #define DMAC11_CHCFG_n_RSW_SHIFT (29u)
|
---|
2269 | #define DMAC11_CHCFG_n_REN_SHIFT (30u)
|
---|
2270 | #define DMAC11_CHCFG_n_DMS_SHIFT (31u)
|
---|
2271 |
|
---|
2272 | #define DMAC11_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2273 |
|
---|
2274 | #define DMAC11_CHEXT_n_SCA_SHIFT (4u)
|
---|
2275 | #define DMAC11_CHEXT_n_DCA_SHIFT (12u)
|
---|
2276 |
|
---|
2277 | #define DMAC11_NXLA_n_NXLA_SHIFT (0u)
|
---|
2278 |
|
---|
2279 | #define DMAC11_CRLA_n_CRLA_SHIFT (0u)
|
---|
2280 |
|
---|
2281 | /* ---- DMAC12 ---- */
|
---|
2282 | #define DMAC12_N0SA_n_SA_SHIFT (0u)
|
---|
2283 |
|
---|
2284 | #define DMAC12_N0DA_n_DA_SHIFT (0u)
|
---|
2285 |
|
---|
2286 | #define DMAC12_N0TB_n_TB_SHIFT (0u)
|
---|
2287 |
|
---|
2288 | #define DMAC12_N1SA_n_SA_SHIFT (0u)
|
---|
2289 |
|
---|
2290 | #define DMAC12_N1DA_n_DA_SHIFT (0u)
|
---|
2291 |
|
---|
2292 | #define DMAC12_N1TB_n_TB_SHIFT (0u)
|
---|
2293 |
|
---|
2294 | #define DMAC12_CRSA_n_CRSA_SHIFT (0u)
|
---|
2295 |
|
---|
2296 | #define DMAC12_CRDA_n_CRDA_SHIFT (0u)
|
---|
2297 |
|
---|
2298 | #define DMAC12_CRTB_n_CRTB_SHIFT (0u)
|
---|
2299 |
|
---|
2300 | #define DMAC12_CHSTAT_n_EN_SHIFT (0u)
|
---|
2301 | #define DMAC12_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2302 | #define DMAC12_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2303 | #define DMAC12_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2304 | #define DMAC12_CHSTAT_n_ER_SHIFT (4u)
|
---|
2305 | #define DMAC12_CHSTAT_n_END_SHIFT (5u)
|
---|
2306 | #define DMAC12_CHSTAT_n_TC_SHIFT (6u)
|
---|
2307 | #define DMAC12_CHSTAT_n_SR_SHIFT (7u)
|
---|
2308 | #define DMAC12_CHSTAT_n_DL_SHIFT (8u)
|
---|
2309 | #define DMAC12_CHSTAT_n_DW_SHIFT (9u)
|
---|
2310 | #define DMAC12_CHSTAT_n_DER_SHIFT (10u)
|
---|
2311 | #define DMAC12_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2312 | #define DMAC12_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2313 |
|
---|
2314 | #define DMAC12_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2315 | #define DMAC12_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2316 | #define DMAC12_CHCTRL_n_STG_SHIFT (2u)
|
---|
2317 | #define DMAC12_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2318 | #define DMAC12_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2319 | #define DMAC12_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2320 | #define DMAC12_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2321 | #define DMAC12_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2322 | #define DMAC12_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2323 | #define DMAC12_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2324 | #define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2325 |
|
---|
2326 | #define DMAC12_CHCFG_n_SEL_SHIFT (0u)
|
---|
2327 | #define DMAC12_CHCFG_n_REQD_SHIFT (3u)
|
---|
2328 | #define DMAC12_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2329 | #define DMAC12_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2330 | #define DMAC12_CHCFG_n_LVL_SHIFT (6u)
|
---|
2331 | #define DMAC12_CHCFG_n_AM_SHIFT (8u)
|
---|
2332 | #define DMAC12_CHCFG_n_SDS_SHIFT (12u)
|
---|
2333 | #define DMAC12_CHCFG_n_DDS_SHIFT (16u)
|
---|
2334 | #define DMAC12_CHCFG_n_SAD_SHIFT (20u)
|
---|
2335 | #define DMAC12_CHCFG_n_DAD_SHIFT (21u)
|
---|
2336 | #define DMAC12_CHCFG_n_TM_SHIFT (22u)
|
---|
2337 | #define DMAC12_CHCFG_n_DEM_SHIFT (24u)
|
---|
2338 | #define DMAC12_CHCFG_n_TCM_SHIFT (25u)
|
---|
2339 | #define DMAC12_CHCFG_n_SBE_SHIFT (27u)
|
---|
2340 | #define DMAC12_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2341 | #define DMAC12_CHCFG_n_RSW_SHIFT (29u)
|
---|
2342 | #define DMAC12_CHCFG_n_REN_SHIFT (30u)
|
---|
2343 | #define DMAC12_CHCFG_n_DMS_SHIFT (31u)
|
---|
2344 |
|
---|
2345 | #define DMAC12_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2346 |
|
---|
2347 | #define DMAC12_CHEXT_n_SCA_SHIFT (4u)
|
---|
2348 | #define DMAC12_CHEXT_n_DCA_SHIFT (12u)
|
---|
2349 |
|
---|
2350 | #define DMAC12_NXLA_n_NXLA_SHIFT (0u)
|
---|
2351 |
|
---|
2352 | #define DMAC12_CRLA_n_CRLA_SHIFT (0u)
|
---|
2353 |
|
---|
2354 | /* ---- DMAC13 ---- */
|
---|
2355 | #define DMAC13_N0SA_n_SA_SHIFT (0u)
|
---|
2356 |
|
---|
2357 | #define DMAC13_N0DA_n_DA_SHIFT (0u)
|
---|
2358 |
|
---|
2359 | #define DMAC13_N0TB_n_TB_SHIFT (0u)
|
---|
2360 |
|
---|
2361 | #define DMAC13_N1SA_n_SA_SHIFT (0u)
|
---|
2362 |
|
---|
2363 | #define DMAC13_N1DA_n_DA_SHIFT (0u)
|
---|
2364 |
|
---|
2365 | #define DMAC13_N1TB_n_TB_SHIFT (0u)
|
---|
2366 |
|
---|
2367 | #define DMAC13_CRSA_n_CRSA_SHIFT (0u)
|
---|
2368 |
|
---|
2369 | #define DMAC13_CRDA_n_CRDA_SHIFT (0u)
|
---|
2370 |
|
---|
2371 | #define DMAC13_CRTB_n_CRTB_SHIFT (0u)
|
---|
2372 |
|
---|
2373 | #define DMAC13_CHSTAT_n_EN_SHIFT (0u)
|
---|
2374 | #define DMAC13_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2375 | #define DMAC13_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2376 | #define DMAC13_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2377 | #define DMAC13_CHSTAT_n_ER_SHIFT (4u)
|
---|
2378 | #define DMAC13_CHSTAT_n_END_SHIFT (5u)
|
---|
2379 | #define DMAC13_CHSTAT_n_TC_SHIFT (6u)
|
---|
2380 | #define DMAC13_CHSTAT_n_SR_SHIFT (7u)
|
---|
2381 | #define DMAC13_CHSTAT_n_DL_SHIFT (8u)
|
---|
2382 | #define DMAC13_CHSTAT_n_DW_SHIFT (9u)
|
---|
2383 | #define DMAC13_CHSTAT_n_DER_SHIFT (10u)
|
---|
2384 | #define DMAC13_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2385 | #define DMAC13_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2386 |
|
---|
2387 | #define DMAC13_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2388 | #define DMAC13_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2389 | #define DMAC13_CHCTRL_n_STG_SHIFT (2u)
|
---|
2390 | #define DMAC13_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2391 | #define DMAC13_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2392 | #define DMAC13_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2393 | #define DMAC13_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2394 | #define DMAC13_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2395 | #define DMAC13_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2396 | #define DMAC13_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2397 | #define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2398 |
|
---|
2399 | #define DMAC13_CHCFG_n_SEL_SHIFT (0u)
|
---|
2400 | #define DMAC13_CHCFG_n_REQD_SHIFT (3u)
|
---|
2401 | #define DMAC13_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2402 | #define DMAC13_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2403 | #define DMAC13_CHCFG_n_LVL_SHIFT (6u)
|
---|
2404 | #define DMAC13_CHCFG_n_AM_SHIFT (8u)
|
---|
2405 | #define DMAC13_CHCFG_n_SDS_SHIFT (12u)
|
---|
2406 | #define DMAC13_CHCFG_n_DDS_SHIFT (16u)
|
---|
2407 | #define DMAC13_CHCFG_n_SAD_SHIFT (20u)
|
---|
2408 | #define DMAC13_CHCFG_n_DAD_SHIFT (21u)
|
---|
2409 | #define DMAC13_CHCFG_n_TM_SHIFT (22u)
|
---|
2410 | #define DMAC13_CHCFG_n_DEM_SHIFT (24u)
|
---|
2411 | #define DMAC13_CHCFG_n_TCM_SHIFT (25u)
|
---|
2412 | #define DMAC13_CHCFG_n_SBE_SHIFT (27u)
|
---|
2413 | #define DMAC13_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2414 | #define DMAC13_CHCFG_n_RSW_SHIFT (29u)
|
---|
2415 | #define DMAC13_CHCFG_n_REN_SHIFT (30u)
|
---|
2416 | #define DMAC13_CHCFG_n_DMS_SHIFT (31u)
|
---|
2417 |
|
---|
2418 | #define DMAC13_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2419 |
|
---|
2420 | #define DMAC13_CHEXT_n_SCA_SHIFT (4u)
|
---|
2421 | #define DMAC13_CHEXT_n_DCA_SHIFT (12u)
|
---|
2422 |
|
---|
2423 | #define DMAC13_NXLA_n_NXLA_SHIFT (0u)
|
---|
2424 |
|
---|
2425 | #define DMAC13_CRLA_n_CRLA_SHIFT (0u)
|
---|
2426 |
|
---|
2427 | /* ---- DMAC14 ---- */
|
---|
2428 | #define DMAC14_N0SA_n_SA_SHIFT (0u)
|
---|
2429 |
|
---|
2430 | #define DMAC14_N0DA_n_DA_SHIFT (0u)
|
---|
2431 |
|
---|
2432 | #define DMAC14_N0TB_n_TB_SHIFT (0u)
|
---|
2433 |
|
---|
2434 | #define DMAC14_N1SA_n_SA_SHIFT (0u)
|
---|
2435 |
|
---|
2436 | #define DMAC14_N1DA_n_DA_SHIFT (0u)
|
---|
2437 |
|
---|
2438 | #define DMAC14_N1TB_n_TB_SHIFT (0u)
|
---|
2439 |
|
---|
2440 | #define DMAC14_CRSA_n_CRSA_SHIFT (0u)
|
---|
2441 |
|
---|
2442 | #define DMAC14_CRDA_n_CRDA_SHIFT (0u)
|
---|
2443 |
|
---|
2444 | #define DMAC14_CRTB_n_CRTB_SHIFT (0u)
|
---|
2445 |
|
---|
2446 | #define DMAC14_CHSTAT_n_EN_SHIFT (0u)
|
---|
2447 | #define DMAC14_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2448 | #define DMAC14_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2449 | #define DMAC14_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2450 | #define DMAC14_CHSTAT_n_ER_SHIFT (4u)
|
---|
2451 | #define DMAC14_CHSTAT_n_END_SHIFT (5u)
|
---|
2452 | #define DMAC14_CHSTAT_n_TC_SHIFT (6u)
|
---|
2453 | #define DMAC14_CHSTAT_n_SR_SHIFT (7u)
|
---|
2454 | #define DMAC14_CHSTAT_n_DL_SHIFT (8u)
|
---|
2455 | #define DMAC14_CHSTAT_n_DW_SHIFT (9u)
|
---|
2456 | #define DMAC14_CHSTAT_n_DER_SHIFT (10u)
|
---|
2457 | #define DMAC14_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2458 | #define DMAC14_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2459 |
|
---|
2460 | #define DMAC14_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2461 | #define DMAC14_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2462 | #define DMAC14_CHCTRL_n_STG_SHIFT (2u)
|
---|
2463 | #define DMAC14_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2464 | #define DMAC14_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2465 | #define DMAC14_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2466 | #define DMAC14_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2467 | #define DMAC14_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2468 | #define DMAC14_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2469 | #define DMAC14_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2470 | #define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2471 |
|
---|
2472 | #define DMAC14_CHCFG_n_SEL_SHIFT (0u)
|
---|
2473 | #define DMAC14_CHCFG_n_REQD_SHIFT (3u)
|
---|
2474 | #define DMAC14_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2475 | #define DMAC14_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2476 | #define DMAC14_CHCFG_n_LVL_SHIFT (6u)
|
---|
2477 | #define DMAC14_CHCFG_n_AM_SHIFT (8u)
|
---|
2478 | #define DMAC14_CHCFG_n_SDS_SHIFT (12u)
|
---|
2479 | #define DMAC14_CHCFG_n_DDS_SHIFT (16u)
|
---|
2480 | #define DMAC14_CHCFG_n_SAD_SHIFT (20u)
|
---|
2481 | #define DMAC14_CHCFG_n_DAD_SHIFT (21u)
|
---|
2482 | #define DMAC14_CHCFG_n_TM_SHIFT (22u)
|
---|
2483 | #define DMAC14_CHCFG_n_DEM_SHIFT (24u)
|
---|
2484 | #define DMAC14_CHCFG_n_TCM_SHIFT (25u)
|
---|
2485 | #define DMAC14_CHCFG_n_SBE_SHIFT (27u)
|
---|
2486 | #define DMAC14_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2487 | #define DMAC14_CHCFG_n_RSW_SHIFT (29u)
|
---|
2488 | #define DMAC14_CHCFG_n_REN_SHIFT (30u)
|
---|
2489 | #define DMAC14_CHCFG_n_DMS_SHIFT (31u)
|
---|
2490 |
|
---|
2491 | #define DMAC14_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2492 |
|
---|
2493 | #define DMAC14_CHEXT_n_SCA_SHIFT (4u)
|
---|
2494 | #define DMAC14_CHEXT_n_DCA_SHIFT (12u)
|
---|
2495 |
|
---|
2496 | #define DMAC14_NXLA_n_NXLA_SHIFT (0u)
|
---|
2497 |
|
---|
2498 | #define DMAC14_CRLA_n_CRLA_SHIFT (0u)
|
---|
2499 |
|
---|
2500 | /* ---- DMAC15 ---- */
|
---|
2501 | #define DMAC15_N0SA_n_SA_SHIFT (0u)
|
---|
2502 |
|
---|
2503 | #define DMAC15_N0DA_n_DA_SHIFT (0u)
|
---|
2504 |
|
---|
2505 | #define DMAC15_N0TB_n_TB_SHIFT (0u)
|
---|
2506 |
|
---|
2507 | #define DMAC15_N1SA_n_SA_SHIFT (0u)
|
---|
2508 |
|
---|
2509 | #define DMAC15_N1DA_n_DA_SHIFT (0u)
|
---|
2510 |
|
---|
2511 | #define DMAC15_N1TB_n_TB_SHIFT (0u)
|
---|
2512 |
|
---|
2513 | #define DMAC15_CRSA_n_CRSA_SHIFT (0u)
|
---|
2514 |
|
---|
2515 | #define DMAC15_CRDA_n_CRDA_SHIFT (0u)
|
---|
2516 |
|
---|
2517 | #define DMAC15_CRTB_n_CRTB_SHIFT (0u)
|
---|
2518 |
|
---|
2519 | #define DMAC15_CHSTAT_n_EN_SHIFT (0u)
|
---|
2520 | #define DMAC15_CHSTAT_n_RQST_SHIFT (1u)
|
---|
2521 | #define DMAC15_CHSTAT_n_TACT_SHIFT (2u)
|
---|
2522 | #define DMAC15_CHSTAT_n_SUS_SHIFT (3u)
|
---|
2523 | #define DMAC15_CHSTAT_n_ER_SHIFT (4u)
|
---|
2524 | #define DMAC15_CHSTAT_n_END_SHIFT (5u)
|
---|
2525 | #define DMAC15_CHSTAT_n_TC_SHIFT (6u)
|
---|
2526 | #define DMAC15_CHSTAT_n_SR_SHIFT (7u)
|
---|
2527 | #define DMAC15_CHSTAT_n_DL_SHIFT (8u)
|
---|
2528 | #define DMAC15_CHSTAT_n_DW_SHIFT (9u)
|
---|
2529 | #define DMAC15_CHSTAT_n_DER_SHIFT (10u)
|
---|
2530 | #define DMAC15_CHSTAT_n_MODE_SHIFT (11u)
|
---|
2531 | #define DMAC15_CHSTAT_n_INTMSK_SHIFT (16u)
|
---|
2532 |
|
---|
2533 | #define DMAC15_CHCTRL_n_SETEN_SHIFT (0u)
|
---|
2534 | #define DMAC15_CHCTRL_n_CLREN_SHIFT (1u)
|
---|
2535 | #define DMAC15_CHCTRL_n_STG_SHIFT (2u)
|
---|
2536 | #define DMAC15_CHCTRL_n_SWRST_SHIFT (3u)
|
---|
2537 | #define DMAC15_CHCTRL_n_CLRRQ_SHIFT (4u)
|
---|
2538 | #define DMAC15_CHCTRL_n_CLREND_SHIFT (5u)
|
---|
2539 | #define DMAC15_CHCTRL_n_CLRTC_SHIFT (6u)
|
---|
2540 | #define DMAC15_CHCTRL_n_SETSUS_SHIFT (8u)
|
---|
2541 | #define DMAC15_CHCTRL_n_CLRSUS_SHIFT (9u)
|
---|
2542 | #define DMAC15_CHCTRL_n_SETINTMSK_SHIFT (16u)
|
---|
2543 | #define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT (17u)
|
---|
2544 |
|
---|
2545 | #define DMAC15_CHCFG_n_SEL_SHIFT (0u)
|
---|
2546 | #define DMAC15_CHCFG_n_REQD_SHIFT (3u)
|
---|
2547 | #define DMAC15_CHCFG_n_LOEN_SHIFT (4u)
|
---|
2548 | #define DMAC15_CHCFG_n_HIEN_SHIFT (5u)
|
---|
2549 | #define DMAC15_CHCFG_n_LVL_SHIFT (6u)
|
---|
2550 | #define DMAC15_CHCFG_n_AM_SHIFT (8u)
|
---|
2551 | #define DMAC15_CHCFG_n_SDS_SHIFT (12u)
|
---|
2552 | #define DMAC15_CHCFG_n_DDS_SHIFT (16u)
|
---|
2553 | #define DMAC15_CHCFG_n_SAD_SHIFT (20u)
|
---|
2554 | #define DMAC15_CHCFG_n_DAD_SHIFT (21u)
|
---|
2555 | #define DMAC15_CHCFG_n_TM_SHIFT (22u)
|
---|
2556 | #define DMAC15_CHCFG_n_DEM_SHIFT (24u)
|
---|
2557 | #define DMAC15_CHCFG_n_TCM_SHIFT (25u)
|
---|
2558 | #define DMAC15_CHCFG_n_SBE_SHIFT (27u)
|
---|
2559 | #define DMAC15_CHCFG_n_RSEL_SHIFT (28u)
|
---|
2560 | #define DMAC15_CHCFG_n_RSW_SHIFT (29u)
|
---|
2561 | #define DMAC15_CHCFG_n_REN_SHIFT (30u)
|
---|
2562 | #define DMAC15_CHCFG_n_DMS_SHIFT (31u)
|
---|
2563 |
|
---|
2564 | #define DMAC15_CHITVL_n_ITVL_SHIFT (0u)
|
---|
2565 |
|
---|
2566 | #define DMAC15_CHEXT_n_SCA_SHIFT (4u)
|
---|
2567 | #define DMAC15_CHEXT_n_DCA_SHIFT (12u)
|
---|
2568 |
|
---|
2569 | #define DMAC15_NXLA_n_NXLA_SHIFT (0u)
|
---|
2570 |
|
---|
2571 | #define DMAC15_CRLA_n_CRLA_SHIFT (0u)
|
---|
2572 |
|
---|
2573 | /* ---- DMAC8-15 ---- */
|
---|
2574 | #define DMAC815_DCTRL_8_15_PR_SHIFT (0u)
|
---|
2575 | #define DMAC815_DCTRL_8_15_LVINT_SHIFT (1u)
|
---|
2576 | #define DMAC815_DCTRL_8_15_LDCA_SHIFT (2u)
|
---|
2577 | #define DMAC815_DCTRL_8_15_LWCA_SHIFT (10u)
|
---|
2578 |
|
---|
2579 | #define DMAC815_DSTAT_EN_8_15_EN8_SHIFT (0u)
|
---|
2580 | #define DMAC815_DSTAT_EN_8_15_EN9_SHIFT (1u)
|
---|
2581 | #define DMAC815_DSTAT_EN_8_15_EN10_SHIFT (2u)
|
---|
2582 | #define DMAC815_DSTAT_EN_8_15_EN11_SHIFT (3u)
|
---|
2583 | #define DMAC815_DSTAT_EN_8_15_EN12_SHIFT (4u)
|
---|
2584 | #define DMAC815_DSTAT_EN_8_15_EN13_SHIFT (5u)
|
---|
2585 | #define DMAC815_DSTAT_EN_8_15_EN14_SHIFT (6u)
|
---|
2586 | #define DMAC815_DSTAT_EN_8_15_EN15_SHIFT (7u)
|
---|
2587 |
|
---|
2588 | #define DMAC815_DSTAT_ER_8_15_ER8_SHIFT (0u)
|
---|
2589 | #define DMAC815_DSTAT_ER_8_15_ER9_SHIFT (1u)
|
---|
2590 | #define DMAC815_DSTAT_ER_8_15_ER10_SHIFT (2u)
|
---|
2591 | #define DMAC815_DSTAT_ER_8_15_ER11_SHIFT (3u)
|
---|
2592 | #define DMAC815_DSTAT_ER_8_15_ER12_SHIFT (4u)
|
---|
2593 | #define DMAC815_DSTAT_ER_8_15_ER13_SHIFT (5u)
|
---|
2594 | #define DMAC815_DSTAT_ER_8_15_ER14_SHIFT (6u)
|
---|
2595 | #define DMAC815_DSTAT_ER_8_15_ER15_SHIFT (7u)
|
---|
2596 |
|
---|
2597 | #define DMAC815_DSTAT_END_8_15_END8_SHIFT (0u)
|
---|
2598 | #define DMAC815_DSTAT_END_8_15_END9_SHIFT (1u)
|
---|
2599 | #define DMAC815_DSTAT_END_8_15_END10_SHIFT (2u)
|
---|
2600 | #define DMAC815_DSTAT_END_8_15_END11_SHIFT (3u)
|
---|
2601 | #define DMAC815_DSTAT_END_8_15_END12_SHIFT (4u)
|
---|
2602 | #define DMAC815_DSTAT_END_8_15_END13_SHIFT (5u)
|
---|
2603 | #define DMAC815_DSTAT_END_8_15_END14_SHIFT (6u)
|
---|
2604 | #define DMAC815_DSTAT_END_8_15_END15_SHIFT (7u)
|
---|
2605 |
|
---|
2606 | #define DMAC815_DSTAT_TC_8_15_TC8_SHIFT (0u)
|
---|
2607 | #define DMAC815_DSTAT_TC_8_15_TC9_SHIFT (1u)
|
---|
2608 | #define DMAC815_DSTAT_TC_8_15_TC10_SHIFT (2u)
|
---|
2609 | #define DMAC815_DSTAT_TC_8_15_TC11_SHIFT (3u)
|
---|
2610 | #define DMAC815_DSTAT_TC_8_15_TC12_SHIFT (4u)
|
---|
2611 | #define DMAC815_DSTAT_TC_8_15_TC13_SHIFT (5u)
|
---|
2612 | #define DMAC815_DSTAT_TC_8_15_TC14_SHIFT (6u)
|
---|
2613 | #define DMAC815_DSTAT_TC_8_15_TC15_SHIFT (7u)
|
---|
2614 |
|
---|
2615 | #define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT (0u)
|
---|
2616 | #define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT (1u)
|
---|
2617 | #define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT (2u)
|
---|
2618 | #define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT (3u)
|
---|
2619 | #define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT (4u)
|
---|
2620 | #define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT (5u)
|
---|
2621 | #define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT (6u)
|
---|
2622 | #define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT (7u)
|
---|
2623 |
|
---|
2624 | /* ---- DMAC0-1 ---- */
|
---|
2625 | #define DMAC01_DMARS_CH0_RID_SHIFT (0u)
|
---|
2626 | #define DMAC01_DMARS_CH0_MID_SHIFT (2u)
|
---|
2627 | #define DMAC01_DMARS_CH1_RID_SHIFT (16u)
|
---|
2628 | #define DMAC01_DMARS_CH1_MID_SHIFT (18u)
|
---|
2629 |
|
---|
2630 | /* ---- DMAC2-3 ---- */
|
---|
2631 | #define DMAC23_DMARS_CH2_RID_SHIFT (0u)
|
---|
2632 | #define DMAC23_DMARS_CH2_MID_SHIFT (2u)
|
---|
2633 | #define DMAC23_DMARS_CH3_RID_SHIFT (16u)
|
---|
2634 | #define DMAC23_DMARS_CH3_MID_SHIFT (18u)
|
---|
2635 |
|
---|
2636 | /* ---- DMAC4-5 ---- */
|
---|
2637 | #define DMAC45_DMARS_CH4_RID_SHIFT (0u)
|
---|
2638 | #define DMAC45_DMARS_CH4_MID_SHIFT (2u)
|
---|
2639 | #define DMAC45_DMARS_CH5_RID_SHIFT (16u)
|
---|
2640 | #define DMAC45_DMARS_CH5_MID_SHIFT (18u)
|
---|
2641 |
|
---|
2642 | /* ---- DMAC6-7 ---- */
|
---|
2643 | #define DMAC67_DMARS_CH6_RID_SHIFT (0u)
|
---|
2644 | #define DMAC67_DMARS_CH6_MID_SHIFT (2u)
|
---|
2645 | #define DMAC67_DMARS_CH7_RID_SHIFT (16u)
|
---|
2646 | #define DMAC67_DMARS_CH7_MID_SHIFT (18u)
|
---|
2647 |
|
---|
2648 | /* ---- DMAC8-9 ---- */
|
---|
2649 | #define DMAC89_DMARS_CH8_RID_SHIFT (0u)
|
---|
2650 | #define DMAC89_DMARS_CH8_MID_SHIFT (2u)
|
---|
2651 | #define DMAC89_DMARS_CH9_RID_SHIFT (16u)
|
---|
2652 | #define DMAC89_DMARS_CH9_MID_SHIFT (18u)
|
---|
2653 |
|
---|
2654 | /* ---- DMAC10-11 ---- */
|
---|
2655 | #define DMAC1011_DMARS_CH10_RID_SHIFT (0u)
|
---|
2656 | #define DMAC1011_DMARS_CH10_MID_SHIFT (2u)
|
---|
2657 | #define DMAC1011_DMARS_CH11_RID_SHIFT (16u)
|
---|
2658 | #define DMAC1011_DMARS_CH11_MID_SHIFT (18u)
|
---|
2659 |
|
---|
2660 | /* ---- DMAC12-13 ---- */
|
---|
2661 | #define DMAC1213_DMARS_CH12_RID_SHIFT (0u)
|
---|
2662 | #define DMAC1213_DMARS_CH12_MID_SHIFT (2u)
|
---|
2663 | #define DMAC1213_DMARS_CH13_RID_SHIFT (16u)
|
---|
2664 | #define DMAC1213_DMARS_CH13_MID_SHIFT (18u)
|
---|
2665 |
|
---|
2666 | /* ---- DMAC14-15 ---- */
|
---|
2667 | #define DMAC1415_DMARS_CH14_RID_SHIFT (0u)
|
---|
2668 | #define DMAC1415_DMARS_CH14_MID_SHIFT (2u)
|
---|
2669 | #define DMAC1415_DMARS_CH15_RID_SHIFT (16u)
|
---|
2670 | #define DMAC1415_DMARS_CH15_MID_SHIFT (18u)
|
---|
2671 |
|
---|
2672 |
|
---|
2673 | #endif /* DMAC_IOBITMASK_H */
|
---|
2674 |
|
---|
2675 | /* End of File */
|
---|