| 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer
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| 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : cpg_iobitmask.h
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| 25 | * $Rev: 1115 $
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| 26 | * $Date:: 2014-07-09 15:35:02 +0900#$
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| 27 | * Description : CPG register define header
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| 28 | *******************************************************************************/
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| 29 | #ifndef CPG_IOBITMASK_H
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| 30 | #define CPG_IOBITMASK_H
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| 31 |
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| 32 |
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| 33 | /* ==== Mask values for IO registers ==== */
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| 34 | #define CPG_FRQCR_IFC (0x0300u)
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| 35 | #define CPG_FRQCR_CKOEN (0x3000u)
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| 36 | #define CPG_FRQCR_CKOEN2 (0x4000u)
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| 37 |
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| 38 | #define CPG_FRQCR2_GFC (0x0003u)
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| 39 |
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| 40 | #define CPG_CPUSTS_ISBUSY (0x10u)
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| 41 |
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| 42 | #define CPG_STBCR1_DEEP (0x40u)
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| 43 | #define CPG_STBCR1_STBY (0x80u)
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| 44 |
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| 45 | #define CPG_STBCR2_MSTP20 (0x01u)
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| 46 | #define CPG_STBCR2_HIZ (0x80u)
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| 47 |
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| 48 | #define CPG_STBREQ1_STBRQ10 (0x01u)
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| 49 | #define CPG_STBREQ1_STBRQ12 (0x04u)
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| 50 | #define CPG_STBREQ1_STBRQ13 (0x08u)
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| 51 | #define CPG_STBREQ1_STBRQ15 (0x20u)
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| 52 |
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| 53 | #define CPG_STBREQ2_STBRQ20 (0x01u)
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| 54 | #define CPG_STBREQ2_STBRQ21 (0x02u)
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| 55 | #define CPG_STBREQ2_STBRQ22 (0x04u)
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| 56 | #define CPG_STBREQ2_STBRQ23 (0x08u)
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| 57 | #define CPG_STBREQ2_STBRQ24 (0x10u)
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| 58 | #define CPG_STBREQ2_STBRQ25 (0x20u)
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| 59 | #define CPG_STBREQ2_STBRQ26 (0x40u)
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| 60 | #define CPG_STBREQ2_STBRQ27 (0x80u)
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| 61 |
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| 62 | #define CPG_STBACK1_STBAK10 (0x01u)
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| 63 | #define CPG_STBACK1_STBAK12 (0x04u)
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| 64 | #define CPG_STBACK1_STBAK13 (0x08u)
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| 65 | #define CPG_STBACK1_STBAK15 (0x20u)
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| 66 |
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| 67 | #define CPG_STBACK2_STBAK20 (0x01u)
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| 68 | #define CPG_STBACK2_STBAK21 (0x02u)
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| 69 | #define CPG_STBACK2_STBAK22 (0x04u)
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| 70 | #define CPG_STBACK2_STBAK23 (0x08u)
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| 71 | #define CPG_STBACK2_STBAK24 (0x10u)
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| 72 | #define CPG_STBACK2_STBAK25 (0x20u)
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| 73 | #define CPG_STBACK2_STBAK26 (0x40u)
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| 74 | #define CPG_STBACK2_STBAK27 (0x80u)
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| 75 |
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| 76 | #define CPG_SYSCR1_VRAME0 (0x01u)
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| 77 | #define CPG_SYSCR1_VRAME1 (0x02u)
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| 78 | #define CPG_SYSCR1_VRAME2 (0x04u)
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| 79 | #define CPG_SYSCR1_VRAME3 (0x08u)
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| 80 | #define CPG_SYSCR1_VRAME4 (0x10u)
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| 81 |
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| 82 | #define CPG_SYSCR2_VRAMWE0 (0x01u)
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| 83 | #define CPG_SYSCR2_VRAMWE1 (0x02u)
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| 84 | #define CPG_SYSCR2_VRAMWE2 (0x04u)
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| 85 | #define CPG_SYSCR2_VRAMWE3 (0x08u)
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| 86 | #define CPG_SYSCR2_VRAMWE4 (0x10u)
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| 87 |
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| 88 | #define CPG_SYSCR3_RRAMWE0 (0x01u)
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| 89 | #define CPG_SYSCR3_RRAMWE1 (0x02u)
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| 90 | #define CPG_SYSCR3_RRAMWE2 (0x04u)
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| 91 | #define CPG_SYSCR3_RRAMWE3 (0x08u)
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| 92 |
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| 93 | #define CPG_STBCR3_MSTP30 (0x01u)
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| 94 | #define CPG_STBCR3_MSTP31 (0x02u)
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| 95 | #define CPG_STBCR3_MSTP32 (0x04u)
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| 96 | #define CPG_STBCR3_MSTP33 (0x08u)
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| 97 | #define CPG_STBCR3_MSTP34 (0x10u)
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| 98 | #define CPG_STBCR3_MSTP35 (0x20u)
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| 99 | #define CPG_STBCR3_MSTP36 (0x40u)
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| 100 | #define CPG_STBCR3_MSTP37 (0x80u)
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| 101 |
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| 102 | #define CPG_STBCR4_MSTP40 (0x01u)
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| 103 | #define CPG_STBCR4_MSTP41 (0x02u)
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| 104 | #define CPG_STBCR4_MSTP42 (0x04u)
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| 105 | #define CPG_STBCR4_MSTP43 (0x08u)
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| 106 | #define CPG_STBCR4_MSTP44 (0x10u)
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| 107 | #define CPG_STBCR4_MSTP45 (0x20u)
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| 108 | #define CPG_STBCR4_MSTP46 (0x40u)
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| 109 | #define CPG_STBCR4_MSTP47 (0x80u)
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| 110 |
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| 111 | #define CPG_STBCR5_MSTP50 (0x01u)
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| 112 | #define CPG_STBCR5_MSTP51 (0x02u)
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| 113 | #define CPG_STBCR5_MSTP52 (0x04u)
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| 114 | #define CPG_STBCR5_MSTP53 (0x08u)
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| 115 | #define CPG_STBCR5_MSTP54 (0x10u)
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| 116 | #define CPG_STBCR5_MSTP55 (0x20u)
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| 117 | #define CPG_STBCR5_MSTP56 (0x40u)
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| 118 | #define CPG_STBCR5_MSTP57 (0x80u)
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| 119 |
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| 120 | #define CPG_STBCR6_MSTP60 (0x01u)
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| 121 | #define CPG_STBCR6_MSTP61 (0x02u)
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| 122 | #define CPG_STBCR6_MSTP62 (0x04u)
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| 123 | #define CPG_STBCR6_MSTP63 (0x08u)
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| 124 | #define CPG_STBCR6_MSTP64 (0x10u)
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| 125 | #define CPG_STBCR6_MSTP65 (0x20u)
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| 126 | #define CPG_STBCR6_MSTP66 (0x40u)
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| 127 | #define CPG_STBCR6_MSTP67 (0x80u)
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| 128 |
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| 129 | #define CPG_STBCR7_MSTP70 (0x01u)
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| 130 | #define CPG_STBCR7_MSTP71 (0x02u)
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| 131 | #define CPG_STBCR7_MSTP73 (0x08u)
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| 132 | #define CPG_STBCR7_MSTP74 (0x10u)
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| 133 | #define CPG_STBCR7_MSTP76 (0x40u)
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| 134 | #define CPG_STBCR7_MSTP77 (0x80u)
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| 135 |
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| 136 | #define CPG_STBCR8_MSTP81 (0x02u)
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| 137 | #define CPG_STBCR8_MSTP82 (0x04u)
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| 138 | #define CPG_STBCR8_MSTP83 (0x08u)
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| 139 | #define CPG_STBCR8_MSTP84 (0x10u)
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| 140 | #define CPG_STBCR8_MSTP85 (0x20u)
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| 141 | #define CPG_STBCR8_MSTP86 (0x40u)
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| 142 | #define CPG_STBCR8_MSTP87 (0x80u)
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| 143 |
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| 144 | #define CPG_STBCR9_MSTP90 (0x01u)
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| 145 | #define CPG_STBCR9_MSTP91 (0x02u)
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| 146 | #define CPG_STBCR9_MSTP92 (0x04u)
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| 147 | #define CPG_STBCR9_MSTP93 (0x08u)
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| 148 | #define CPG_STBCR9_MSTP94 (0x10u)
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| 149 | #define CPG_STBCR9_MSTP95 (0x20u)
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| 150 | #define CPG_STBCR9_MSTP96 (0x40u)
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| 151 | #define CPG_STBCR9_MSTP97 (0x80u)
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| 152 |
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| 153 | #define CPG_STBCR10_MSTP100 (0x01u)
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| 154 | #define CPG_STBCR10_MSTP101 (0x02u)
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| 155 | #define CPG_STBCR10_MSTP102 (0x04u)
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| 156 | #define CPG_STBCR10_MSTP103 (0x08u)
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| 157 | #define CPG_STBCR10_MSTP104 (0x10u)
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| 158 | #define CPG_STBCR10_MSTP105 (0x20u)
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| 159 | #define CPG_STBCR10_MSTP106 (0x40u)
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| 160 | #define CPG_STBCR10_MSTP107 (0x80u)
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| 161 |
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| 162 | #define CPG_STBCR11_MSTP110 (0x01u)
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| 163 | #define CPG_STBCR11_MSTP111 (0x02u)
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| 164 | #define CPG_STBCR11_MSTP112 (0x04u)
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| 165 | #define CPG_STBCR11_MSTP113 (0x08u)
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| 166 | #define CPG_STBCR11_MSTP114 (0x10u)
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| 167 | #define CPG_STBCR11_MSTP115 (0x20u)
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| 168 |
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| 169 | #define CPG_STBCR12_MSTP120 (0x01u)
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| 170 | #define CPG_STBCR12_MSTP121 (0x02u)
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| 171 | #define CPG_STBCR12_MSTP122 (0x04u)
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| 172 | #define CPG_STBCR12_MSTP123 (0x08u)
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| 173 |
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| 174 | #define CPG_STBCR13_MSTP131 (0x02u)
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| 175 | #define CPG_STBCR13_MSTP132 (0x04u)
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| 176 |
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| 177 | #define CPG_SWRSTCR1_SRST11 (0x02u)
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| 178 | #define CPG_SWRSTCR1_SRST12 (0x04u)
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| 179 | #define CPG_SWRSTCR1_SRST13 (0x08u)
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| 180 | #define CPG_SWRSTCR1_SRST14 (0x10u)
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| 181 | #define CPG_SWRSTCR1_SRST15 (0x20u)
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| 182 | #define CPG_SWRSTCR1_SRST16 (0x40u)
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| 183 | #define CPG_SWRSTCR1_AXTALE (0x80u)
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| 184 |
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| 185 | #define CPG_SWRSTCR2_SRST21 (0x02u)
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| 186 |
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| 187 | #define CPG_SWRSTCR3_SRST32 (0x04u)
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| 188 |
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| 189 | #define CPG_RRAMKP_RRAMKP0 (0x01u)
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| 190 | #define CPG_RRAMKP_RRAMKP1 (0x02u)
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| 191 | #define CPG_RRAMKP_RRAMKP2 (0x04u)
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| 192 | #define CPG_RRAMKP_RRAMKP3 (0x08u)
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| 193 |
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| 194 | #define CPG_DSCTR_RAMBOOT (0x40u)
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| 195 | #define CPG_DSCTR_EBUSKEEPE (0x80u)
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| 196 |
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| 197 | #define CPG_DSSSR_P8_2 (0x0001u)
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| 198 | #define CPG_DSSSR_P9_1 (0x0002u)
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| 199 | #define CPG_DSSSR_P2_15 (0x0004u)
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| 200 | #define CPG_DSSSR_P7_8 (0x0008u)
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| 201 | #define CPG_DSSSR_P5_9 (0x0010u)
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| 202 | #define CPG_DSSSR_P6_4 (0x0020u)
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| 203 | #define CPG_DSSSR_RTCAR (0x0040u)
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| 204 | #define CPG_DSSSR_NMI (0x0100u)
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| 205 | #define CPG_DSSSR_P3_3 (0x0200u)
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| 206 | #define CPG_DSSSR_P8_7 (0x0400u)
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| 207 | #define CPG_DSSSR_P2_12 (0x0800u)
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| 208 | #define CPG_DSSSR_P3_1 (0x1000u)
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| 209 | #define CPG_DSSSR_P3_9 (0x2000u)
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| 210 | #define CPG_DSSSR_P6_2 (0x4000u)
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| 211 |
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| 212 | #define CPG_DSESR_P8_2E (0x0001u)
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| 213 | #define CPG_DSESR_P9_1E (0x0002u)
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| 214 | #define CPG_DSESR_P2_15E (0x0004u)
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| 215 | #define CPG_DSESR_P7_8E (0x0008u)
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| 216 | #define CPG_DSESR_P5_9E (0x0010u)
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| 217 | #define CPG_DSESR_P6_4E (0x0020u)
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| 218 | #define CPG_DSESR_NMIE (0x0100u)
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| 219 | #define CPG_DSESR_P3_3E (0x0200u)
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| 220 | #define CPG_DSESR_P8_7E (0x0400u)
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| 221 | #define CPG_DSESR_P2_12E (0x0800u)
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| 222 | #define CPG_DSESR_P3_1E (0x1000u)
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| 223 | #define CPG_DSESR_P3_9E (0x2000u)
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| 224 | #define CPG_DSESR_P6_2E (0x4000u)
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| 225 |
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| 226 | #define CPG_DSFR_P8_2F (0x0001u)
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| 227 | #define CPG_DSFR_P9_1F (0x0002u)
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| 228 | #define CPG_DSFR_P2_15F (0x0004u)
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| 229 | #define CPG_DSFR_P7_8F (0x0008u)
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| 230 | #define CPG_DSFR_P5_9F (0x0010u)
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| 231 | #define CPG_DSFR_P6_4F (0x0020u)
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| 232 | #define CPG_DSFR_RTCARF (0x0040u)
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| 233 | #define CPG_DSFR_NMIF (0x0100u)
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| 234 | #define CPG_DSFR_P3_3F (0x0200u)
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| 235 | #define CPG_DSFR_P8_7F (0x0400u)
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| 236 | #define CPG_DSFR_P2_12F (0x0800u)
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| 237 | #define CPG_DSFR_P3_1F (0x1000u)
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| 238 | #define CPG_DSFR_P3_9F (0x2000u)
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| 239 | #define CPG_DSFR_P6_2F (0x4000u)
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| 240 | #define CPG_DSFR_IOKEEP (0x8000u)
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| 241 |
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| 242 | #define CPG_XTALCTR_GAIN0 (0x01u)
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| 243 | #define CPG_XTALCTR_GAIN1 (0x02u)
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| 244 |
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| 245 |
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| 246 | /* ==== Shift values for IO registers ==== */
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| 247 | #define CPG_FRQCR_IFC_SHIFT (8u)
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| 248 | #define CPG_FRQCR_CKOEN_SHIFT (12u)
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| 249 | #define CPG_FRQCR_CKOEN2_SHIFT (14u)
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| 250 |
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| 251 | #define CPG_FRQCR2_GFC_SHIFT (0u)
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| 252 |
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| 253 | #define CPG_CPUSTS_ISBUSY_SHIFT (4u)
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| 254 |
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| 255 | #define CPG_STBCR1_DEEP_SHIFT (6u)
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| 256 | #define CPG_STBCR1_STBY_SHIFT (7u)
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| 257 |
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| 258 | #define CPG_STBCR2_MSTP20_SHIFT (0u)
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| 259 | #define CPG_STBCR2_HIZ_SHIFT (7u)
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| 260 |
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| 261 | #define CPG_STBREQ1_STBRQ10_SHIFT (0u)
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| 262 | #define CPG_STBREQ1_STBRQ12_SHIFT (2u)
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| 263 | #define CPG_STBREQ1_STBRQ13_SHIFT (3u)
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| 264 | #define CPG_STBREQ1_STBRQ15_SHIFT (5u)
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| 265 |
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| 266 | #define CPG_STBREQ2_STBRQ20_SHIFT (0u)
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| 267 | #define CPG_STBREQ2_STBRQ21_SHIFT (1u)
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| 268 | #define CPG_STBREQ2_STBRQ22_SHIFT (2u)
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| 269 | #define CPG_STBREQ2_STBRQ23_SHIFT (3u)
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| 270 | #define CPG_STBREQ2_STBRQ24_SHIFT (4u)
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| 271 | #define CPG_STBREQ2_STBRQ25_SHIFT (5u)
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| 272 | #define CPG_STBREQ2_STBRQ26_SHIFT (6u)
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| 273 | #define CPG_STBREQ2_STBRQ27_SHIFT (7u)
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| 274 |
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| 275 | #define CPG_STBACK1_STBAK10_SHIFT (0u)
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| 276 | #define CPG_STBACK1_STBAK12_SHIFT (2u)
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| 277 | #define CPG_STBACK1_STBAK13_SHIFT (3u)
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| 278 | #define CPG_STBACK1_STBAK15_SHIFT (5u)
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| 279 |
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| 280 | #define CPG_STBACK2_STBAK20_SHIFT (0u)
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| 281 | #define CPG_STBACK2_STBAK21_SHIFT (1u)
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| 282 | #define CPG_STBACK2_STBAK22_SHIFT (2u)
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| 283 | #define CPG_STBACK2_STBAK23_SHIFT (3u)
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| 284 | #define CPG_STBACK2_STBAK24_SHIFT (4u)
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| 285 | #define CPG_STBACK2_STBAK25_SHIFT (5u)
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| 286 | #define CPG_STBACK2_STBAK26_SHIFT (6u)
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| 287 | #define CPG_STBACK2_STBAK27_SHIFT (7u)
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| 288 |
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| 289 | #define CPG_SYSCR1_VRAME0_SHIFT (0u)
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| 290 | #define CPG_SYSCR1_VRAME1_SHIFT (1u)
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| 291 | #define CPG_SYSCR1_VRAME2_SHIFT (2u)
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| 292 | #define CPG_SYSCR1_VRAME3_SHIFT (3u)
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| 293 | #define CPG_SYSCR1_VRAME4_SHIFT (4u)
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| 294 |
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| 295 | #define CPG_SYSCR2_VRAMWE0_SHIFT (0u)
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| 296 | #define CPG_SYSCR2_VRAMWE1_SHIFT (1u)
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| 297 | #define CPG_SYSCR2_VRAMWE2_SHIFT (2u)
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| 298 | #define CPG_SYSCR2_VRAMWE3_SHIFT (3u)
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| 299 | #define CPG_SYSCR2_VRAMWE4_SHIFT (4u)
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| 300 |
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| 301 | #define CPG_SYSCR3_RRAMWE0_SHIFT (0u)
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| 302 | #define CPG_SYSCR3_RRAMWE1_SHIFT (1u)
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| 303 | #define CPG_SYSCR3_RRAMWE2_SHIFT (2u)
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| 304 | #define CPG_SYSCR3_RRAMWE3_SHIFT (3u)
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| 305 |
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| 306 | #define CPG_STBCR3_MSTP30_SHIFT (0u)
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| 307 | #define CPG_STBCR3_MSTP31_SHIFT (1u)
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| 308 | #define CPG_STBCR3_MSTP32_SHIFT (2u)
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| 309 | #define CPG_STBCR3_MSTP33_SHIFT (3u)
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| 310 | #define CPG_STBCR3_MSTP34_SHIFT (4u)
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| 311 | #define CPG_STBCR3_MSTP35_SHIFT (5u)
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| 312 | #define CPG_STBCR3_MSTP36_SHIFT (6u)
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| 313 | #define CPG_STBCR3_MSTP37_SHIFT (7u)
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| 314 |
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| 315 | #define CPG_STBCR4_MSTP40_SHIFT (0u)
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| 316 | #define CPG_STBCR4_MSTP41_SHIFT (1u)
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| 317 | #define CPG_STBCR4_MSTP42_SHIFT (2u)
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| 318 | #define CPG_STBCR4_MSTP43_SHIFT (3u)
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| 319 | #define CPG_STBCR4_MSTP44_SHIFT (4u)
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| 320 | #define CPG_STBCR4_MSTP45_SHIFT (5u)
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| 321 | #define CPG_STBCR4_MSTP46_SHIFT (6u)
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| 322 | #define CPG_STBCR4_MSTP47_SHIFT (7u)
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| 323 |
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| 324 | #define CPG_STBCR5_MSTP50_SHIFT (0u)
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| 325 | #define CPG_STBCR5_MSTP51_SHIFT (1u)
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| 326 | #define CPG_STBCR5_MSTP52_SHIFT (2u)
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| 327 | #define CPG_STBCR5_MSTP53_SHIFT (3u)
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| 328 | #define CPG_STBCR5_MSTP54_SHIFT (4u)
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| 329 | #define CPG_STBCR5_MSTP55_SHIFT (5u)
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| 330 | #define CPG_STBCR5_MSTP56_SHIFT (6u)
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| 331 | #define CPG_STBCR5_MSTP57_SHIFT (7u)
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| 332 |
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| 333 | #define CPG_STBCR6_MSTP60_SHIFT (0u)
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| 334 | #define CPG_STBCR6_MSTP61_SHIFT (1u)
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| 335 | #define CPG_STBCR6_MSTP62_SHIFT (2u)
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| 336 | #define CPG_STBCR6_MSTP63_SHIFT (3u)
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| 337 | #define CPG_STBCR6_MSTP64_SHIFT (4u)
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| 338 | #define CPG_STBCR6_MSTP65_SHIFT (5u)
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| 339 | #define CPG_STBCR6_MSTP66_SHIFT (6u)
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| 340 | #define CPG_STBCR6_MSTP67_SHIFT (7u)
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| 341 |
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| 342 | #define CPG_STBCR7_MSTP70_SHIFT (0u)
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| 343 | #define CPG_STBCR7_MSTP71_SHIFT (1u)
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| 344 | #define CPG_STBCR7_MSTP73_SHIFT (3u)
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| 345 | #define CPG_STBCR7_MSTP74_SHIFT (4u)
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| 346 | #define CPG_STBCR7_MSTP76_SHIFT (6u)
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| 347 | #define CPG_STBCR7_MSTP77_SHIFT (7u)
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| 348 |
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| 349 | #define CPG_STBCR8_MSTP81_SHIFT (1u)
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| 350 | #define CPG_STBCR8_MSTP82_SHIFT (2u)
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| 351 | #define CPG_STBCR8_MSTP83_SHIFT (3u)
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| 352 | #define CPG_STBCR8_MSTP84_SHIFT (4u)
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| 353 | #define CPG_STBCR8_MSTP85_SHIFT (5u)
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| 354 | #define CPG_STBCR8_MSTP86_SHIFT (6u)
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| 355 | #define CPG_STBCR8_MSTP87_SHIFT (7u)
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| 356 |
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| 357 | #define CPG_STBCR9_MSTP90_SHIFT (0u)
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| 358 | #define CPG_STBCR9_MSTP91_SHIFT (1u)
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| 359 | #define CPG_STBCR9_MSTP92_SHIFT (2u)
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| 360 | #define CPG_STBCR9_MSTP93_SHIFT (3u)
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| 361 | #define CPG_STBCR9_MSTP94_SHIFT (4u)
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| 362 | #define CPG_STBCR9_MSTP95_SHIFT (5u)
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| 363 | #define CPG_STBCR9_MSTP96_SHIFT (6u)
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| 364 | #define CPG_STBCR9_MSTP97_SHIFT (7u)
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| 365 |
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| 366 | #define CPG_STBCR10_MSTP100_SHIFT (0u)
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| 367 | #define CPG_STBCR10_MSTP101_SHIFT (1u)
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| 368 | #define CPG_STBCR10_MSTP102_SHIFT (2u)
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| 369 | #define CPG_STBCR10_MSTP103_SHIFT (3u)
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| 370 | #define CPG_STBCR10_MSTP104_SHIFT (4u)
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| 371 | #define CPG_STBCR10_MSTP105_SHIFT (5u)
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| 372 | #define CPG_STBCR10_MSTP106_SHIFT (6u)
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| 373 | #define CPG_STBCR10_MSTP107_SHIFT (7u)
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| 374 |
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| 375 | #define CPG_STBCR11_MSTP110_SHIFT (0u)
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|---|
| 376 | #define CPG_STBCR11_MSTP111_SHIFT (1u)
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| 377 | #define CPG_STBCR11_MSTP112_SHIFT (2u)
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| 378 | #define CPG_STBCR11_MSTP113_SHIFT (3u)
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| 379 | #define CPG_STBCR11_MSTP114_SHIFT (4u)
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|---|
| 380 | #define CPG_STBCR11_MSTP115_SHIFT (5u)
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| 381 |
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| 382 | #define CPG_STBCR12_MSTP120_SHIFT (0u)
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|---|
| 383 | #define CPG_STBCR12_MSTP121_SHIFT (1u)
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|---|
| 384 | #define CPG_STBCR12_MSTP122_SHIFT (2u)
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|---|
| 385 | #define CPG_STBCR12_MSTP123_SHIFT (3u)
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|---|
| 386 |
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| 387 | #define CPG_STBCR13_MSTP131_SHIFT (1u)
|
|---|
| 388 | #define CPG_STBCR13_MSTP132_SHIFT (2u)
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|---|
| 389 |
|
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| 390 | #define CPG_SWRSTCR1_SRST11_SHIFT (1u)
|
|---|
| 391 | #define CPG_SWRSTCR1_SRST12_SHIFT (2u)
|
|---|
| 392 | #define CPG_SWRSTCR1_SRST13_SHIFT (3u)
|
|---|
| 393 | #define CPG_SWRSTCR1_SRST14_SHIFT (4u)
|
|---|
| 394 | #define CPG_SWRSTCR1_SRST15_SHIFT (5u)
|
|---|
| 395 | #define CPG_SWRSTCR1_SRST16_SHIFT (6u)
|
|---|
| 396 | #define CPG_SWRSTCR1_AXTALE_SHIFT (7u)
|
|---|
| 397 |
|
|---|
| 398 | #define CPG_SWRSTCR2_SRST21_SHIFT (1u)
|
|---|
| 399 |
|
|---|
| 400 | #define CPG_SWRSTCR3_SRST32_SHIFT (2u)
|
|---|
| 401 |
|
|---|
| 402 | #define CPG_RRAMKP_RRAMKP0_SHIFT (0u)
|
|---|
| 403 | #define CPG_RRAMKP_RRAMKP1_SHIFT (1u)
|
|---|
| 404 | #define CPG_RRAMKP_RRAMKP2_SHIFT (2u)
|
|---|
| 405 | #define CPG_RRAMKP_RRAMKP3_SHIFT (3u)
|
|---|
| 406 |
|
|---|
| 407 | #define CPG_DSCTR_RAMBOOT_SHIFT (6u)
|
|---|
| 408 | #define CPG_DSCTR_EBUSKEEPE_SHIFT (7u)
|
|---|
| 409 |
|
|---|
| 410 | #define CPG_DSSSR_P8_2_SHIFT (0u)
|
|---|
| 411 | #define CPG_DSSSR_P9_1_SHIFT (1u)
|
|---|
| 412 | #define CPG_DSSSR_P2_15_SHIFT (2u)
|
|---|
| 413 | #define CPG_DSSSR_P7_8_SHIFT (3u)
|
|---|
| 414 | #define CPG_DSSSR_P5_9_SHIFT (4u)
|
|---|
| 415 | #define CPG_DSSSR_P6_4_SHIFT (5u)
|
|---|
| 416 | #define CPG_DSSSR_RTCAR_SHIFT (6u)
|
|---|
| 417 | #define CPG_DSSSR_NMI_SHIFT (8u)
|
|---|
| 418 | #define CPG_DSSSR_P3_3_SHIFT (9u)
|
|---|
| 419 | #define CPG_DSSSR_P8_7_SHIFT (10u)
|
|---|
| 420 | #define CPG_DSSSR_P2_12_SHIFT (11u)
|
|---|
| 421 | #define CPG_DSSSR_P3_1_SHIFT (12u)
|
|---|
| 422 | #define CPG_DSSSR_P3_9_SHIFT (13u)
|
|---|
| 423 | #define CPG_DSSSR_P6_2_SHIFT (14u)
|
|---|
| 424 |
|
|---|
| 425 | #define CPG_DSESR_P8_2E_SHIFT (0u)
|
|---|
| 426 | #define CPG_DSESR_P9_1E_SHIFT (1u)
|
|---|
| 427 | #define CPG_DSESR_P2_15E_SHIFT (2u)
|
|---|
| 428 | #define CPG_DSESR_P7_8E_SHIFT (3u)
|
|---|
| 429 | #define CPG_DSESR_P5_9E_SHIFT (4u)
|
|---|
| 430 | #define CPG_DSESR_P6_4E_SHIFT (5u)
|
|---|
| 431 | #define CPG_DSESR_NMIE_SHIFT (8u)
|
|---|
| 432 | #define CPG_DSESR_P3_3E_SHIFT (9u)
|
|---|
| 433 | #define CPG_DSESR_P8_7E_SHIFT (10u)
|
|---|
| 434 | #define CPG_DSESR_P2_12E_SHIFT (11u)
|
|---|
| 435 | #define CPG_DSESR_P3_1E_SHIFT (12u)
|
|---|
| 436 | #define CPG_DSESR_P3_9E_SHIFT (13u)
|
|---|
| 437 | #define CPG_DSESR_P6_2E_SHIFT (14u)
|
|---|
| 438 |
|
|---|
| 439 | #define CPG_DSFR_P8_2F_SHIFT (0u)
|
|---|
| 440 | #define CPG_DSFR_P9_1F_SHIFT (1u)
|
|---|
| 441 | #define CPG_DSFR_P2_15F_SHIFT (2u)
|
|---|
| 442 | #define CPG_DSFR_P7_8F_SHIFT (3u)
|
|---|
| 443 | #define CPG_DSFR_P5_9F_SHIFT (4u)
|
|---|
| 444 | #define CPG_DSFR_P6_4F_SHIFT (5u)
|
|---|
| 445 | #define CPG_DSFR_RTCARF_SHIFT (6u)
|
|---|
| 446 | #define CPG_DSFR_NMIF_SHIFT (8u)
|
|---|
| 447 | #define CPG_DSFR_P3_3F_SHIFT (9u)
|
|---|
| 448 | #define CPG_DSFR_P8_7F_SHIFT (10u)
|
|---|
| 449 | #define CPG_DSFR_P2_12F_SHIFT (11u)
|
|---|
| 450 | #define CPG_DSFR_P3_1F_SHIFT (12u)
|
|---|
| 451 | #define CPG_DSFR_P3_9F_SHIFT (13u)
|
|---|
| 452 | #define CPG_DSFR_P6_2F_SHIFT (14u)
|
|---|
| 453 | #define CPG_DSFR_IOKEEP_SHIFT (15u)
|
|---|
| 454 |
|
|---|
| 455 | #define CPG_XTALCTR_GAIN0_SHIFT (0u)
|
|---|
| 456 | #define CPG_XTALCTR_GAIN1_SHIFT (1u)
|
|---|
| 457 |
|
|---|
| 458 |
|
|---|
| 459 | #endif /* CPG_IOBITMASK_H */
|
|---|
| 460 |
|
|---|
| 461 | /* End of File */
|
|---|
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