1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer
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21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : bsc_iobitmask.h
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25 | * $Rev: 1115 $
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26 | * $Date:: 2014-07-09 15:35:02 +0900#$
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27 | * Description : BSC register define header
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28 | *******************************************************************************/
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29 | #ifndef BSC_IOBITMASK_H
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30 | #define BSC_IOBITMASK_H
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31 |
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32 |
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33 | /* ==== Mask values for IO registers ==== */
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34 | #define BSC_CMNCR_HIZCNT (0x00000001uL)
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35 | #define BSC_CMNCR_HIZMEM (0x00000002uL)
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36 | #define BSC_CMNCR_DPRTY (0x00000600uL)
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37 | #define BSC_CMNCR_AL0 (0x01000000uL)
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38 | #define BSC_CMNCR_TL0 (0x10000000uL)
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39 |
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40 | #define BSC_CS0BCR_BSZ (0x00000600uL)
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41 | #define BSC_CS0BCR_TYPE (0x00007000uL)
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42 | #define BSC_CS0BCR_IWRRS (0x00070000uL)
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43 | #define BSC_CS0BCR_IWRRD (0x00380000uL)
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44 | #define BSC_CS0BCR_IWRWS (0x01C00000uL)
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45 | #define BSC_CS0BCR_IWRWD (0x0E000000uL)
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46 | #define BSC_CS0BCR_IWW (0x70000000uL)
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47 |
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48 | #define BSC_CS1BCR_BSZ (0x00000600uL)
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49 | #define BSC_CS1BCR_TYPE (0x00007000uL)
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50 | #define BSC_CS1BCR_IWRRS (0x00070000uL)
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51 | #define BSC_CS1BCR_IWRRD (0x00380000uL)
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52 | #define BSC_CS1BCR_IWRWS (0x01C00000uL)
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53 | #define BSC_CS1BCR_IWRWD (0x0E000000uL)
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54 | #define BSC_CS1BCR_IWW (0x70000000uL)
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55 |
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56 | #define BSC_CS2BCR_BSZ (0x00000600uL)
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57 | #define BSC_CS2BCR_TYPE (0x00007000uL)
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58 | #define BSC_CS2BCR_IWRRS (0x00070000uL)
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59 | #define BSC_CS2BCR_IWRRD (0x00380000uL)
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60 | #define BSC_CS2BCR_IWRWS (0x01C00000uL)
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61 | #define BSC_CS2BCR_IWRWD (0x0E000000uL)
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62 | #define BSC_CS2BCR_IWW (0x70000000uL)
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63 |
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64 | #define BSC_CS3BCR_BSZ (0x00000600uL)
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65 | #define BSC_CS3BCR_TYPE (0x00007000uL)
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66 | #define BSC_CS3BCR_IWRRS (0x00070000uL)
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67 | #define BSC_CS3BCR_IWRRD (0x00380000uL)
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68 | #define BSC_CS3BCR_IWRWS (0x01C00000uL)
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69 | #define BSC_CS3BCR_IWRWD (0x0E000000uL)
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70 | #define BSC_CS3BCR_IWW (0x70000000uL)
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71 |
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72 | #define BSC_CS4BCR_BSZ (0x00000600uL)
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73 | #define BSC_CS4BCR_TYPE (0x00007000uL)
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74 | #define BSC_CS4BCR_IWRRS (0x00070000uL)
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75 | #define BSC_CS4BCR_IWRRD (0x00380000uL)
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76 | #define BSC_CS4BCR_IWRWS (0x01C00000uL)
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77 | #define BSC_CS4BCR_IWRWD (0x0E000000uL)
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78 | #define BSC_CS4BCR_IWW (0x70000000uL)
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79 |
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80 | #define BSC_CS5BCR_BSZ (0x00000600uL)
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81 | #define BSC_CS5BCR_TYPE (0x00007000uL)
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82 | #define BSC_CS5BCR_IWRRS (0x00070000uL)
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83 | #define BSC_CS5BCR_IWRRD (0x00380000uL)
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84 | #define BSC_CS5BCR_IWRWS (0x01C00000uL)
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85 | #define BSC_CS5BCR_IWRWD (0x0E000000uL)
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86 | #define BSC_CS5BCR_IWW (0x70000000uL)
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87 |
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88 | #define BSC_CS0WCR_NORMAL_HW (0x00000003uL)
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89 | #define BSC_CS0WCR_NORMAL_WM (0x00000040uL)
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90 | #define BSC_CS0WCR_NORMAL_WR (0x00000780uL)
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91 | #define BSC_CS0WCR_NORMAL_SW (0x00001800uL)
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92 | #define BSC_CS0WCR_NORMAL_BAS (0x00100000uL)
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93 |
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94 | #define BSC_CS1WCR_NORMAL_HW (0x00000003uL)
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95 | #define BSC_CS1WCR_NORMAL_WM (0x00000040uL)
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96 | #define BSC_CS1WCR_NORMAL_WR (0x00000780uL)
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97 | #define BSC_CS1WCR_NORMAL_SW (0x00001800uL)
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98 | #define BSC_CS1WCR_NORMAL_WW (0x00070000uL)
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99 | #define BSC_CS1WCR_NORMAL_BAS (0x00100000uL)
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100 |
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101 | #define BSC_CS2WCR_NORMAL_WM (0x00000040uL)
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102 | #define BSC_CS2WCR_NORMAL_WR (0x00000780uL)
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103 | #define BSC_CS2WCR_NORMAL_BAS (0x00100000uL)
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104 |
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105 | #define BSC_CS3WCR_NORMAL_WM (0x00000040uL)
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106 | #define BSC_CS3WCR_NORMAL_WR (0x00000780uL)
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107 | #define BSC_CS3WCR_NORMAL_BAS (0x00100000uL)
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108 |
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109 | #define BSC_CS4WCR_NORMAL_HW (0x00000003uL)
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110 | #define BSC_CS4WCR_NORMAL_WM (0x00000040uL)
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111 | #define BSC_CS4WCR_NORMAL_WR (0x00000780uL)
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112 | #define BSC_CS4WCR_NORMAL_SW (0x00001800uL)
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113 | #define BSC_CS4WCR_NORMAL_WW (0x00070000uL)
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114 | #define BSC_CS4WCR_NORMAL_BAS (0x00100000uL)
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115 |
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116 | #define BSC_CS5WCR_NORMAL_HW (0x00000003uL)
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117 | #define BSC_CS5WCR_NORMAL_WM (0x00000040uL)
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118 | #define BSC_CS5WCR_NORMAL_WR (0x00000780uL)
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119 | #define BSC_CS5WCR_NORMAL_SW (0x00001800uL)
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120 | #define BSC_CS5WCR_NORMAL_WW (0x00070000uL)
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121 | #define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL)
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122 | #define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL)
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123 |
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124 | #define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL)
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125 | #define BSC_CS0WCR_BROM_ASY_W (0x00000780uL)
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126 | #define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL)
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127 | #define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL)
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128 |
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129 | #define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL)
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130 | #define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL)
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131 | #define BSC_CS4WCR_BROM_ASY_W (0x00000780uL)
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132 | #define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL)
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133 | #define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL)
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134 | #define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL)
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135 |
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136 | #define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL)
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137 |
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138 | #define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL)
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139 | #define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL)
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140 | #define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL)
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141 | #define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL)
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142 | #define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL)
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143 |
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144 | #define BSC_CS0WCR_BROM_SY_WM (0x00000040uL)
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145 | #define BSC_CS0WCR_BROM_SY_W (0x00000780uL)
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146 | #define BSC_CS0WCR_BROM_SY_BW (0x00030000uL)
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147 |
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148 | #define BSC_SDCR_A3COL (0x00000003uL)
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149 | #define BSC_SDCR_A3ROW (0x00000018uL)
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150 | #define BSC_SDCR_BACTV (0x00000100uL)
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151 | #define BSC_SDCR_PDOWN (0x00000200uL)
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152 | #define BSC_SDCR_RMODE (0x00000400uL)
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153 | #define BSC_SDCR_RFSH (0x00000800uL)
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154 | #define BSC_SDCR_DEEP (0x00002000uL)
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155 | #define BSC_SDCR_A2COL (0x00030000uL)
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156 | #define BSC_SDCR_A2ROW (0x00180000uL)
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157 |
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158 | #define BSC_RTCSR_RRC (0x00000007uL)
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159 | #define BSC_RTCSR_CKS (0x00000038uL)
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160 | #define BSC_RTCSR_CMIE (0x00000040uL)
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161 | #define BSC_RTCSR_CMF (0x00000080uL)
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162 |
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163 | #define BSC_RTCNT_D (0xFFFFFFFFuL)
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164 |
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165 | #define BSC_RTCOR_D (0xFFFFFFFFuL)
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166 |
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167 | #define BSC_TOSCOR0_D (0x0000FFFFuL)
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168 |
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169 | #define BSC_TOSCOR1_D (0x0000FFFFuL)
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170 |
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171 | #define BSC_TOSCOR2_D (0x0000FFFFuL)
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172 |
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173 | #define BSC_TOSCOR3_D (0x0000FFFFuL)
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174 |
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175 | #define BSC_TOSCOR4_D (0x0000FFFFuL)
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176 |
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177 | #define BSC_TOSCOR5_D (0x0000FFFFuL)
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178 |
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179 | #define BSC_TOSTR_CS0TOSTF (0x00000001uL)
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180 | #define BSC_TOSTR_CS1TOSTF (0x00000002uL)
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181 | #define BSC_TOSTR_CS2TOSTF (0x00000004uL)
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182 | #define BSC_TOSTR_CS3TOSTF (0x00000008uL)
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183 | #define BSC_TOSTR_CS4TOSTF (0x00000010uL)
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184 | #define BSC_TOSTR_CS5TOSTF (0x00000020uL)
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185 |
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186 | #define BSC_TOENR_CS0TOEN (0x00000001uL)
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187 | #define BSC_TOENR_CS1TOEN (0x00000002uL)
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188 | #define BSC_TOENR_CS2TOEN (0x00000004uL)
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189 | #define BSC_TOENR_CS3TOEN (0x00000008uL)
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190 | #define BSC_TOENR_CS4TOEN (0x00000010uL)
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191 | #define BSC_TOENR_CS5TOEN (0x00000020uL)
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192 |
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193 |
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194 | /* ==== Shift values for IO registers ==== */
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195 | #define BSC_CMNCR_HIZCNT_SHIFT (0u)
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196 | #define BSC_CMNCR_HIZMEM_SHIFT (1u)
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197 | #define BSC_CMNCR_DPRTY_SHIFT (9u)
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198 | #define BSC_CMNCR_AL0_SHIFT (24u)
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199 | #define BSC_CMNCR_TL0_SHIFT (28u)
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200 |
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201 | #define BSC_CS0BCR_BSZ_SHIFT (9u)
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202 | #define BSC_CS0BCR_TYPE_SHIFT (12u)
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203 | #define BSC_CS0BCR_IWRRS_SHIFT (16u)
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204 | #define BSC_CS0BCR_IWRRD_SHIFT (19u)
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205 | #define BSC_CS0BCR_IWRWS_SHIFT (22u)
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206 | #define BSC_CS0BCR_IWRWD_SHIFT (25u)
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207 | #define BSC_CS0BCR_IWW_SHIFT (28u)
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208 |
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209 | #define BSC_CS1BCR_BSZ_SHIFT (9u)
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210 | #define BSC_CS1BCR_TYPE_SHIFT (12u)
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211 | #define BSC_CS1BCR_IWRRS_SHIFT (16u)
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212 | #define BSC_CS1BCR_IWRRD_SHIFT (19u)
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213 | #define BSC_CS1BCR_IWRWS_SHIFT (22u)
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214 | #define BSC_CS1BCR_IWRWD_SHIFT (25u)
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215 | #define BSC_CS1BCR_IWW_SHIFT (28u)
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216 |
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217 | #define BSC_CS2BCR_BSZ_SHIFT (9u)
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218 | #define BSC_CS2BCR_TYPE_SHIFT (12u)
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219 | #define BSC_CS2BCR_IWRRS_SHIFT (16u)
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220 | #define BSC_CS2BCR_IWRRD_SHIFT (19u)
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221 | #define BSC_CS2BCR_IWRWS_SHIFT (22u)
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222 | #define BSC_CS2BCR_IWRWD_SHIFT (25u)
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223 | #define BSC_CS2BCR_IWW_SHIFT (28u)
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224 |
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225 | #define BSC_CS3BCR_BSZ_SHIFT (9u)
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226 | #define BSC_CS3BCR_TYPE_SHIFT (12u)
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227 | #define BSC_CS3BCR_IWRRS_SHIFT (16u)
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228 | #define BSC_CS3BCR_IWRRD_SHIFT (19u)
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229 | #define BSC_CS3BCR_IWRWS_SHIFT (22u)
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230 | #define BSC_CS3BCR_IWRWD_SHIFT (25u)
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231 | #define BSC_CS3BCR_IWW_SHIFT (28u)
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232 |
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233 | #define BSC_CS4BCR_BSZ_SHIFT (9u)
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234 | #define BSC_CS4BCR_TYPE_SHIFT (12u)
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235 | #define BSC_CS4BCR_IWRRS_SHIFT (16u)
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236 | #define BSC_CS4BCR_IWRRD_SHIFT (19u)
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237 | #define BSC_CS4BCR_IWRWS_SHIFT (22u)
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238 | #define BSC_CS4BCR_IWRWD_SHIFT (25u)
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239 | #define BSC_CS4BCR_IWW_SHIFT (28u)
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240 |
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241 | #define BSC_CS5BCR_BSZ_SHIFT (9u)
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242 | #define BSC_CS5BCR_TYPE_SHIFT (12u)
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243 | #define BSC_CS5BCR_IWRRS_SHIFT (16u)
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244 | #define BSC_CS5BCR_IWRRD_SHIFT (19u)
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245 | #define BSC_CS5BCR_IWRWS_SHIFT (22u)
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246 | #define BSC_CS5BCR_IWRWD_SHIFT (25u)
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247 | #define BSC_CS5BCR_IWW_SHIFT (28u)
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248 |
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249 | #define BSC_CS0WCR_NORMAL_HW_SHIFT (0u)
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250 | #define BSC_CS0WCR_NORMAL_WM_SHIFT (6u)
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251 | #define BSC_CS0WCR_NORMAL_WR_SHIFT (7u)
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252 | #define BSC_CS0WCR_NORMAL_SW_SHIFT (11u)
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253 | #define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u)
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254 |
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255 | #define BSC_CS1WCR_NORMAL_HW_SHIFT (0u)
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256 | #define BSC_CS1WCR_NORMAL_WM_SHIFT (6u)
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257 | #define BSC_CS1WCR_NORMAL_WR_SHIFT (7u)
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258 | #define BSC_CS1WCR_NORMAL_SW_SHIFT (11u)
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259 | #define BSC_CS1WCR_NORMAL_WW_SHIFT (16u)
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260 | #define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u)
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261 |
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262 | #define BSC_CS2WCR_NORMAL_WM_SHIFT (6u)
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263 | #define BSC_CS2WCR_NORMAL_WR_SHIFT (7u)
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264 | #define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u)
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265 |
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266 | #define BSC_CS3WCR_NORMAL_WM_SHIFT (6u)
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267 | #define BSC_CS3WCR_NORMAL_WR_SHIFT (7u)
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268 | #define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u)
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269 |
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270 | #define BSC_CS4WCR_NORMAL_HW_SHIFT (0u)
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271 | #define BSC_CS4WCR_NORMAL_WM_SHIFT (6u)
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272 | #define BSC_CS4WCR_NORMAL_WR_SHIFT (7u)
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273 | #define BSC_CS4WCR_NORMAL_SW_SHIFT (11u)
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274 | #define BSC_CS4WCR_NORMAL_WW_SHIFT (16u)
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275 | #define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u)
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276 |
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277 | #define BSC_CS5WCR_NORMAL_HW_SHIFT (0u)
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278 | #define BSC_CS5WCR_NORMAL_WM_SHIFT (6u)
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279 | #define BSC_CS5WCR_NORMAL_WR_SHIFT (7u)
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280 | #define BSC_CS5WCR_NORMAL_SW_SHIFT (11u)
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281 | #define BSC_CS5WCR_NORMAL_WW_SHIFT (16u)
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282 | #define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
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283 | #define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u)
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284 |
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285 | #define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u)
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286 | #define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u)
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287 | #define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u)
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288 | #define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u)
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289 |
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290 | #define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u)
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291 | #define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u)
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292 | #define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u)
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293 | #define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u)
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294 | #define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u)
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295 | #define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u)
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296 |
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297 | #define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u)
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298 |
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299 | #define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u)
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300 | #define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u)
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301 | #define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u)
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302 | #define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u)
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303 | #define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u)
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304 |
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305 | #define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u)
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306 | #define BSC_CS0WCR_BROM_SY_W_SHIFT (7u)
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307 | #define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u)
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308 |
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309 | #define BSC_SDCR_A3COL_SHIFT (0u)
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310 | #define BSC_SDCR_A3ROW_SHIFT (3u)
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311 | #define BSC_SDCR_BACTV_SHIFT (8u)
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312 | #define BSC_SDCR_PDOWN_SHIFT (9u)
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313 | #define BSC_SDCR_RMODE_SHIFT (10u)
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314 | #define BSC_SDCR_RFSH_SHIFT (11u)
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315 | #define BSC_SDCR_DEEP_SHIFT (13u)
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316 | #define BSC_SDCR_A2COL_SHIFT (16u)
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317 | #define BSC_SDCR_A2ROW_SHIFT (19u)
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318 |
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319 | #define BSC_RTCSR_RRC_SHIFT (0u)
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320 | #define BSC_RTCSR_CKS_SHIFT (3u)
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321 | #define BSC_RTCSR_CMIE_SHIFT (6u)
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322 | #define BSC_RTCSR_CMF_SHIFT (7u)
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323 |
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324 | #define BSC_RTCNT_D_SHIFT (0u)
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325 |
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326 | #define BSC_RTCOR_D_SHIFT (0u)
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327 |
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328 | #define BSC_TOSCOR0_D_SHIFT (0u)
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329 |
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330 | #define BSC_TOSCOR1_D_SHIFT (0u)
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331 |
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332 | #define BSC_TOSCOR2_D_SHIFT (0u)
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333 |
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334 | #define BSC_TOSCOR3_D_SHIFT (0u)
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335 |
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336 | #define BSC_TOSCOR4_D_SHIFT (0u)
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337 |
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338 | #define BSC_TOSCOR5_D_SHIFT (0u)
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339 |
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340 | #define BSC_TOSTR_CS0TOSTF_SHIFT (0u)
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341 | #define BSC_TOSTR_CS1TOSTF_SHIFT (1u)
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342 | #define BSC_TOSTR_CS2TOSTF_SHIFT (2u)
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343 | #define BSC_TOSTR_CS3TOSTF_SHIFT (3u)
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344 | #define BSC_TOSTR_CS4TOSTF_SHIFT (4u)
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345 | #define BSC_TOSTR_CS5TOSTF_SHIFT (5u)
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346 |
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347 | #define BSC_TOENR_CS0TOEN_SHIFT (0u)
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348 | #define BSC_TOENR_CS1TOEN_SHIFT (1u)
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349 | #define BSC_TOENR_CS2TOEN_SHIFT (2u)
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350 | #define BSC_TOENR_CS3TOEN_SHIFT (3u)
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351 | #define BSC_TOENR_CS4TOEN_SHIFT (4u)
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352 | #define BSC_TOENR_CS5TOEN_SHIFT (5u)
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353 |
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354 |
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355 | #endif /* BSC_IOBITMASK_H */
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356 |
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357 | /* End of File */
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