1 | /**************************************************************************//**
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2 | * @file gic.c
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3 | * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
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4 | * @version
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5 | * @date 19 Sept 2013
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2011 - 2013 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 |
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37 | #include "MBRZA1H.h"
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38 |
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39 | #define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
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40 | #define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
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41 |
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42 | /* Globals for use of post-scatterloading code that must access GIC */
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43 | const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
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44 | const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
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45 |
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46 | void GIC_EnableDistributor(void)
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47 | {
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48 | GICDistributor->ICDDCR |= 1; //enable distributor
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49 | }
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50 |
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51 | void GIC_DisableDistributor(void)
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52 | {
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53 | GICDistributor->ICDDCR &=~1; //disable distributor
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54 | }
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55 |
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56 | uint32_t GIC_DistributorInfo(void)
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57 | {
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58 | return (uint32_t)(GICDistributor->ICDICTR);
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59 | }
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60 |
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61 | uint32_t GIC_DistributorImplementer(void)
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62 | {
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63 | return (uint32_t)(GICDistributor->ICDIIDR);
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64 | }
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65 |
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66 | void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
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67 | {
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68 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
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69 | field += IRQn % 4;
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70 | *field = (uint8_t)cpu_target & 0xf;
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71 | }
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72 |
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73 | void GIC_SetICDICFR (const uint32_t *ICDICFRn)
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74 | {
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75 | uint32_t i, num_irq;
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76 |
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77 | //Get the maximum number of interrupts that the GIC supports
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78 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
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79 |
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80 | for (i = 0; i < (num_irq/16); i++)
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81 | {
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82 | GICDistributor->ICDISPR[i] = *ICDICFRn++;
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83 | }
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84 | }
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85 |
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86 | uint32_t GIC_GetTarget(IRQn_Type IRQn)
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87 | {
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88 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
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89 | field += IRQn % 4;
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90 | return ((uint32_t)*field & 0xf);
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91 | }
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92 |
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93 | void GIC_EnableInterface(void)
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94 | {
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95 | GICInterface->ICCICR |= 1; //enable interface
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96 | }
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97 |
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98 | void GIC_DisableInterface(void)
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99 | {
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100 | GICInterface->ICCICR &=~1; //disable distributor
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101 | }
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102 |
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103 | IRQn_Type GIC_AcknowledgePending(void)
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104 | {
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105 | return (IRQn_Type)(GICInterface->ICCIAR);
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106 | }
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107 |
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108 | void GIC_EndInterrupt(IRQn_Type IRQn)
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109 | {
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110 | GICInterface->ICCEOIR = IRQn;
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111 | }
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112 |
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113 | void GIC_EnableIRQ(IRQn_Type IRQn)
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114 | {
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115 | GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
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116 | }
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117 |
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118 | void GIC_DisableIRQ(IRQn_Type IRQn)
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119 | {
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120 | GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
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121 | }
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122 |
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123 | void GIC_SetPendingIRQ(IRQn_Type IRQn)
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124 | {
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125 | GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
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126 | }
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127 |
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128 | void GIC_ClearPendingIRQ(IRQn_Type IRQn)
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129 | {
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130 | GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
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131 | }
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132 |
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133 | void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
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134 | {
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135 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
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136 | int bit_shift = (IRQn % 16)<<1;
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137 | uint8_t save_byte;
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138 |
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139 | field += (bit_shift / 8);
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140 | bit_shift %= 8;
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141 |
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142 | save_byte = *field;
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143 | save_byte &= ((uint8_t)~(3u << bit_shift));
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144 |
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145 | *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
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146 | }
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147 |
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148 | void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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149 | {
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150 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
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151 | field += (IRQn % 4);
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152 | *field = (uint8_t)priority;
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153 | }
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154 |
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155 | uint32_t GIC_GetPriority(IRQn_Type IRQn)
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156 | {
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157 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
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158 | field += (IRQn % 4);
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159 | return (uint32_t)*field;
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160 | }
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161 |
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162 | void GIC_InterfacePriorityMask(uint32_t priority)
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163 | {
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164 | GICInterface->ICCPMR = priority & 0xff; //set priority mask
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165 | }
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166 |
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167 | void GIC_SetBinaryPoint(uint32_t binary_point)
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168 | {
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169 | GICInterface->ICCBPR = binary_point & 0x07; //set binary point
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170 | }
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171 |
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172 | uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
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173 | {
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174 | return (uint32_t)GICInterface->ICCBPR;
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175 | }
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176 |
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177 | uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
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178 | {
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179 | uint32_t pending, active;
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180 |
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181 | active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
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182 | pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
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183 |
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184 | return ((active<<1) | pending);
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185 | }
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186 |
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187 | void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
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188 | {
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189 | GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
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190 | }
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191 |
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192 | void GIC_DistInit(void)
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193 | {
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194 | //IRQn_Type i;
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195 | uint32_t i;
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196 | uint32_t num_irq = 0;
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197 | uint32_t priority_field;
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198 |
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199 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
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200 | //configuring all of the interrupts as Secure.
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201 |
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202 | //Disable interrupt forwarding
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203 | GIC_DisableDistributor();
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204 | //Get the maximum number of interrupts that the GIC supports
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205 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
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206 |
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207 | /* Priority level is implementation defined.
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208 | To determine the number of priority bits implemented write 0xFF to an ICDIPR
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209 | priority field and read back the value stored.*/
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210 | GIC_SetPriority((IRQn_Type)0, 0xff);
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211 | priority_field = GIC_GetPriority((IRQn_Type)0);
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212 |
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213 | for (i = 32; i < num_irq; i++)
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214 | {
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215 | //Disable all SPI the interrupts
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216 | GIC_DisableIRQ((IRQn_Type)i);
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217 | //Set level-sensitive and N-N model
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218 | //GIC_SetLevelModel(i, 0, 0);
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219 | //Set priority
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220 | GIC_SetPriority((IRQn_Type)i, priority_field/2);
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221 | //Set target list to "all cpus"
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222 | GIC_SetTarget((IRQn_Type)i, 0xff);
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223 | }
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224 | /* Set level-edge and 1-N model */
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225 | /* GICDistributor->ICDICFR[ 0] is read only */
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226 | GICDistributor->ICDICFR[ 1] = 0x00000055;
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227 | GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
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228 | GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
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229 | GICDistributor->ICDICFR[ 4] = 0x55555555;
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230 | GICDistributor->ICDICFR[ 5] = 0x55555555;
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231 | GICDistributor->ICDICFR[ 6] = 0x55555555;
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232 | GICDistributor->ICDICFR[ 7] = 0x55555555;
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233 | GICDistributor->ICDICFR[ 8] = 0x5555F555;
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234 | GICDistributor->ICDICFR[ 9] = 0x55555555;
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235 | GICDistributor->ICDICFR[10] = 0x55555555;
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236 | GICDistributor->ICDICFR[11] = 0xF5555555;
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237 | GICDistributor->ICDICFR[12] = 0xF555F555;
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238 | GICDistributor->ICDICFR[13] = 0x5555F555;
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239 | GICDistributor->ICDICFR[14] = 0x55555555;
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240 | GICDistributor->ICDICFR[15] = 0x55555555;
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241 | GICDistributor->ICDICFR[16] = 0x55555555;
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242 | GICDistributor->ICDICFR[17] = 0xFD555555;
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243 | GICDistributor->ICDICFR[18] = 0x55555557;
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244 | GICDistributor->ICDICFR[19] = 0x55555555;
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245 | GICDistributor->ICDICFR[20] = 0xFFD55555;
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246 | GICDistributor->ICDICFR[21] = 0x5F55557F;
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247 | GICDistributor->ICDICFR[22] = 0xFD55555F;
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248 | GICDistributor->ICDICFR[23] = 0x55555557;
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249 | GICDistributor->ICDICFR[24] = 0x55555555;
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250 | GICDistributor->ICDICFR[25] = 0x55555555;
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251 | GICDistributor->ICDICFR[26] = 0x55555555;
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252 | GICDistributor->ICDICFR[27] = 0x55555555;
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253 | GICDistributor->ICDICFR[28] = 0x55555555;
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254 | GICDistributor->ICDICFR[29] = 0x55555555;
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255 | GICDistributor->ICDICFR[30] = 0x55555555;
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256 | GICDistributor->ICDICFR[31] = 0x55555555;
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257 | GICDistributor->ICDICFR[32] = 0x55555555;
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258 | GICDistributor->ICDICFR[33] = 0x55555555;
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259 |
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260 | //Enable distributor
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261 | GIC_EnableDistributor();
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262 | }
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263 |
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264 | void GIC_CPUInterfaceInit(void)
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265 | {
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266 | IRQn_Type i;
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267 | uint32_t priority_field;
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268 |
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269 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
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270 | //configuring all of the interrupts as Secure.
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271 |
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272 | //Disable interrupt forwarding
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273 | GIC_DisableInterface();
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274 |
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275 | /* Priority level is implementation defined.
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276 | To determine the number of priority bits implemented write 0xFF to an ICDIPR
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277 | priority field and read back the value stored.*/
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278 | GIC_SetPriority((IRQn_Type)0, 0xff);
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279 | priority_field = GIC_GetPriority((IRQn_Type)0);
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280 |
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281 | //SGI and PPI
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282 | for (i = (IRQn_Type)0; i < 32; i++)
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283 | {
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284 | //Set level-sensitive and N-N model for PPI
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285 | //if(i > 15)
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286 | //GIC_SetLevelModel(i, 0, 0);
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287 | //Disable SGI and PPI interrupts
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288 | GIC_DisableIRQ(i);
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289 | //Set priority
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290 | GIC_SetPriority(i, priority_field/2);
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291 | }
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292 | //Enable interface
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293 | GIC_EnableInterface();
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294 | //Set binary point to 0
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295 | GIC_SetBinaryPoint(0);
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296 | //Set priority mask
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297 | GIC_InterfacePriorityMask(0xff);
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298 | }
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299 |
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300 | void GIC_Enable(void)
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301 | {
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302 | GIC_DistInit();
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303 | GIC_CPUInterfaceInit(); //per CPU
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304 | }
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305 |
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