[270] | 1 | /* File: startup_ARMCM3.s
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| 2 | * Purpose: startup file for Cortex-M3/M4 devices. Should use with
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| 3 | * GNU Tools for ARM Embedded Processors
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| 4 | * Version: V1.1
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| 5 | * Date: 17 June 2011
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| 6 | *
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| 7 | * Copyright (C) 2011 ARM Limited. All rights reserved.
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| 8 | * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
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| 9 | * processor based microcontrollers. This file can be freely distributed
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| 10 | * within development tools that are supporting such ARM based processors.
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| 11 | *
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| 12 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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| 13 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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| 15 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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| 16 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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| 17 | */
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| 18 | .syntax unified
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| 19 | .extern sta_ker
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| 20 |
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| 21 | @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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| 22 | .equ USR_MODE , 0x10
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| 23 | .equ FIQ_MODE , 0x11
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| 24 | .equ IRQ_MODE , 0x12
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| 25 | .equ SVC_MODE , 0x13
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| 26 | .equ ABT_MODE , 0x17
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| 27 | .equ UND_MODE , 0x1b
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| 28 | .equ SYS_MODE , 0x1f
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| 29 | .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
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| 30 |
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| 31 | .equ GICI_BASE , 0xe8202000
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| 32 | .equ ICCIAR_OFFSET , 0x0000000C
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| 33 | .equ ICCEOIR_OFFSET , 0x00000010
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| 34 | .equ ICCHPIR_OFFSET , 0x00000018
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| 35 | .equ GICD_BASE , 0xe8201000
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| 36 | .equ ICDISER0_OFFSET , 0x00000100
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| 37 | .equ ICDICER0_OFFSET , 0x00000180
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| 38 | .equ ICDISPR0_OFFSET , 0x00000200
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| 39 | .equ ICDABR0_OFFSET , 0x00000300
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| 40 | .equ ICDIPR0_OFFSET , 0x00000400
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| 41 |
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| 42 | .equ Mode_USR , 0x10
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| 43 | .equ Mode_FIQ , 0x11
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| 44 | .equ Mode_IRQ , 0x12
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| 45 | .equ Mode_SVC , 0x13
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| 46 | .equ Mode_ABT , 0x17
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| 47 | .equ Mode_UND , 0x1B
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| 48 | .equ Mode_SYS , 0x1F
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| 49 |
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| 50 | .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
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| 51 | .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
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| 52 | .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
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| 53 |
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| 54 | .equ GIC_ERRATA_CHECK_1, 0x000003FE
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| 55 | .equ GIC_ERRATA_CHECK_2, 0x000003FF
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| 56 |
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| 57 | .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
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| 58 | .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
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| 59 | .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
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| 60 | .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
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| 61 | .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
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| 62 | .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
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| 63 | .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
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| 64 | .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
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| 65 |
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| 66 | .equ RAM_BASE , 0x80000000
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| 67 | .equ VRAM_BASE , 0x18000000
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| 68 | .equ SRAM_BASE , 0x2e000000
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| 69 | .equ ETHERNET , 0x1a000000
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| 70 | .equ CS3_PERIPHERAL_BASE, 0x1c000000
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| 71 |
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| 72 |
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| 73 | @ Stack Configuration
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| 74 |
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| 75 | .EQU UND_Stack_Size , 0x00000100
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| 76 | .EQU SVC_Stack_Size , 0x00008000
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| 77 | .EQU ABT_Stack_Size , 0x00000100
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| 78 | .EQU FIQ_Stack_Size , 0x00000100
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| 79 | .EQU IRQ_Stack_Size , 0x00008000
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| 80 | .EQU USR_Stack_Size , 0x00004000
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| 81 |
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| 82 | .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
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| 83 |
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| 84 | .section .stack
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| 85 | .align 3
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| 86 | .globl __StackTop
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| 87 | .globl __StackLimit
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| 88 | __StackLimit:
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| 89 | .space ISR_Stack_Size
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| 90 | __initial_sp:
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| 91 | .space USR_Stack_Size
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| 92 | .size __StackLimit, . - __StackLimit
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| 93 | __StackTop:
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| 94 | .size __StackTop, . - __StackTop
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| 95 |
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| 96 |
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| 97 | @ Heap Configuration
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| 98 |
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[331] | 99 | .EQU Heap_Size , 0x00020000
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[270] | 100 |
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| 101 | .section .heap
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| 102 | .align 3
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| 103 | .globl __HeapBase
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| 104 | .globl __HeapLimit
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| 105 | __HeapBase:
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| 106 | .space Heap_Size
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| 107 | .size __HeapBase, . - __HeapBase
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| 108 | __HeapLimit:
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| 109 | .size __HeapLimit, . - __HeapLimit
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| 110 |
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| 111 |
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| 112 | .section .isr_vector
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| 113 | .align 2
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| 114 | .globl __isr_vector
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| 115 | __isr_vector:
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| 116 | .long 0xe59ff018 /* 0x00 */
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| 117 | .long 0xe59ff018 /* 0x04 */
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| 118 | .long 0xe59ff018 /* 0x08 */
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| 119 | .long 0xe59ff018 /* 0x0c */
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| 120 | .long 0xe59ff018 /* 0x10 */
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| 121 | .long 0xe59ff018 /* 0x14 */
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| 122 | .long 0xe59ff018 /* 0x18 */
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| 123 | .long 0xe59ff018 /* 0x1c */
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| 124 |
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| 125 | .long Reset_Handler /* 0x20 */
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| 126 | .long _kernel_undef_handler /* 0x24 */
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| 127 | .long _kernel_svc_handler /* 0x28 */
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| 128 | .long _kernel_pabort_handler /* 0x2c */
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| 129 | .long _kernel_dabort_handler /* 0x30 */
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| 130 | .long 0 /* Reserved */
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| 131 | .long _kernel_irq_handler /* IRQ */
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| 132 | .long _kernel_fiq_handler /* FIQ */
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| 133 |
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| 134 |
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| 135 | .size __isr_vector, . - __isr_vector
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| 136 |
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| 137 | .text
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| 138 | .align 2
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| 139 | .globl Reset_Handler
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| 140 | .type Reset_Handler, %function
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| 141 | Reset_Handler:
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| 142 | @ Put any cores other than 0 to sleep
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| 143 | mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
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| 144 | ands r0, r0, #3
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| 145 |
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| 146 | goToSleep:
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| 147 | wfine
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| 148 | bne goToSleep
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| 149 |
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| 150 | @ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
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| 151 | @ Enables Full Access i.e. in both privileged and non privileged modes
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| 152 | mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
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| 153 | orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
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| 154 | mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
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| 155 | isb
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| 156 |
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| 157 | @ Switch on the VFP and NEON hardware
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| 158 | mov r0, #0x40000000
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| 159 | vmsr fpexc, r0 @ Write FPEXC register, EN bit set
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| 160 |
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| 161 | mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
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| 162 | bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
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| 163 | bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
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| 164 | bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
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| 165 | bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
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| 166 | bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
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| 167 | mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
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| 168 | isb
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| 169 |
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| 170 | @ Set Vector Base Address Register (VBAR) to point to this application's vector table
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| 171 | ldr r0, =__isr_vector
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| 172 | mcr p15, 0, r0, c12, c0, 0
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| 173 |
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| 174 | @ Setup Stack for each exceptional mode
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| 175 | /* ldr r0, =__StackTop */
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| 176 | ldr r0, =(__StackTop - USR_Stack_Size)
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| 177 |
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| 178 | @ Enter Undefined Instruction Mode and set its Stack Pointer
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| 179 | msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
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| 180 | mov sp, r0
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| 181 | sub r0, r0, #UND_Stack_Size
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| 182 |
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| 183 | @ Enter Abort Mode and set its Stack Pointer
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| 184 | msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
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| 185 | mov sp, r0
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| 186 | sub r0, r0, #ABT_Stack_Size
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| 187 |
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| 188 | @ Enter FIQ Mode and set its Stack Pointer
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| 189 | msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
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| 190 | mov sp, r0
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| 191 | sub r0, r0, #FIQ_Stack_Size
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| 192 |
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| 193 | @ Enter IRQ Mode and set its Stack Pointer
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| 194 | msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
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| 195 | mov sp, r0
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| 196 | sub r0, r0, #IRQ_Stack_Size
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| 197 |
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| 198 | @ Enter Supervisor Mode and set its Stack Pointer
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| 199 | msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
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| 200 | mov sp, r0
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| 201 | sub r0, r0, #SVC_Stack_Size
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| 202 |
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| 203 | @ Enter System Mode to complete initialization and enter kernel
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| 204 | msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
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| 205 | mov sp, r0
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| 206 |
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| 207 | isb
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| 208 | ldr r0, =RZ_A1_SetSramWriteEnable
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| 209 | blx r0
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| 210 |
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| 211 | .extern create_translation_table
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| 212 | bl create_translation_table
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| 213 |
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| 214 | @ USR/SYS stack pointer will be set during kernel init
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| 215 | ldr r0, =SystemInit
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| 216 | blx r0
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| 217 | ldr r0, =InitMemorySubsystem
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| 218 | blx r0
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| 219 |
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| 220 | @ fp_init
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| 221 | mov r0, #0x3000000
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| 222 | vmsr fpscr, r0
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| 223 |
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| 224 |
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| 225 | @ data sections copy
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| 226 | ldr r4, =__copy_table_start__
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| 227 | ldr r5, =__copy_table_end__
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| 228 |
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| 229 | .L_loop0:
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| 230 | cmp r4, r5
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| 231 | bge .L_loop0_done
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| 232 | ldr r1, [r4]
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| 233 | ldr r2, [r4, #4]
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| 234 | ldr r3, [r4, #8]
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| 235 |
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| 236 | .L_loop0_0:
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| 237 | subs r3, #4
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| 238 | ittt ge
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| 239 | ldrge r0, [r1, r3]
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| 240 | strge r0, [r2, r3]
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| 241 | bge .L_loop0_0
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| 242 |
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| 243 | adds r4, #12
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| 244 | b .L_loop0
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| 245 |
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| 246 | .L_loop0_done:
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| 247 |
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| 248 | @ bss sections clear
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| 249 | ldr r3, =__zero_table_start__
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| 250 | ldr r4, =__zero_table_end__
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| 251 |
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| 252 | .L_loop2:
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| 253 | cmp r3, r4
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| 254 | bge .L_loop2_done
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| 255 | ldr r1, [r3]
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| 256 | ldr r2, [r3, #4]
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| 257 | movs r0, 0
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| 258 |
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| 259 | .L_loop2_0:
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| 260 | subs r2, #4
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| 261 | itt ge
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| 262 | strge r0, [r1, r2]
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| 263 | bge .L_loop2_0
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| 264 |
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| 265 | adds r3, #8
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| 266 | b .L_loop2
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| 267 | .L_loop2_done:
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| 268 |
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| 269 |
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| 270 | ldr r0, =sta_ker
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| 271 | bx r0
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| 272 |
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| 273 | ldr r0, sf_boot @ dummy to keep boot loader area
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| 274 | loop_here:
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| 275 | b loop_here
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| 276 |
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| 277 | sf_boot:
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| 278 | .word boot_loader
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| 279 |
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| 280 | .pool
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| 281 | .size Reset_Handler, . - Reset_Handler
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| 282 |
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| 283 |
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| 284 | .text
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| 285 |
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| 286 | Undef_Handler:
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| 287 | .global Undef_Handler
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| 288 | .func Undef_Handler
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| 289 | .extern CUndefHandler
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| 290 | SRSDB SP!, #Mode_UND
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| 291 | PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
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| 292 |
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| 293 | MRS R0, SPSR
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| 294 | TST R0, #T_Bit /* Check mode */
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| 295 | MOVEQ R1, #4 /* R1 = 4 ARM mode */
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| 296 | MOVNE R1, #2 /* R1 = 2 Thumb mode */
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| 297 | SUB R0, LR, R1
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| 298 | LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
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| 299 | BEQ undef_cont
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| 300 |
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| 301 | /* Thumb instruction */
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| 302 | /* Determine if it is a 32-bit Thumb instruction */
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| 303 | LDRH R0, [R0]
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| 304 | MOV R2, #0x1c
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| 305 | CMP R2, R0, LSR #11
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| 306 | BHS undef_cont /* 16-bit Thumb instruction */
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| 307 |
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| 308 | /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
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| 309 | LDRH R2, [LR]
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| 310 | ORR R0, R2, R0, LSL #16
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| 311 | undef_cont:
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| 312 | MOV R2, LR /* Set LR to third argument */
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| 313 |
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| 314 | /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
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| 315 | MOV R3, SP /* Ensure stack is 8-byte aligned */
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| 316 | AND R12, R3, #4
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| 317 | SUB SP, SP, R12 /* Adjust stack */
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| 318 | PUSH {R12, LR} /* Store stack adjustment and dummy LR */
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| 319 |
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| 320 | /* R0 Offending instruction */
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| 321 | /* R1 =2 (Thumb) or =4 (ARM) */
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| 322 | BL CUndefHandler
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| 323 |
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| 324 | POP {R12, LR} /* Get stack adjustment & discard dummy LR */
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| 325 | ADD SP, SP, R12 /* Unadjust stack */
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| 326 |
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| 327 | LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
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| 328 | SUB LR, LR, R0
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| 329 | LDR R0, [SP, #28] /* Restore stacked SPSR */
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| 330 | MSR SPSR_cxsf, R0
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| 331 | POP {R0-R4, R12} /* Restore stacked APCS registers */
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| 332 | ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
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| 333 | MOVS PC, LR
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| 334 | .endfunc
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| 335 |
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| 336 | PAbt_Handler:
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| 337 | .global PAbt_Handler
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| 338 | .func PAbt_Handler
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| 339 | .extern CPAbtHandler
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| 340 | SUB LR, LR, #4 /* Pre-adjust LR */
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| 341 | SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
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| 342 | PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
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| 343 | MRC p15, 0, R0, c5, c0, 1 /* IFSR */
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| 344 | MRC p15, 0, R1, c6, c0, 2 /* IFAR */
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| 345 |
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| 346 | MOV R2, LR /* Set LR to third argument */
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| 347 |
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| 348 | /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
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| 349 | MOV R3, SP /* Ensure stack is 8-byte aligned */
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| 350 | AND R12, R3, #4
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| 351 | SUB SP, SP, R12 /* Adjust stack */
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| 352 | PUSH {R12, LR} /* Store stack adjustment and dummy LR */
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| 353 |
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| 354 | BL CPAbtHandler
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| 355 |
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| 356 | POP {R12, LR} /* Get stack adjustment & discard dummy LR */
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| 357 | ADD SP, SP, R12 /* Unadjust stack */
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| 358 |
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| 359 | POP {R0-R4, R12} /* Restore stack APCS registers */
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| 360 | RFEFD SP! /* Return from exception */
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| 361 | .endfunc
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| 362 |
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| 363 | DAbt_Handler:
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| 364 | .global DAbt_Handler
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| 365 | .func DAbt_Handler
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| 366 | .extern CDAbtHandler
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| 367 | SUB LR, LR, #8 /* Pre-adjust LR */
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| 368 | SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
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| 369 | PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
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| 370 | CLREX /* State of exclusive monitors unknown after taken data abort */
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| 371 | MRC p15, 0, R0, c5, c0, 0 /* DFSR */
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| 372 | MRC p15, 0, R1, c6, c0, 0 /* DFAR */
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| 373 |
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| 374 | MOV R2, LR /* Set LR to third argument */
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| 375 |
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| 376 | /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
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| 377 | MOV R3, SP /* Ensure stack is 8-byte aligned */
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| 378 | AND R12, R3, #4
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| 379 | SUB SP, SP, R12 /* Adjust stack */
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| 380 | PUSH {R12, LR} /* Store stack adjustment and dummy LR */
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| 381 |
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| 382 | BL CDAbtHandler
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| 383 |
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| 384 | POP {R12, LR} /* Get stack adjustment & discard dummy LR */
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| 385 | ADD SP, SP, R12 /* Unadjust stack */
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| 386 |
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| 387 | POP {R0-R4, R12} /* Restore stacked APCS registers */
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| 388 | RFEFD SP! /* Return from exception */
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| 389 | .endfunc
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| 390 |
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| 391 | FIQ_Handler:
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| 392 | .global FIQ_Handler
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| 393 | .func FIQ_Handler
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| 394 | /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
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| 395 | * so if a real FIQ Handler is implemented, this will be needed before returning:
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| 396 | */
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| 397 | /* LDR R1, =GICI_BASE
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| 398 | LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
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| 399 | */
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| 400 | B .
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| 401 | .endfunc
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| 402 |
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| 403 | .extern SVC_Handler /* refer RTX function */
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| 404 |
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| 405 | IRQ_Handler:
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| 406 | .global IRQ_Handler
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| 407 | .func IRQ_Handler
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| 408 | .extern IRQCount
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| 409 | .extern IRQTable
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| 410 | .extern IRQNestLevel
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| 411 |
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| 412 | /* prologue */
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| 413 | SUB LR, LR, #4 /* Pre-adjust LR */
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| 414 | SRSDB SP!, #Mode_IRQ /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
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| 415 | CPS #Mode_IRQ /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
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| 416 | PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
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| 417 |
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| 418 | /* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
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| 419 | MOV R3, SP /* Ensure stack is 8-byte aligned */
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| 420 | AND R1, R3, #4
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| 421 | SUB SP, SP, R1 /* Adjust stack */
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| 422 | PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
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| 423 |
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| 424 | LDR R0, =IRQNestLevel /* Get address of nesting counter */
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| 425 | LDR R1, [R0]
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| 426 | ADD R1, R1, #1 /* Increment nesting counter */
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| 427 | STR R1, [R0]
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| 428 |
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| 429 | /* identify and acknowledge interrupt */
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| 430 | LDR R1, =GICI_BASE
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| 431 | LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
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| 432 | LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
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| 433 | DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
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| 434 |
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| 435 | /* Workaround GIC 390 errata 733075
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| 436 | * If the ID is not 0, then service the interrupt as normal.
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| 437 | * If the ID is 0 and active, then service interrupt ID 0 as normal.
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| 438 | * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
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| 439 | * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
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| 440 | */
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| 441 | LDR R2, =GICD_BASE
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| 442 | LDR R3, =GIC_ERRATA_CHECK_1
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| 443 | CMP R0, R3
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| 444 | BEQ unlock_cpu
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| 445 | LDR R3, =GIC_ERRATA_CHECK_2
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| 446 | CMP R0, R3
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| 447 | BEQ unlock_cpu
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| 448 | CMP R0, #0
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| 449 | BNE int_active /* If the ID is not 0, then service the interrupt */
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| 450 | LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
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| 451 | TST R3, #1
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| 452 | BNE int_active /* If active, then service the interrupt */
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| 453 | unlock_cpu:
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| 454 | LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
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| 455 | STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
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| 456 | DSB /* Ensure the write completes before continuing */
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| 457 | B ret_irq /* Do not service the spurious interrupt */
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| 458 | /* End workaround */
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| 459 |
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| 460 | int_active:
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| 461 | LDR R2, =IRQCount /* Read number of IRQs */
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| 462 | LDR R2, [R2]
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| 463 | CMP R0, R2 /* Clean up and return if no handler */
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| 464 | BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
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| 465 | LDR R2, =IRQTable /* Get address of handler */
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| 466 | LDR R2, [R2, R0, LSL #2]
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| 467 | CMP R2, #0 /* Clean up and return if handler address is 0 */
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| 468 | BEQ ret_irq
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| 469 | PUSH {R0,R1}
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| 470 |
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| 471 | CPSIE i /* Now safe to re-enable interrupts */
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| 472 | BLX R2 /* Call handler. R0 will be IRQ number */
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| 473 | CPSID i /* Disable interrupts again */
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| 474 |
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| 475 | /* write EOIR (GIC CPU Interface register) */
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| 476 | POP {R0,R1}
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| 477 | DSB /* Ensure that interrupt source is cleared before we write the EOIR */
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| 478 | ret_irq:
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| 479 | /* epilogue */
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| 480 | STR R0, [R1, #ICCEOIR_OFFSET]
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| 481 |
|
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| 482 | LDR R0, =IRQNestLevel /* Get address of nesting counter */
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| 483 | LDR R1, [R0]
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| 484 | SUB R1, R1, #1 /* Decrement nesting counter */
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| 485 | STR R1, [R0]
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| 486 |
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| 487 | POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
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| 488 | ADD SP, SP, R1 /* Unadjust stack */
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| 489 |
|
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| 490 | POP {R0-R3,R12} /* Restore stacked APCS registers */
|
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| 491 | RFEFD SP! /* Return from exception */
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| 492 | .endfunc
|
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| 493 |
|
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| 494 | /* Macro to define default handlers. Default handler
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| 495 | * will be weak symbol and just dead loops. They can be
|
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| 496 | * overwritten by other handlers */
|
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| 497 | .macro def_default_handler handler_name
|
---|
| 498 | .align 1
|
---|
| 499 | .thumb_func
|
---|
| 500 | .weak \handler_name
|
---|
| 501 | .type \handler_name, %function
|
---|
| 502 | \handler_name :
|
---|
| 503 | b .
|
---|
| 504 | .size \handler_name, . - \handler_name
|
---|
| 505 | .endm
|
---|
| 506 |
|
---|
| 507 | def_default_handler SVC_Handler
|
---|
| 508 |
|
---|
| 509 |
|
---|
| 510 | /* User Initial Stack & Heap */
|
---|
| 511 |
|
---|
| 512 | .ifdef __MICROLIB
|
---|
| 513 |
|
---|
| 514 | .global __initial_sp
|
---|
| 515 | .global __heap_base
|
---|
| 516 | .global __heap_limit
|
---|
| 517 |
|
---|
| 518 | .else
|
---|
| 519 |
|
---|
| 520 | .extern __use_two_region_memory
|
---|
| 521 | .global __user_initial_stackheap
|
---|
| 522 | __user_initial_stackheap:
|
---|
| 523 |
|
---|
| 524 | LDR R0, = __HeapBase
|
---|
| 525 | LDR R1, =(__StackTop)
|
---|
| 526 | LDR R2, = (__HeapBase + Heap_Size)
|
---|
| 527 | LDR R3, = (__StackTop - USR_Stack_Size)
|
---|
| 528 | BX LR
|
---|
| 529 |
|
---|
| 530 | .endif
|
---|
| 531 |
|
---|
| 532 |
|
---|
| 533 | .END
|
---|