1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer
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21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /**************************************************************************//**
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24 | * @file MBRZA1H.h
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25 | * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
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26 | * Renesas MBRZA1H Device Series
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27 | * @version
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28 | * @date 19 Sept 2013
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29 | *
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30 | * @note
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31 | *
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32 | ******************************************************************************/
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33 |
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34 | #ifndef __MBRZA1H_H__
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35 | #define __MBRZA1H_H__
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36 |
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37 | #ifdef __cplusplus
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38 | extern "C" {
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39 | #endif
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40 |
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41 |
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42 | /* ------------------------- Interrupt Number Definition ------------------------ */
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43 |
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44 | typedef enum IRQn
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45 | {
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46 | /****** SGI Interrupts Numbers ****************************************/
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47 | SGI0_IRQn = 0,
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48 | SGI1_IRQn = 1,
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49 | SGI2_IRQn = 2,
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50 | SGI3_IRQn = 3,
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51 | SGI4_IRQn = 4,
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52 | SGI5_IRQn = 5,
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53 | SGI6_IRQn = 6,
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54 | SGI7_IRQn = 7,
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55 | SGI8_IRQn = 8,
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56 | SGI9_IRQn = 9,
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57 | SGI10_IRQn = 10,
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58 | SGI11_IRQn = 11,
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59 | SGI12_IRQn = 12,
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60 | SGI13_IRQn = 13,
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61 | SGI14_IRQn = 14,
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62 | SGI15_IRQn = 15,
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63 |
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64 | /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
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65 | /* 16 - 578 */
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66 | PMUIRQ0_IRQn = 16,
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67 | COMMRX0_IRQn = 17,
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68 | COMMTX0_IRQn = 18,
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69 | CTIIRQ0_IRQn = 19,
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70 |
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71 | IRQ0_IRQn = 32,
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72 | IRQ1_IRQn = 33,
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73 | IRQ2_IRQn = 34,
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74 | IRQ3_IRQn = 35,
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75 | IRQ4_IRQn = 36,
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76 | IRQ5_IRQn = 37,
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77 | IRQ6_IRQn = 38,
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78 | IRQ7_IRQn = 39,
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79 |
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80 | PL310ERR_IRQn = 40,
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81 |
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82 | DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
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83 | DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
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84 | DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
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85 | DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
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86 | DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
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87 | DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
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88 | DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
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89 | DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
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90 | DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
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91 | DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
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92 | DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
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93 | DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
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94 | DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
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95 | DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
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96 | DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
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97 | DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
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98 | DMAERR_IRQn = 57, /*!< DMAC Interrupt */
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99 |
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100 | /* 58-72 Reserved */
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101 |
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102 | USBI0_IRQn = 73,
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103 | USBI1_IRQn = 74,
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104 |
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105 | S0_VI_VSYNC0_IRQn = 75,
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106 | S0_LO_VSYNC0_IRQn = 76,
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107 | S0_VSYNCERR0_IRQn = 77,
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108 | GR3_VLINE0_IRQn = 78,
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109 | S0_VFIELD0_IRQn = 79,
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110 | IV1_VBUFERR0_IRQn = 80,
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111 | IV3_VBUFERR0_IRQn = 81,
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112 | IV5_VBUFERR0_IRQn = 82,
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113 | IV6_VBUFERR0_IRQn = 83,
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114 | S0_WLINE0_IRQn = 84,
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115 | S1_VI_VSYNC0_IRQn = 85,
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116 | S1_LO_VSYNC0_IRQn = 86,
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117 | S1_VSYNCERR0_IRQn = 87,
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118 | S1_VFIELD0_IRQn = 88,
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119 | IV2_VBUFERR0_IRQn = 89,
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120 | IV4_VBUFERR0_IRQn = 90,
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121 | S1_WLINE0_IRQn = 91,
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122 | OIR_VI_VSYNC0_IRQn = 92,
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123 | OIR_LO_VSYNC0_IRQn = 93,
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124 | OIR_VSYNCERR0_IRQn = 94,
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125 | OIR_VFIELD0_IRQn = 95,
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126 | IV7_VBUFERR0_IRQn = 96,
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127 | IV8_VBUFERR0_IRQn = 97,
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128 | /* 98 Reserved */
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129 | S0_VI_VSYNC1_IRQn = 99,
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130 | S0_LO_VSYNC1_IRQn = 100,
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131 | S0_VSYNCERR1_IRQn = 101,
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132 | GR3_VLINE1_IRQn = 102,
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133 | S0_VFIELD1_IRQn = 103,
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134 | IV1_VBUFERR1_IRQn = 104,
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135 | IV3_VBUFERR1_IRQn = 105,
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136 | IV5_VBUFERR1_IRQn = 106,
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137 | IV6_VBUFERR1_IRQn = 107,
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138 | S0_WLINE1_IRQn = 108,
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139 | S1_VI_VSYNC1_IRQn = 109,
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140 | S1_LO_VSYNC1_IRQn = 110,
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141 | S1_VSYNCERR1_IRQn = 111,
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142 | S1_VFIELD1_IRQn = 112,
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143 | IV2_VBUFERR1_IRQn = 113,
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144 | IV4_VBUFERR1_IRQn = 114,
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145 | S1_WLINE1_IRQn = 115,
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146 | OIR_VI_VSYNC1_IRQn = 116,
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147 | OIR_LO_VSYNC1_IRQn = 117,
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148 | OIR_VSYNCERR1_IRQn = 118,
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149 | OIR_VFIELD1_IRQn = 119,
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150 | IV7_VBUFERR1_IRQn = 120,
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151 | IV8_VBUFERR1_IRQn = 121,
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152 | /* Reserved = 122 */
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153 |
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154 | IMRDI_IRQn = 123,
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155 | IMR2I0_IRQn = 124,
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156 | IMR2I1_IRQn = 125,
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157 |
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158 | JEDI_IRQn = 126,
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159 | JDTI_IRQn = 127,
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160 |
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161 | CMP0_IRQn = 128,
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162 | CMP1_IRQn = 129,
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163 |
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164 | INT0_IRQn = 130,
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165 | INT1_IRQn = 131,
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166 | INT2_IRQn = 132,
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167 | INT3_IRQn = 133,
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168 |
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169 | OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
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170 | OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
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171 |
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172 | CMI_IRQn = 136,
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173 | WTOUT_IRQn = 137,
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174 |
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175 | ITI_IRQn = 138,
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176 |
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177 | TGI0A_IRQn = 139,
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178 | TGI0B_IRQn = 140,
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179 | TGI0C_IRQn = 141,
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180 | TGI0D_IRQn = 142,
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181 | TGI0V_IRQn = 143,
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182 | TGI0E_IRQn = 144,
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183 | TGI0F_IRQn = 145,
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184 | TGI1A_IRQn = 146,
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185 | TGI1B_IRQn = 147,
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186 | TGI1V_IRQn = 148,
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187 | TGI1U_IRQn = 149,
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188 | TGI2A_IRQn = 150,
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189 | TGI2B_IRQn = 151,
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190 | TGI2V_IRQn = 152,
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191 | TGI2U_IRQn = 153,
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192 | TGI3A_IRQn = 154,
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193 | TGI3B_IRQn = 155,
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194 | TGI3C_IRQn = 156,
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195 | TGI3D_IRQn = 157,
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196 | TGI3V_IRQn = 158,
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197 | TGI4A_IRQn = 159,
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198 | TGI4B_IRQn = 160,
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199 | TGI4C_IRQn = 161,
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200 | TGI4D_IRQn = 162,
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201 | TGI4V_IRQn = 163,
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202 |
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203 | CMI1_IRQn = 164,
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204 | CMI2_IRQn = 165,
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205 |
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206 | SGDEI0_IRQn = 166,
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207 | SGDEI1_IRQn = 167,
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208 | SGDEI2_IRQn = 168,
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209 | SGDEI3_IRQn = 169,
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210 |
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211 | ADI_IRQn = 170,
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212 | LMTI_IRQn = 171,
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213 |
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214 | SSII0_IRQn = 172, /*!< SSIF Interrupt */
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215 | SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
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216 | SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
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217 | SSII1_IRQn = 175, /*!< SSIF Interrupt */
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218 | SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
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219 | SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
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220 | SSII2_IRQn = 178, /*!< SSIF Interrupt */
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221 | SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
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222 | SSII3_IRQn = 180, /*!< SSIF Interrupt */
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223 | SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
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224 | SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
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225 | SSII4_IRQn = 183, /*!< SSIF Interrupt */
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226 | SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
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227 | SSII5_IRQn = 185, /*!< SSIF Interrupt */
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228 | SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
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229 | SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
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230 |
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231 | SPDIFI_IRQn = 188,
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232 |
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233 | INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
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234 | INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
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235 | INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
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236 | INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
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237 | INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
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238 | INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
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239 | INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
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240 | INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
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241 | INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
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242 | INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
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243 | INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
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244 | INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
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245 | INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
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246 | INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
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247 | INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
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248 | INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
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249 | INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
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250 | INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
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251 | INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
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252 | INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
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253 | INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
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254 | INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
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255 | INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
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256 | INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
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257 | INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
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258 | INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
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259 | INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
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260 | INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
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261 | INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
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262 | INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
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263 | INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
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264 | INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
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265 |
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266 | SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
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267 | SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
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268 | SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
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269 | SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
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270 | SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
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271 | SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
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272 | SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
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273 | SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
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274 | SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
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275 | SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
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276 | SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
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277 | SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
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278 | SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
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279 | SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
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280 | SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
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281 | SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
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282 | SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
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283 | SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
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284 | SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
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285 | SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
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286 | SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
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287 | SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
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288 | SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
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289 | SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
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290 | SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
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291 | SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
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292 | SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
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293 | SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
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294 | SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
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295 | SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
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296 | SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
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297 | SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
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298 |
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299 | INTRCANGERR_IRQn = 253,
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300 | INTRCANGRECC_IRQn = 254,
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301 | INTRCAN0REC_IRQn = 255,
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302 | INTRCAN0ERR_IRQn = 256,
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303 | INTRCAN0TRX_IRQn = 257,
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304 | INTRCAN1REC_IRQn = 258,
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305 | INTRCAN1ERR_IRQn = 259,
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306 | INTRCAN1TRX_IRQn = 260,
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307 | INTRCAN2REC_IRQn = 261,
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308 | INTRCAN2ERR_IRQn = 262,
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309 | INTRCAN2TRX_IRQn = 263,
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310 | INTRCAN3REC_IRQn = 264,
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311 | INTRCAN3ERR_IRQn = 265,
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312 | INTRCAN3TRX_IRQn = 266,
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313 | INTRCAN4REC_IRQn = 267,
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314 | INTRCAN4ERR_IRQn = 268,
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315 | INTRCAN4TRX_IRQn = 269,
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316 |
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317 | RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
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318 | RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
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319 | RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
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320 | RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
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321 | RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
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322 | RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
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323 | RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
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324 | RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
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325 | RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
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326 | RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
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327 | RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
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328 | RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
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329 | RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
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330 | RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
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331 | RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
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332 |
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333 | IEBBTD_IRQn = 285,
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334 | IEBBTERR_IRQn = 286,
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335 | IEBBTSTA_IRQn = 287,
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336 | IEBBTV_IRQn = 288,
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337 |
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338 | ISY_IRQn = 289,
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339 | IERR_IRQn = 290,
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340 | ITARG_IRQn = 291,
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341 | ISEC_IRQn = 292,
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342 | IBUF_IRQn = 293,
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343 | IREADY_IRQn = 294,
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344 |
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345 | STERB_IRQn = 295,
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346 | FLTENDI_IRQn = 296,
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347 | FLTREQ0I_IRQn = 297,
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348 | FLTREQ1I_IRQn = 298,
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349 |
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350 | MMC0_IRQn = 299,
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351 | MMC1_IRQn = 300,
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352 | MMC2_IRQn = 301,
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353 |
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354 | SCHI0_3_IRQn = 302,
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355 | SDHI0_0_IRQn = 303,
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356 | SDHI0_1_IRQn = 304,
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357 | SCHI1_3_IRQn = 305,
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358 | SDHI1_0_IRQn = 306,
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359 | SDHI1_1_IRQn = 307,
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360 |
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361 | ARM_IRQn = 308,
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362 | PRD_IRQn = 309,
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363 | CUP_IRQn = 310,
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364 |
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365 | SCUAI0_IRQn = 311,
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366 | SCUAI1_IRQn = 312,
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367 | SCUFDI0_IRQn = 313,
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368 | SCUFDI1_IRQn = 314,
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369 | SCUFDI2_IRQn = 315,
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370 | SCUFDI3_IRQn = 316,
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371 | SCUFUI0_IRQn = 317,
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372 | SCUFUI1_IRQn = 318,
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373 | SCUFUI2_IRQn = 319,
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374 | SCUFUI3_IRQn = 320,
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375 | SCUDVI0_IRQn = 321,
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376 | SCUDVI1_IRQn = 322,
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377 | SCUDVI2_IRQn = 323,
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378 | SCUDVI3_IRQn = 324,
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379 |
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380 | MLB_CINT_IRQn = 325,
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381 | MLB_SINT_IRQn = 326,
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382 |
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383 | DRC10_IRQn = 327,
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384 | DRC11_IRQn = 328,
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385 |
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386 | /* 329-330 Reserved */
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387 |
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388 | LINI0_INT_T_IRQn = 331,
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389 | LINI0_INT_R_IRQn = 332,
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390 | LINI0_INT_S_IRQn = 333,
|
---|
391 | LINI0_INT_M_IRQn = 334,
|
---|
392 | LINI1_INT_T_IRQn = 335,
|
---|
393 | LINI1_INT_R_IRQn = 336,
|
---|
394 | LINI1_INT_S_IRQn = 337,
|
---|
395 | LINI1_INT_M_IRQn = 338,
|
---|
396 |
|
---|
397 | /* 339-346 Reserved */
|
---|
398 |
|
---|
399 | SCIERI0_IRQn = 347,
|
---|
400 | SCIRXI0_IRQn = 348,
|
---|
401 | SCITXI0_IRQn = 349,
|
---|
402 | SCITEI0_IRQn = 350,
|
---|
403 | SCIERI1_IRQn = 351,
|
---|
404 | SCIRXI1_IRQn = 352,
|
---|
405 | SCITXI1_IRQn = 353,
|
---|
406 | SCITEI1_IRQn = 354,
|
---|
407 |
|
---|
408 | AVBI_DATA = 355,
|
---|
409 | AVBI_ERROR = 356,
|
---|
410 | AVBI_MANAGE = 357,
|
---|
411 | AVBI_MAC = 358,
|
---|
412 |
|
---|
413 | ETHERI_IRQn = 359,
|
---|
414 |
|
---|
415 | /* 360-363 Reserved */
|
---|
416 |
|
---|
417 | CEUI_IRQn = 364,
|
---|
418 |
|
---|
419 | /* 365-380 Reserved */
|
---|
420 |
|
---|
421 |
|
---|
422 | H2XMLB_ERRINT_IRQn = 381,
|
---|
423 | H2XIC1_ERRINT_IRQn = 382,
|
---|
424 | X2HPERI1_ERRINT_IRQn = 383,
|
---|
425 | X2HPERR2_ERRINT_IRQn = 384,
|
---|
426 | X2HPERR34_ERRINT_IRQn= 385,
|
---|
427 | X2HPERR5_ERRINT_IRQn = 386,
|
---|
428 | X2HPERR67_ERRINT_IRQn= 387,
|
---|
429 | X2HDBGR_ERRINT_IRQn = 388,
|
---|
430 | X2HBSC_ERRINT_IRQn = 389,
|
---|
431 | X2HSPI1_ERRINT_IRQn = 390,
|
---|
432 | X2HSPI2_ERRINT_IRQn = 391,
|
---|
433 | PRRI_IRQn = 392,
|
---|
434 |
|
---|
435 | IFEI0_IRQn = 393,
|
---|
436 | OFFI0_IRQn = 394,
|
---|
437 | PFVEI0_IRQn = 395,
|
---|
438 | IFEI1_IRQn = 396,
|
---|
439 | OFFI1_IRQn = 397,
|
---|
440 | PFVEI1_IRQn = 398,
|
---|
441 |
|
---|
442 | /* 399-415 Reserved */
|
---|
443 | TINT0_IRQn = 416,
|
---|
444 | TINT1_IRQn = 417,
|
---|
445 | TINT2_IRQn = 418,
|
---|
446 | TINT3_IRQn = 419,
|
---|
447 | TINT4_IRQn = 420,
|
---|
448 | TINT5_IRQn = 421,
|
---|
449 | TINT6_IRQn = 422,
|
---|
450 | TINT7_IRQn = 423,
|
---|
451 | TINT8_IRQn = 424,
|
---|
452 | TINT9_IRQn = 425,
|
---|
453 | TINT10_IRQn = 426,
|
---|
454 | TINT11_IRQn = 427,
|
---|
455 | TINT12_IRQn = 428,
|
---|
456 | TINT13_IRQn = 429,
|
---|
457 | TINT14_IRQn = 430,
|
---|
458 | TINT15_IRQn = 431,
|
---|
459 | TINT16_IRQn = 432,
|
---|
460 | TINT17_IRQn = 433,
|
---|
461 | TINT18_IRQn = 434,
|
---|
462 | TINT19_IRQn = 435,
|
---|
463 | TINT20_IRQn = 436,
|
---|
464 | TINT21_IRQn = 437,
|
---|
465 | TINT22_IRQn = 438,
|
---|
466 | TINT23_IRQn = 439,
|
---|
467 | TINT24_IRQn = 440,
|
---|
468 | TINT25_IRQn = 441,
|
---|
469 | TINT26_IRQn = 442,
|
---|
470 | TINT27_IRQn = 443,
|
---|
471 | TINT28_IRQn = 444,
|
---|
472 | TINT29_IRQn = 445,
|
---|
473 | TINT30_IRQn = 446,
|
---|
474 | TINT31_IRQn = 447,
|
---|
475 | TINT32_IRQn = 448,
|
---|
476 | TINT33_IRQn = 449,
|
---|
477 | TINT34_IRQn = 450,
|
---|
478 | TINT35_IRQn = 451,
|
---|
479 | TINT36_IRQn = 452,
|
---|
480 | TINT37_IRQn = 453,
|
---|
481 | TINT38_IRQn = 454,
|
---|
482 | TINT39_IRQn = 455,
|
---|
483 | TINT40_IRQn = 456,
|
---|
484 | TINT41_IRQn = 457,
|
---|
485 | TINT42_IRQn = 458,
|
---|
486 | TINT43_IRQn = 459,
|
---|
487 | TINT44_IRQn = 460,
|
---|
488 | TINT45_IRQn = 461,
|
---|
489 | TINT46_IRQn = 462,
|
---|
490 | TINT47_IRQn = 463,
|
---|
491 | TINT48_IRQn = 464,
|
---|
492 | TINT49_IRQn = 465,
|
---|
493 | TINT50_IRQn = 466,
|
---|
494 | TINT51_IRQn = 467,
|
---|
495 | TINT52_IRQn = 468,
|
---|
496 | TINT53_IRQn = 469,
|
---|
497 | TINT54_IRQn = 470,
|
---|
498 | TINT55_IRQn = 471,
|
---|
499 | TINT56_IRQn = 472,
|
---|
500 | TINT57_IRQn = 473,
|
---|
501 | TINT58_IRQn = 474,
|
---|
502 | TINT59_IRQn = 475,
|
---|
503 | TINT60_IRQn = 476,
|
---|
504 | TINT61_IRQn = 477,
|
---|
505 | TINT62_IRQn = 478,
|
---|
506 | TINT63_IRQn = 479,
|
---|
507 | TINT64_IRQn = 480,
|
---|
508 | TINT65_IRQn = 481,
|
---|
509 | TINT66_IRQn = 482,
|
---|
510 | TINT67_IRQn = 483,
|
---|
511 | TINT68_IRQn = 484,
|
---|
512 | TINT69_IRQn = 485,
|
---|
513 | TINT70_IRQn = 486,
|
---|
514 | TINT71_IRQn = 487,
|
---|
515 | TINT72_IRQn = 488,
|
---|
516 | TINT73_IRQn = 489,
|
---|
517 | TINT74_IRQn = 490,
|
---|
518 | TINT75_IRQn = 491,
|
---|
519 | TINT76_IRQn = 492,
|
---|
520 | TINT77_IRQn = 493,
|
---|
521 | TINT78_IRQn = 494,
|
---|
522 | TINT79_IRQn = 495,
|
---|
523 | TINT80_IRQn = 496,
|
---|
524 | TINT81_IRQn = 497,
|
---|
525 | TINT82_IRQn = 498,
|
---|
526 | TINT83_IRQn = 499,
|
---|
527 | TINT84_IRQn = 500,
|
---|
528 | TINT85_IRQn = 501,
|
---|
529 | TINT86_IRQn = 502,
|
---|
530 | TINT87_IRQn = 503,
|
---|
531 | TINT88_IRQn = 504,
|
---|
532 | TINT89_IRQn = 505,
|
---|
533 | TINT90_IRQn = 506,
|
---|
534 | TINT91_IRQn = 507,
|
---|
535 | TINT92_IRQn = 508,
|
---|
536 | TINT93_IRQn = 509,
|
---|
537 | TINT94_IRQn = 510,
|
---|
538 | TINT95_IRQn = 511,
|
---|
539 | TINT96_IRQn = 512,
|
---|
540 | TINT97_IRQn = 513,
|
---|
541 | TINT98_IRQn = 514,
|
---|
542 | TINT99_IRQn = 515,
|
---|
543 | TINT100_IRQn = 516,
|
---|
544 | TINT101_IRQn = 517,
|
---|
545 | TINT102_IRQn = 518,
|
---|
546 | TINT103_IRQn = 519,
|
---|
547 | TINT104_IRQn = 520,
|
---|
548 | TINT105_IRQn = 521,
|
---|
549 | TINT106_IRQn = 522,
|
---|
550 | TINT107_IRQn = 523,
|
---|
551 | TINT108_IRQn = 524,
|
---|
552 | TINT109_IRQn = 525,
|
---|
553 | TINT110_IRQn = 526,
|
---|
554 | TINT111_IRQn = 527,
|
---|
555 | TINT112_IRQn = 528,
|
---|
556 | TINT113_IRQn = 529,
|
---|
557 | TINT114_IRQn = 530,
|
---|
558 | TINT115_IRQn = 531,
|
---|
559 | TINT116_IRQn = 532,
|
---|
560 | TINT117_IRQn = 533,
|
---|
561 | TINT118_IRQn = 534,
|
---|
562 | TINT119_IRQn = 535,
|
---|
563 | TINT120_IRQn = 536,
|
---|
564 | TINT121_IRQn = 537,
|
---|
565 | TINT122_IRQn = 538,
|
---|
566 | TINT123_IRQn = 539,
|
---|
567 | TINT124_IRQn = 540,
|
---|
568 | TINT125_IRQn = 541,
|
---|
569 | TINT126_IRQn = 542,
|
---|
570 | TINT127_IRQn = 543,
|
---|
571 | TINT128_IRQn = 544,
|
---|
572 | TINT129_IRQn = 545,
|
---|
573 | TINT130_IRQn = 546,
|
---|
574 | TINT131_IRQn = 547,
|
---|
575 | TINT132_IRQn = 548,
|
---|
576 | TINT133_IRQn = 549,
|
---|
577 | TINT134_IRQn = 550,
|
---|
578 | TINT135_IRQn = 551,
|
---|
579 | TINT136_IRQn = 552,
|
---|
580 | TINT137_IRQn = 553,
|
---|
581 | TINT138_IRQn = 554,
|
---|
582 | TINT139_IRQn = 555,
|
---|
583 | TINT140_IRQn = 556,
|
---|
584 | TINT141_IRQn = 557,
|
---|
585 | TINT142_IRQn = 558,
|
---|
586 | TINT143_IRQn = 559,
|
---|
587 | TINT144_IRQn = 560,
|
---|
588 | TINT145_IRQn = 561,
|
---|
589 | TINT146_IRQn = 562,
|
---|
590 | TINT147_IRQn = 563,
|
---|
591 | TINT148_IRQn = 564,
|
---|
592 | TINT149_IRQn = 565,
|
---|
593 | TINT150_IRQn = 566,
|
---|
594 | TINT151_IRQn = 567,
|
---|
595 | TINT152_IRQn = 568,
|
---|
596 | TINT153_IRQn = 569,
|
---|
597 | TINT154_IRQn = 570,
|
---|
598 | TINT155_IRQn = 571,
|
---|
599 | TINT156_IRQn = 572,
|
---|
600 | TINT157_IRQn = 573,
|
---|
601 | TINT158_IRQn = 574,
|
---|
602 | TINT159_IRQn = 575,
|
---|
603 | TINT160_IRQn = 576,
|
---|
604 | TINT161_IRQn = 577,
|
---|
605 | TINT162_IRQn = 578,
|
---|
606 | TINT163_IRQn = 579,
|
---|
607 | TINT164_IRQn = 580,
|
---|
608 | TINT165_IRQn = 581,
|
---|
609 | TINT166_IRQn = 582,
|
---|
610 | TINT167_IRQn = 583,
|
---|
611 | TINT168_IRQn = 584,
|
---|
612 | TINT169_IRQn = 585,
|
---|
613 | TINT170_IRQn = 586
|
---|
614 |
|
---|
615 | } IRQn_Type;
|
---|
616 |
|
---|
617 | #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
|
---|
618 |
|
---|
619 | /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
|
---|
620 | #define __CA9_REV 0x0000 /*!< Core revision r0 */
|
---|
621 |
|
---|
622 | #define __MPU_PRESENT 1 /*!< MPU present or not */
|
---|
623 |
|
---|
624 | #define __FPU_PRESENT 1 /*!< FPU present or not */
|
---|
625 |
|
---|
626 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
|
---|
627 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
---|
628 |
|
---|
629 | #include <core_ca9.h>
|
---|
630 | #include "system_MBRZA1H.h"
|
---|
631 |
|
---|
632 |
|
---|
633 | /******************************************************************************/
|
---|
634 | /* Device Specific Peripheral Section */
|
---|
635 | /******************************************************************************/
|
---|
636 | /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
|
---|
637 | Renesas_RZ_A1 Device Specific Peripheral registers structures
|
---|
638 | @{
|
---|
639 | */
|
---|
640 |
|
---|
641 | #if defined ( __CC_ARM )
|
---|
642 | #pragma anon_unions
|
---|
643 | #endif
|
---|
644 |
|
---|
645 | #include "pl310.h"
|
---|
646 | #include "gic.h"
|
---|
647 | #include "nvic_wrapper.h"
|
---|
648 | #include "cmsis_nvic.h"
|
---|
649 |
|
---|
650 | #include "ostm_iodefine.h"
|
---|
651 | #include "gpio_iodefine.h"
|
---|
652 | #include "cpg_iodefine.h"
|
---|
653 | #include "l2c_iodefine.h"
|
---|
654 |
|
---|
655 | #if defined ( __CC_ARM )
|
---|
656 | #pragma no_anon_unions
|
---|
657 | #endif
|
---|
658 |
|
---|
659 | /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
|
---|
660 |
|
---|
661 |
|
---|
662 | /******************************************************************************/
|
---|
663 | /* Peripheral memory map */
|
---|
664 | /******************************************************************************/
|
---|
665 | /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
|
---|
666 | @{
|
---|
667 | */
|
---|
668 |
|
---|
669 | /* R7S72100 CPU board */
|
---|
670 | #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
|
---|
671 | #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
|
---|
672 | #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
|
---|
673 | #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
|
---|
674 | #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
|
---|
675 | #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
|
---|
676 | #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
|
---|
677 | #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
|
---|
678 | #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
|
---|
679 | #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
|
---|
680 | #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
|
---|
681 | #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
|
---|
682 | #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
|
---|
683 | #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
|
---|
684 | #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
|
---|
685 | #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
|
---|
686 | #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
|
---|
687 |
|
---|
688 | //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
|
---|
689 | //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
|
---|
690 | #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
691 | region.domain = 0x0; \
|
---|
692 | region.e_t = ECC_DISABLED; \
|
---|
693 | region.g_t = GLOBAL; \
|
---|
694 | region.inner_norm_t = WB_WA; \
|
---|
695 | region.outer_norm_t = WB_WA; \
|
---|
696 | region.mem_t = NORMAL; \
|
---|
697 | region.sec_t = NON_SECURE; \
|
---|
698 | region.xn_t = EXECUTE; \
|
---|
699 | region.priv_t = RW; \
|
---|
700 | region.user_t = RW; \
|
---|
701 | region.sh_t = NON_SHARED; \
|
---|
702 | __get_section_descriptor(&descriptor_l1, region);
|
---|
703 |
|
---|
704 | #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
705 | region.domain = 0x0; \
|
---|
706 | region.e_t = ECC_DISABLED; \
|
---|
707 | region.g_t = GLOBAL; \
|
---|
708 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
709 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
710 | region.mem_t = NORMAL; \
|
---|
711 | region.sec_t = SECURE; \
|
---|
712 | region.xn_t = EXECUTE; \
|
---|
713 | region.priv_t = RW; \
|
---|
714 | region.user_t = RW; \
|
---|
715 | region.sh_t = NON_SHARED; \
|
---|
716 | __get_section_descriptor(&descriptor_l1, region);
|
---|
717 |
|
---|
718 | //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
|
---|
719 | #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
720 | region.domain = 0x0; \
|
---|
721 | region.e_t = ECC_DISABLED; \
|
---|
722 | region.g_t = GLOBAL; \
|
---|
723 | region.inner_norm_t = WB_WA; \
|
---|
724 | region.outer_norm_t = WB_WA; \
|
---|
725 | region.mem_t = NORMAL; \
|
---|
726 | region.sec_t = NON_SECURE; \
|
---|
727 | region.xn_t = EXECUTE; \
|
---|
728 | region.priv_t = READ; \
|
---|
729 | region.user_t = READ; \
|
---|
730 | region.sh_t = NON_SHARED; \
|
---|
731 | __get_section_descriptor(&descriptor_l1, region);
|
---|
732 |
|
---|
733 | //Sect_Normal_RO. Sect_Normal_Cod, but not executable
|
---|
734 | #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
735 | region.domain = 0x0; \
|
---|
736 | region.e_t = ECC_DISABLED; \
|
---|
737 | region.g_t = GLOBAL; \
|
---|
738 | region.inner_norm_t = WB_WA; \
|
---|
739 | region.outer_norm_t = WB_WA; \
|
---|
740 | region.mem_t = NORMAL; \
|
---|
741 | region.sec_t = NON_SECURE; \
|
---|
742 | region.xn_t = NON_EXECUTE; \
|
---|
743 | region.priv_t = READ; \
|
---|
744 | region.user_t = READ; \
|
---|
745 | region.sh_t = NON_SHARED; \
|
---|
746 | __get_section_descriptor(&descriptor_l1, region);
|
---|
747 |
|
---|
748 | //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
|
---|
749 | #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
750 | region.domain = 0x0; \
|
---|
751 | region.e_t = ECC_DISABLED; \
|
---|
752 | region.g_t = GLOBAL; \
|
---|
753 | region.inner_norm_t = WB_WA; \
|
---|
754 | region.outer_norm_t = WB_WA; \
|
---|
755 | region.mem_t = NORMAL; \
|
---|
756 | region.sec_t = NON_SECURE; \
|
---|
757 | region.xn_t = NON_EXECUTE; \
|
---|
758 | region.priv_t = RW; \
|
---|
759 | region.user_t = RW; \
|
---|
760 | region.sh_t = NON_SHARED; \
|
---|
761 | __get_section_descriptor(&descriptor_l1, region);
|
---|
762 | //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
|
---|
763 | #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
764 | region.domain = 0x0; \
|
---|
765 | region.e_t = ECC_DISABLED; \
|
---|
766 | region.g_t = GLOBAL; \
|
---|
767 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
768 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
769 | region.mem_t = STRONGLY_ORDERED; \
|
---|
770 | region.sec_t = SECURE; \
|
---|
771 | region.xn_t = NON_EXECUTE; \
|
---|
772 | region.priv_t = RW; \
|
---|
773 | region.user_t = RW; \
|
---|
774 | region.sh_t = NON_SHARED; \
|
---|
775 | __get_section_descriptor(&descriptor_l1, region);
|
---|
776 |
|
---|
777 | //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
|
---|
778 | #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
779 | region.domain = 0x0; \
|
---|
780 | region.e_t = ECC_DISABLED; \
|
---|
781 | region.g_t = GLOBAL; \
|
---|
782 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
783 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
784 | region.mem_t = STRONGLY_ORDERED; \
|
---|
785 | region.sec_t = SECURE; \
|
---|
786 | region.xn_t = NON_EXECUTE; \
|
---|
787 | region.priv_t = READ; \
|
---|
788 | region.user_t = READ; \
|
---|
789 | region.sh_t = NON_SHARED; \
|
---|
790 | __get_section_descriptor(&descriptor_l1, region);
|
---|
791 |
|
---|
792 | //Sect_Device_RW. Sect_Device_RO, but writeable
|
---|
793 | #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
|
---|
794 | region.domain = 0x0; \
|
---|
795 | region.e_t = ECC_DISABLED; \
|
---|
796 | region.g_t = GLOBAL; \
|
---|
797 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
798 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
799 | region.mem_t = STRONGLY_ORDERED; \
|
---|
800 | region.sec_t = SECURE; \
|
---|
801 | region.xn_t = NON_EXECUTE; \
|
---|
802 | region.priv_t = RW; \
|
---|
803 | region.user_t = RW; \
|
---|
804 | region.sh_t = NON_SHARED; \
|
---|
805 | __get_section_descriptor(&descriptor_l1, region);
|
---|
806 | //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
|
---|
807 | #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
|
---|
808 | region.domain = 0x0; \
|
---|
809 | region.e_t = ECC_DISABLED; \
|
---|
810 | region.g_t = GLOBAL; \
|
---|
811 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
812 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
813 | region.mem_t = SHARED_DEVICE; \
|
---|
814 | region.sec_t = SECURE; \
|
---|
815 | region.xn_t = NON_EXECUTE; \
|
---|
816 | region.priv_t = RW; \
|
---|
817 | region.user_t = RW; \
|
---|
818 | region.sh_t = NON_SHARED; \
|
---|
819 | __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
|
---|
820 |
|
---|
821 | //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
|
---|
822 | #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
|
---|
823 | region.domain = 0x0; \
|
---|
824 | region.e_t = ECC_DISABLED; \
|
---|
825 | region.g_t = GLOBAL; \
|
---|
826 | region.inner_norm_t = NON_CACHEABLE; \
|
---|
827 | region.outer_norm_t = NON_CACHEABLE; \
|
---|
828 | region.mem_t = SHARED_DEVICE; \
|
---|
829 | region.sec_t = SECURE; \
|
---|
830 | region.xn_t = NON_EXECUTE; \
|
---|
831 | region.priv_t = RW; \
|
---|
832 | region.user_t = RW; \
|
---|
833 | region.sh_t = NON_SHARED; \
|
---|
834 | __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
|
---|
835 |
|
---|
836 | /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
|
---|
837 |
|
---|
838 | /******************************************************************************/
|
---|
839 | /* Clock Settings */
|
---|
840 | /******************************************************************************/
|
---|
841 | /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
|
---|
842 | @{
|
---|
843 | */
|
---|
844 |
|
---|
845 | /*
|
---|
846 | * Clock Mode 0 settings
|
---|
847 | * SW1-4(MD_CLK):ON
|
---|
848 | * SW1-5(MD_CLKS):ON
|
---|
849 | * FRQCR=0x1035
|
---|
850 | * CLKEN2 = 0b - unstable
|
---|
851 | * CLKEN[1:0]=01b - Output, Low, Low
|
---|
852 | * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
|
---|
853 | * FRQCR2=0x0001
|
---|
854 | * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
|
---|
855 | */
|
---|
856 | #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
|
---|
857 | #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
|
---|
858 | #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
|
---|
859 | #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
|
---|
860 | #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
|
---|
861 | #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
|
---|
862 | #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
|
---|
863 |
|
---|
864 | /*
|
---|
865 | * Clock Mode 1 settings
|
---|
866 | * SW1-4(MD_CLK):OFF
|
---|
867 | * SW1-5(MD_CLKS):ON
|
---|
868 | * FRQCR=0x1335
|
---|
869 | * CLKEN2 = 0b - unstable
|
---|
870 | * CLKEN[1:0]=01b - Output, Low, Low
|
---|
871 | * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
|
---|
872 | * FRQCR2=0x0003
|
---|
873 | * GFC[1:0] =11b - graphic clock is 1/3 bus clock
|
---|
874 | */
|
---|
875 | #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
|
---|
876 | #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
|
---|
877 | #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
|
---|
878 | #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
|
---|
879 | #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
|
---|
880 | #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
|
---|
881 | #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
|
---|
882 |
|
---|
883 | /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
|
---|
884 |
|
---|
885 | /******************************************************************************/
|
---|
886 | /* CPG Settings */
|
---|
887 | /******************************************************************************/
|
---|
888 | /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
|
---|
889 | @{
|
---|
890 | */
|
---|
891 |
|
---|
892 | #define CPG_FRQCR_SHIFT_CKOEN2 (14)
|
---|
893 | #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
|
---|
894 | #define CPG_FRQCR_SHIFT_CKOEN0 (12)
|
---|
895 | #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
|
---|
896 | #define CPG_FRQCR_SHIFT_IFC (8)
|
---|
897 | #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
|
---|
898 |
|
---|
899 | #define CPG_FRQCR2_SHIFT_GFC (0)
|
---|
900 | #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
|
---|
901 |
|
---|
902 |
|
---|
903 | #define CPG_STBCR1_BIT_STBY (0x80u)
|
---|
904 | #define CPG_STBCR1_BIT_DEEP (0x40u)
|
---|
905 | #define CPG_STBCR2_BIT_HIZ (0x80u)
|
---|
906 | #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
|
---|
907 | #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
|
---|
908 | #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
|
---|
909 | #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
|
---|
910 | #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
|
---|
911 | #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
|
---|
912 | #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
|
---|
913 | #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
|
---|
914 | #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
|
---|
915 | #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
|
---|
916 | #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
|
---|
917 | #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
|
---|
918 | #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
|
---|
919 | #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
|
---|
920 | #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
|
---|
921 | #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
|
---|
922 | #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
|
---|
923 | #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
|
---|
924 | #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
|
---|
925 | #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
|
---|
926 | #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
|
---|
927 | #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
|
---|
928 | #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
|
---|
929 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
|
---|
930 | #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
|
---|
931 | #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
|
---|
932 | #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
|
---|
933 | #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
|
---|
934 | #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
|
---|
935 | #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
|
---|
936 | #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
|
---|
937 | #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
|
---|
938 | #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
|
---|
939 | #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
|
---|
940 | #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
|
---|
941 | #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
|
---|
942 | #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
|
---|
943 | #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
|
---|
944 | #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
|
---|
945 | #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
|
---|
946 | #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
|
---|
947 | #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
|
---|
948 | #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
|
---|
949 | #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
|
---|
950 | #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
|
---|
951 | #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
|
---|
952 | #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
|
---|
953 | #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
|
---|
954 | #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
|
---|
955 | #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
|
---|
956 | #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
|
---|
957 | #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
|
---|
958 | #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
|
---|
959 | #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
|
---|
960 | #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
|
---|
961 | #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
|
---|
962 | #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
|
---|
963 | #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
|
---|
964 | #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
|
---|
965 | #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
|
---|
966 | #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
|
---|
967 | #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
|
---|
968 | #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
|
---|
969 | #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
|
---|
970 | #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
|
---|
971 | #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
|
---|
972 | #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
|
---|
973 | #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
|
---|
974 | #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
|
---|
975 | #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
|
---|
976 | #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
|
---|
977 | #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
|
---|
978 | #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
|
---|
979 | #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
|
---|
980 | #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
|
---|
981 | #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
|
---|
982 | #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
|
---|
983 | #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
|
---|
984 | #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
|
---|
985 | #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
|
---|
986 | #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
|
---|
987 | #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
|
---|
988 | #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
|
---|
989 | #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
|
---|
990 | #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
|
---|
991 | #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
|
---|
992 | #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
|
---|
993 | #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
|
---|
994 | #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
|
---|
995 | #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
|
---|
996 | #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
|
---|
997 | #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
|
---|
998 | #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
|
---|
999 | #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
|
---|
1000 | #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
|
---|
1001 | #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
|
---|
1002 | #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
|
---|
1003 | #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
|
---|
1004 | #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
|
---|
1005 | #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
|
---|
1006 | #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
|
---|
1007 | #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
|
---|
1008 | #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
|
---|
1009 | #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
|
---|
1010 | #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
|
---|
1011 | #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
|
---|
1012 | #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
|
---|
1013 |
|
---|
1014 | /*@}*/ /* end of group Renesas_RZ_A1_CPG */
|
---|
1015 |
|
---|
1016 | /******************************************************************************/
|
---|
1017 | /* GPIO Settings */
|
---|
1018 | /******************************************************************************/
|
---|
1019 | /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
|
---|
1020 | @{
|
---|
1021 | */
|
---|
1022 |
|
---|
1023 | #define GPIO_BIT_N0 (1u << 0)
|
---|
1024 | #define GPIO_BIT_N1 (1u << 1)
|
---|
1025 | #define GPIO_BIT_N2 (1u << 2)
|
---|
1026 | #define GPIO_BIT_N3 (1u << 3)
|
---|
1027 | #define GPIO_BIT_N4 (1u << 4)
|
---|
1028 | #define GPIO_BIT_N5 (1u << 5)
|
---|
1029 | #define GPIO_BIT_N6 (1u << 6)
|
---|
1030 | #define GPIO_BIT_N7 (1u << 7)
|
---|
1031 | #define GPIO_BIT_N8 (1u << 8)
|
---|
1032 | #define GPIO_BIT_N9 (1u << 9)
|
---|
1033 | #define GPIO_BIT_N10 (1u << 10)
|
---|
1034 | #define GPIO_BIT_N11 (1u << 11)
|
---|
1035 | #define GPIO_BIT_N12 (1u << 12)
|
---|
1036 | #define GPIO_BIT_N13 (1u << 13)
|
---|
1037 | #define GPIO_BIT_N14 (1u << 14)
|
---|
1038 | #define GPIO_BIT_N15 (1u << 15)
|
---|
1039 |
|
---|
1040 |
|
---|
1041 | #define MD_BOOT10_MASK (0x3)
|
---|
1042 |
|
---|
1043 | #define MD_BOOT10_BM0 (0x0)
|
---|
1044 | #define MD_BOOT10_BM1 (0x2)
|
---|
1045 | #define MD_BOOT10_BM3 (0x1)
|
---|
1046 | #define MD_BOOT10_BM4_5 (0x3)
|
---|
1047 |
|
---|
1048 | #define MD_CLK (1u << 2)
|
---|
1049 | #define MD_CLKS (1u << 3)
|
---|
1050 |
|
---|
1051 | /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
|
---|
1052 |
|
---|
1053 | #ifdef __cplusplus
|
---|
1054 | }
|
---|
1055 | #endif
|
---|
1056 |
|
---|
1057 | #endif // __MBRZA1H_H__
|
---|