source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/ethernet_api.c@ 439

Last change on this file since 439 was 439, checked in by coas-nagasima, 4 years ago

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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include <string.h>
17#include "ethernet_api.h"
18#include "cmsis.h"
19#include "mbed_interface.h"
20#include "mbed_toolchain.h"
21#include "mbed_error.h"
22#include "iodefine.h"
23#include "ethernetext_api.h"
24
25#if DEVICE_ETHERNET
26
27/* Descriptor info */
28#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
29#define MAX_SEND_SIZE (1514)
30/* Ethernet Descriptor Value Define */
31#define TD0_TFP_TOP_BOTTOM (0x30000000)
32#define TD0_TACT (0x80000000)
33#define TD0_TDLE (0x40000000)
34#define RD0_RACT (0x80000000)
35#define RD0_RDLE (0x40000000)
36#define RD0_RFE (0x08000000)
37#define RD0_RCSE (0x04000000)
38#define RD0_RFS (0x03FF0000)
39#define RD0_RCS (0x0000FFFF)
40#define RD0_RFS_RFOF (0x02000000)
41#define RD0_RFS_RUAF (0x00400000)
42#define RD0_RFS_RRF (0x00100000)
43#define RD0_RFS_RTLF (0x00080000)
44#define RD0_RFS_RTSF (0x00040000)
45#define RD0_RFS_PRE (0x00020000)
46#define RD0_RFS_CERF (0x00010000)
47#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
48 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
49#define RD1_RDL_MSK (0x0000FFFF)
50/* PHY Register */
51#define BASIC_MODE_CONTROL_REG (0)
52#define BASIC_MODE_STATUS_REG (1)
53#define PHY_IDENTIFIER1_REG (2)
54#define PHY_IDENTIFIER2_REG (3)
55#define PHY_SP_CTL_STS_REG (31)
56/* MII management interface access */
57#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
58#define PHY_ST (1)
59#define PHY_WRITE (1)
60#define PHY_READ (2)
61#define MDC_WAIT (6) /* 400ns/4 */
62#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
63#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
64#define M_PHY_ID (0xFFFFFFF0)
65#define PHY_ID_LAN8710A (0x0007C0F0)
66/* ETHERPIR0 */
67#define PIR0_MDI (0x00000008)
68#define PIR0_MDO (0x00000004)
69#define PIR0_MMD (0x00000002)
70#define PIR0_MDC (0x00000001)
71#define PIR0_MDC_HIGH (0x00000001)
72#define PIR0_MDC_LOW (0x00000000)
73/* ETHEREDRRR0 */
74#define EDRRR0_RR (0x00000001)
75/* ETHEREDTRR0 */
76#define EDTRR0_TR (0x00000003)
77/* software wait */
78#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
79
80#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
81 /* 0x00040000 : Detect frame reception */
82 /* 0x00010000 : Receive FIFO overflow */
83 /* 0x00000010 : Residual bit frame reception */
84 /* 0x00000008 : Long frame reception */
85 /* 0x00000004 : Short frame reception */
86 /* 0x00000002 : PHY-LSI reception error */
87 /* 0x00000001 : Receive frame CRC error */
88#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
89
90void ethernet_address(char *);
91void ethernet_set_link(int, int);
92
93
94/* Send descriptor */
95typedef struct tag_edmac_send_desc {
96 uint32_t td0;
97 uint32_t td1;
98 uint8_t *td2;
99 uint32_t padding4;
100} edmac_send_desc_t;
101
102/* Receive descriptor */
103typedef struct tag_edmac_recv_desc {
104 uint32_t rd0;
105 uint32_t rd1;
106 uint8_t *rd2;
107 uint32_t padding4;
108} edmac_recv_desc_t;
109
110/* memory */
111/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
112/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
113#if defined(__ICCARM__)
114#pragma data_alignment=16
115static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
116 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
117 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
118 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
119 @ ".mirrorram";
120#else
121static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
122 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
123 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
124 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
125 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
126#endif
127static int32_t rx_read_offset; /* read offset */
128static int32_t tx_wite_offset; /* write offset */
129static uint32_t send_top_index;
130static uint32_t recv_top_index;
131static int32_t Interrupt_priority;
132static edmac_send_desc_t *p_eth_desc_dsend = NULL;
133static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
134static edmac_recv_desc_t *p_recv_end_desc = NULL;
135static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
136static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
137static uint32_t phy_id = 0;
138static uint32_t start_stop = 1; /* 0:stop 1:start */
139static uint32_t tsu_ten_tmp = 0;
140
141volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
142 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
143 ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
144 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
145
146/* function */
147static void lan_reg_reset(void);
148static void lan_desc_create(void);
149static void lan_reg_set(int32_t link);
150static uint16_t phy_reg_read(uint16_t reg_addr);
151static void phy_reg_write(uint16_t reg_addr, uint16_t data);
152static void mii_preamble(void);
153static void mii_cmd(uint16_t reg_addr, uint32_t option);
154static void mii_reg_read(uint16_t *data);
155static void mii_reg_write(uint16_t data);
156static void mii_z(void);
157static void mii_write_1(void);
158static void mii_write_0(void);
159static void set_ether_pir(uint32_t set_data);
160static void wait_100us(int32_t wait_cnt);
161
162
163int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
164 int32_t i;
165 uint16_t val;
166
167 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
168
169 /* P4_2(PHY Reset) */
170 GPIOP4 &= ~0x0004; /* Outputs low level */
171 GPIOPMC4 &= ~0x0004; /* Port mode */
172 GPIOPM4 &= ~0x0004; /* Output mode */
173
174 /* GPIO P1 P1_14(ET_COL) */
175 GPIOPMC1 |= 0x4000;
176 GPIOPFCAE1 &= ~0x4000;
177 GPIOPFCE1 |= 0x4000;
178 GPIOPFC1 |= 0x4000;
179
180 /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
181 GPIOPMC3 |= 0x0079;
182 GPIOPFCAE3 &= ~0x0079;
183 GPIOPFCE3 &= ~0x0079;
184 GPIOPFC3 |= 0x0079;
185 GPIOPIPC3 |= 0x0079;
186
187 /* P5_9(ET_MDC) */
188 GPIOPMC5 |= 0x0200;
189 GPIOPFCAE5 &= ~0x0200;
190 GPIOPFCE5 &= ~0x0200;
191 GPIOPFC5 |= 0x0200;
192 GPIOPIPC5 |= 0x0200;
193
194 /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
195 /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
196 GPIOPMC10 |= 0x0FFE;
197 GPIOPFCAE10 &= ~0x0FFE;
198 GPIOPFCE10 |= 0x0FFE;
199 GPIOPFC10 |= 0x0FFE;
200 GPIOPIPC10 |= 0x0FFE;
201
202 /* Resets the E-MAC,E-DMAC */
203 lan_reg_reset();
204
205 /* PHY Reset */
206 GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
207 wait_100us(250); /* 25msec */
208 GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
209 wait_100us(100); /* 10msec */
210
211 /* Resets the PHY-LSI */
212 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
213 for (i = 10000; i > 0; i--) {
214 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
215 if (((uint32_t)val & 0x8000uL) == 0) {
216 break; /* Reset complete */
217 }
218 }
219
220 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
221 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
222
223 Interrupt_priority = p_ethcfg->int_priority;
224 p_recv_cb_fnc = p_ethcfg->recv_cb;
225 start_stop = 1;
226
227 if (p_ethcfg->ether_mac != NULL) {
228 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
229 } else {
230 ethernet_address(mac_addr); /* Get MAC Address */
231 }
232
233 return 0;
234}
235
236void ethernetext_start_stop(int32_t mode) {
237 if (mode == 1) {
238 /* start */
239 ETHEREDTRR0 |= EDTRR0_TR;
240 ETHEREDRRR0 |= EDRRR0_RR;
241 start_stop = 1;
242 } else {
243 /* stop */
244 ETHEREDTRR0 &= ~EDTRR0_TR;
245 ETHEREDRRR0 &= ~EDRRR0_RR;
246 start_stop = 0;
247 }
248}
249
250int ethernetext_chk_link_mode(void) {
251 int32_t link;
252 uint16_t data;
253
254 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
255 data = phy_reg_read(PHY_SP_CTL_STS_REG);
256 switch (((uint32_t)data >> 2) & 0x00000007) {
257 case 0x0001:
258 link = HALF_10M;
259 break;
260 case 0x0005:
261 link = FULL_10M;
262 break;
263 case 0x0002:
264 link = HALF_TX;
265 break;
266 case 0x0006:
267 link = FULL_TX;
268 break;
269 default:
270 link = NEGO_FAIL;
271 break;
272 }
273 } else {
274 link = NEGO_FAIL;
275 }
276
277 /* Promiscuous Mode */
278 if (ETHERECMR0 & 0x00000001)
279 link |= PROMISCUOUS_MODE;
280
281 return link;
282}
283
284void ethernetext_set_link_mode(int32_t link) {
285 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
286 lan_desc_create(); /* Initialize of buffer memory */
287 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
288}
289
290void ethernetext_add_multicast_group(const uint8_t *addr) {
291 uint32_t cnt;
292 uint32_t tmp_data_h;
293 uint32_t tmp_data_l;
294
295 if (tsu_ten_tmp == 0xFFFFFFFF) {
296 ethernetext_set_all_multicast(1);
297 } else {
298 tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
299 tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
300
301 for (cnt = 0; cnt < 32; cnt++) {
302 if ((tsu_ten_tmp & (0x80000000 >> cnt)) == 0) {
303 while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
304 ;
305 }
306 ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = tmp_data_h;
307 while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
308 ;
309 }
310 ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = tmp_data_l;
311 if ((ETHERECMR0 & 0x00002000) != 0) {
312 ETHERTSU_TEN |= (0x80000000 >> cnt);
313 }
314 tsu_ten_tmp |= (0x80000000 >> cnt);
315 break;
316 }
317 }
318 }
319}
320
321void ethernetext_remove_multicast_group(const uint8_t *addr) {
322 uint32_t cnt;
323 uint32_t tmp_data_h;
324 uint32_t tmp_data_l;
325
326 tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]);
327 tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]);
328
329 for (cnt = 0; cnt< 32; cnt++) {
330 if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) &&
331 (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) {
332 while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
333 ;
334 }
335 ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = 0;
336 while ((ETHERTSU_ADSBSY & 0x00000001) != 0) {
337 ;
338 }
339 ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = 0;
340
341 ETHERTSU_TEN &= ~(0x80000000 >> cnt);
342 tsu_ten_tmp &= ~(0x80000000 >> cnt);
343 break;
344 }
345 }
346}
347
348void ethernetext_set_all_multicast(int all) {
349 if (all != 0) {
350 ETHERECMR0 &= ~(0x00002000);
351 ETHERTSU_TEN = 0x00000000;
352 } else {
353 ETHERECMR0 |= 0x00002000;
354 ETHERTSU_TEN = tsu_ten_tmp;
355 }
356}
357
358
359int ethernet_init() {
360 ethernet_cfg_t ethcfg;
361
362 ethcfg.int_priority = 5;
363 ethcfg.recv_cb = NULL;
364 ethcfg.ether_mac = NULL;
365 ethernetext_init(&ethcfg);
366 ethernet_set_link(-1, 0); /* Auto-Negotiation */
367
368 return 0;
369}
370
371void ethernet_free() {
372 ETHERARSTR |= 0x00000001; /* ETHER software reset */
373 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
374}
375
376int ethernet_write(const char *data, int slen) {
377 edmac_send_desc_t *p_send_desc;
378 int32_t copy_size;
379
380 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
381 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
382 copy_size = 0;
383 } else {
384 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
385 if ((p_send_desc->td0 & TD0_TACT) != 0) {
386 copy_size = 0;
387 } else {
388 copy_size = MAX_SEND_SIZE - tx_wite_offset;
389 if (copy_size > slen) {
390 copy_size = slen;
391 }
392 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
393 tx_wite_offset += copy_size;
394 }
395 }
396
397 return copy_size;
398}
399
400int ethernet_send() {
401 edmac_send_desc_t *p_send_desc;
402 int32_t ret;
403
404 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
405 ret = 0;
406 } else {
407 /* Transfer 1 frame */
408 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
409
410 /* Sets the frame length */
411 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
412 tx_wite_offset = 0;
413
414 /* Sets the transmit descriptor to transmit again */
415 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
416 p_send_desc->td0 |= TD0_TACT;
417 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
418 ETHEREDTRR0 |= EDTRR0_TR;
419 }
420
421 /* Update the current descriptor */
422 send_top_index++;
423 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
424 send_top_index = 0;
425 }
426 ret = 1;
427 }
428
429 return ret;
430}
431
432int ethernet_receive() {
433 edmac_recv_desc_t *p_recv_desc;
434 int32_t receive_size = 0;
435
436 if (p_eth_desc_drecv != NULL) {
437 if (p_recv_end_desc != NULL) {
438 /* Sets the receive descriptor to receive again */
439 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
440 p_recv_end_desc->rd0 |= RD0_RACT;
441 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
442 ETHEREDRRR0 |= EDRRR0_RR;
443 }
444 p_recv_end_desc = NULL;
445 }
446
447 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
448 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
449 /* Receives 1 frame */
450 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
451 /* Receive frame error */
452 /* Sets the receive descriptor to receive again */
453 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
454 p_recv_desc->rd0 |= RD0_RACT;
455 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
456 ETHEREDRRR0 |= EDRRR0_RR;
457 }
458 } else {
459 /* Copies the received frame */
460 rx_read_offset = 0;
461 p_recv_end_desc = p_recv_desc;
462 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
463 }
464
465 /* Update the current descriptor */
466 recv_top_index++;
467 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
468 recv_top_index = 0;
469 }
470 }
471 }
472
473 return receive_size;
474}
475
476int ethernet_read(char *data, int dlen) {
477 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
478 int32_t copy_size;
479
480 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
481 copy_size = 0;
482 } else {
483 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
484 if (copy_size > dlen) {
485 copy_size = dlen;
486 }
487 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
488 rx_read_offset += copy_size;
489 }
490
491 return copy_size;
492}
493
494void ethernet_address(char *mac) {
495 if (mac != NULL) {
496 mbed_mac_address(mac); /* Get MAC Address */
497 }
498}
499
500int ethernet_link(void) {
501 int32_t ret;
502 uint16_t data;
503
504 data = phy_reg_read(BASIC_MODE_STATUS_REG);
505 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
506 ret = 1;
507 } else {
508 ret = 0;
509 }
510
511 return ret;
512}
513
514void ethernet_set_link(int speed, int duplex) {
515 uint16_t data;
516 int32_t i;
517 int32_t link;
518
519 if ((speed < 0) || (speed > 1)) {
520 data = 0x1000; /* Auto-Negotiation Enable */
521 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
522 for (i = 0; i < 1000; i++) {
523 data = phy_reg_read(BASIC_MODE_STATUS_REG);
524 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
525 break;
526 }
527 wait_100us(10);
528 }
529 } else {
530 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
531 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
532 wait_100us(1);
533 }
534
535 link = ethernetext_chk_link_mode();
536 ethernetext_set_link_mode(link);
537}
538
539void INT_Ether(void) {
540 uint32_t stat_edmac;
541 uint32_t stat_etherc;
542
543 /* Clear the interrupt request flag */
544 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
545 ETHEREESR0 = stat_edmac;
546 /* Reception-related */
547 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
548 if (p_recv_cb_fnc != NULL) {
549 p_recv_cb_fnc();
550 }
551 }
552 /* E-MAC-related */
553 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
554 /* Clear the interrupt request flag */
555 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
556 ETHERECSR0 = stat_etherc;
557 }
558}
559
560static void lan_reg_reset(void) {
561 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
562
563 ETHERARSTR |= 0x00000001; /* ETHER software reset */
564 while (j--) {
565 /* Do Nothing */
566 }
567
568 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
569 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
570
571 /* Check clear software reset */
572 while ((ETHEREDMR0 & 0x00000003) != 0) {
573 /* Do Nothing */
574 }
575}
576
577static void lan_desc_create(void) {
578 int32_t i;
579 uint8_t *p_memory_top;
580
581 (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
582 p_memory_top = ethernet_nc_memory;
583
584 /* Descriptor area configuration */
585 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
586 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
587 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
588 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
589
590 /* Transmit descriptor */
591 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
592 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
593 p_memory_top += SIZE_OF_BUFFER;
594 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
595 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
596 }
597 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
598
599 /* Receive descriptor */
600 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
601 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
602 p_memory_top += SIZE_OF_BUFFER;
603 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
604 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
605 }
606 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
607
608 /* Initialize descriptor management information */
609 send_top_index = 0;
610 recv_top_index = 0;
611 rx_read_offset = 0;
612 tx_wite_offset = 0;
613 p_recv_end_desc = NULL;
614}
615
616static void lan_reg_set(int32_t link) {
617 int32_t prm = link & PROMISCUOUS_MODE;
618 link &= ~PROMISCUOUS_MODE;
619
620 /* MAC address setting */
621 ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24)
622 | ((uint8_t)mac_addr[1] << 16)
623 | ((uint8_t)mac_addr[2] << 8)
624 | (uint8_t)mac_addr[3];
625 ETHERMALR0 = ((uint8_t)mac_addr[4] << 8)
626 | (uint8_t)mac_addr[5];
627
628 /* E-DMAC */
629 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
630 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
631 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
632 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
633 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
634 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
635 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
636 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
637 ETHEREDMR0 |= 0x00000040; /* Little endian */
638 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
639 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
640 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
641 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
642 ETHERFCFTR0 &= ~0x001F00FF;
643 ETHERFCFTR0 |= 0x00070007;
644 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
645
646 /* E-MAC */
647 ETHERECMR0 &= ~0x04BF2063; /* All clear */
648 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
649 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
650 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
651 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
652 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
653 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
654 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
655 } else {
656 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
657 }
658 if (!prm) {
659 ETHERECMR0 |= 0x00002000; /* MCT = 1 */
660 }
661 else {
662 ETHERECMR0 &= ~0x00002000; /* MCT = 0 */
663 }
664
665 /* Interrupt-related */
666 if (p_recv_cb_fnc != NULL) {
667 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
668 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
669 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
670 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
671 /*InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
672 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
673 GIC_SetConfiguration(ETHERI_IRQn, 1);
674 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
675 }
676
677 if (prm) {
678 ETHERECMR0 |= 0x00000001; /* Promiscuous Mode */
679 }
680
681 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
682
683 /* Enable transmission/reception */
684 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
685 ETHEREDRRR0 |= 0x00000001; /* RR */
686 }
687}
688
689static uint16_t phy_reg_read(uint16_t reg_addr) {
690 uint16_t data;
691
692 mii_preamble();
693 mii_cmd(reg_addr, PHY_READ);
694 mii_z();
695 mii_reg_read(&data);
696 mii_z();
697
698 return data;
699}
700
701static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
702 mii_preamble();
703 mii_cmd(reg_addr, PHY_WRITE);
704 mii_write_1();
705 mii_write_0();
706 mii_reg_write(data);
707 mii_z();
708}
709
710static void mii_preamble(void) {
711 int32_t i = 32;
712
713 for (i = 32; i > 0; i--) {
714 /* 1 is output via the MII (Media Independent Interface) block. */
715 mii_write_1();
716 }
717}
718
719static void mii_cmd(uint16_t reg_addr, uint32_t option) {
720 int32_t i;
721 uint16_t data = 0;
722
723 data |= (PHY_ST << 14); /* ST code */
724 data |= (option << 12); /* OP code */
725 data |= (PHY_ADDR << 7); /* PHY Address */
726 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
727 for (i = 14; i > 0; i--) {
728 if ((data & 0x8000) == 0) {
729 mii_write_0();
730 } else {
731 mii_write_1();
732 }
733 data <<= 1;
734 }
735}
736
737static void mii_reg_read(uint16_t *data) {
738 int32_t i;
739 uint16_t reg_data = 0;
740
741 /* Data are read in one bit at a time */
742 for (i = 16; i > 0; i--) {
743 set_ether_pir(PIR0_MDC_LOW);
744 set_ether_pir(PIR0_MDC_HIGH);
745 reg_data <<= 1;
746 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
747 set_ether_pir(PIR0_MDC_HIGH);
748 set_ether_pir(PIR0_MDC_LOW);
749 }
750 *data = reg_data;
751}
752
753static void mii_reg_write(uint16_t data) {
754 int32_t i;
755
756 /* Data are written one bit at a time */
757 for (i = 16; i > 0; i--) {
758 if ((data & 0x8000) == 0) {
759 mii_write_0();
760 } else {
761 mii_write_1();
762 }
763 data <<= 1;
764 }
765}
766
767static void mii_z(void) {
768 set_ether_pir(PIR0_MDC_LOW);
769 set_ether_pir(PIR0_MDC_HIGH);
770 set_ether_pir(PIR0_MDC_HIGH);
771 set_ether_pir(PIR0_MDC_LOW);
772}
773
774static void mii_write_1(void) {
775 set_ether_pir(PIR0_MDO | PIR0_MMD);
776 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
777 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
778 set_ether_pir(PIR0_MDO | PIR0_MMD);
779}
780
781static void mii_write_0(void) {
782 set_ether_pir(PIR0_MMD);
783 set_ether_pir(PIR0_MMD | PIR0_MDC);
784 set_ether_pir(PIR0_MMD | PIR0_MDC);
785 set_ether_pir(PIR0_MMD);
786}
787
788static void set_ether_pir(uint32_t set_data) {
789 int32_t i;
790
791 for (i = MDC_WAIT; i > 0; i--) {
792 ETHERPIR0 = set_data;
793 }
794}
795
796static void wait_100us(int32_t wait_cnt) {
797 volatile int32_t j = LOOP_100us * wait_cnt;
798
799 while (--j) {
800 /* Do Nothing */
801 }
802}
803#endif /* DEVICE_ETHERNET */
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