1 | /******************************************************************************
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2 | * @file system_RZ_A1H_H.c
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3 | * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
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4 | * @version V1.00
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5 | * @date 10 Mar 2017
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /*
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11 | * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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12 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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13 | *
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14 | * SPDX-License-Identifier: Apache-2.0
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15 | *
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16 | * Licensed under the Apache License, Version 2.0 (the License); you may
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17 | * not use this file except in compliance with the License.
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18 | * You may obtain a copy of the License at
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19 | *
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20 | * www.apache.org/licenses/LICENSE-2.0
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21 | *
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22 | * Unless required by applicable law or agreed to in writing, software
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23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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25 | * See the License for the specific language governing permissions and
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26 | * limitations under the License.
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27 | */
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28 |
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29 | #include <RZ_A1H.h>
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30 | #include "RZ_A1_Init.h"
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31 | #include "irq_ctrl.h"
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32 |
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33 | #define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
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34 | #define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
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35 | #define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
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36 |
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37 | /*
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38 | Port 0 (P0) MD pin assignment
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39 | P0_0: MD_BOOT0
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40 | P0_1: MD_BOOT1
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41 | P0_2: MD_CLK
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42 | P0_3: MD_CLKS
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43 | */
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44 |
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45 | /*----------------------------------------------------------------------------
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46 | System Core Clock Variable
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47 | *----------------------------------------------------------------------------*/
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48 | uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
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49 |
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50 | /*----------------------------------------------------------------------------
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51 | System Core Clock update function
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52 | *----------------------------------------------------------------------------*/
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53 | void SystemCoreClockUpdate (void)
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54 | {
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55 | uint32_t freq;
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56 | uint16_t mode;
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57 | uint16_t ifc;
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58 |
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59 | mode = (GPIO.PPR0 >> 2U) & 0x01U;
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60 |
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61 | if (mode == 0) {
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62 | /* Clock Mode 0 */
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63 | /* CLKIN is between 10MHz and 13.33MHz */
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64 | /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
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65 | freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
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66 | } else {
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67 | /* Clock Mode 1 */
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68 | /* CLKIN is 48MHz */
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69 | /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
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70 | freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
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71 | }
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72 |
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73 | /* Get CPG.FRQCR[IFC] bits */
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74 | ifc = (CPG.FRQCR >> 8U) & 0x03U;
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75 |
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76 | /* Determine Divider 2 output clock */
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77 | if (ifc == 0x03U) {
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78 | /* Division ratio is 1/3 */
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79 | freq = (freq / 3U);
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80 | }
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81 | else {
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82 | if (ifc == 0x01U) {
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83 | /* Division ratio is 2/3 */
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84 | freq = (freq * 2U) / 3U;
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85 | }
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86 | }
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87 |
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88 | SystemCoreClock = freq;
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89 | }
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90 |
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91 | /*----------------------------------------------------------------------------
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92 | IRQ Handler Register/Unregister
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93 | *----------------------------------------------------------------------------*/
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94 | uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
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95 | {
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96 | return IRQ_SetHandler(irq, handler);
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97 | }
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98 |
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99 | uint32_t InterruptHandlerUnregister (IRQn_Type irq)
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100 | {
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101 | return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
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102 | }
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103 |
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104 | /*----------------------------------------------------------------------------
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105 | System Initialization
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106 | *----------------------------------------------------------------------------*/
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107 | void SystemInit (void)
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108 | {
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109 | /* do not use global variables because this function is called before
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110 | reaching pre-main. RW section may be overwritten afterwards. */
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111 |
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112 | // Enable SRAM write access
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113 | CPG.SYSCR3 = 0x0F;
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114 |
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115 | RZ_A1_InitClock();
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116 | RZ_A1_InitBus();
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117 |
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118 | // Invalidate entire Unified TLB
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119 | __set_TLBIALL(0);
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120 |
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121 | // Invalidate entire branch predictor array
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122 | __set_BPIALL(0);
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123 | __DSB();
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124 | __ISB();
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125 |
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126 | // Invalidate instruction cache and flush branch target cache
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127 | __set_ICIALLU(0);
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128 | __DSB();
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129 | __ISB();
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130 |
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131 | // Invalidate data cache
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132 | L1C_InvalidateDCacheAll();
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133 |
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134 | // Create Translation Table
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135 | MMU_CreateTranslationTable();
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136 |
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137 | // Enable MMU
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138 | MMU_Enable();
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139 |
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140 | // Enable Caches
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141 | L1C_EnableCaches();
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142 | L1C_EnableBTAC();
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143 |
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144 | #if (__L2C_PRESENT == 1)
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145 | L2C_InvAllByWay();
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146 | // Enable L2C
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147 | L2C_Enable();
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148 | #endif
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149 |
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150 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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151 | // Enable FPU
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152 | __FPU_Enable();
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153 | #endif
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154 |
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155 | // IRQ Initialize
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156 | IRQ_Initialize();
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157 | }
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158 |
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159 | void mbed_sdk_init(void) {
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160 | L1C_CleanDCacheAll();
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161 | L1C_InvalidateICacheAll();
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162 | }
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