1 | /**************************************************************************//**
|
---|
2 | * @file mmu_RZ_A1H.c
|
---|
3 | * @brief MMU Configuration for RZ_A1H Device Series
|
---|
4 | * @version V1.00
|
---|
5 | * @date 10 Mar 2017
|
---|
6 | *
|
---|
7 | * @note
|
---|
8 | *
|
---|
9 | ******************************************************************************/
|
---|
10 | /*
|
---|
11 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
---|
12 | *
|
---|
13 | * SPDX-License-Identifier: Apache-2.0
|
---|
14 | *
|
---|
15 | * Licensed under the Apache License, Version 2.0 (the License); you may
|
---|
16 | * not use this file except in compliance with the License.
|
---|
17 | * You may obtain a copy of the License at
|
---|
18 | *
|
---|
19 | * www.apache.org/licenses/LICENSE-2.0
|
---|
20 | *
|
---|
21 | * Unless required by applicable law or agreed to in writing, software
|
---|
22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
---|
23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
---|
24 | * See the License for the specific language governing permissions and
|
---|
25 | * limitations under the License.
|
---|
26 | */
|
---|
27 |
|
---|
28 | /* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
|
---|
29 |
|
---|
30 | Memory Type
|
---|
31 | 0xffffffff |--------------------------| ------------
|
---|
32 | | Peripherals | Device
|
---|
33 | 0xfcf00000 |--------------------------| ------------
|
---|
34 | | Page Fault | Fault
|
---|
35 | 0xe8300000 |--------------------------| ------------
|
---|
36 | | Peripherals | Device
|
---|
37 | 0xe8000000 |--------------------------| ------------
|
---|
38 | | Page Fault | Fault
|
---|
39 | 0x60A00000 |--------------------------| ------------
|
---|
40 | | On Chip RAM (10M) Mirror | Fault
|
---|
41 | 0x60000000 |--------------------------| ------------
|
---|
42 | | SPI multi I/O 64MB | Fault
|
---|
43 | 0x5c000000 |--------------------------| ------------
|
---|
44 | | SPI multi I/O 64MB | Fault
|
---|
45 | 0x58000000 |--------------------------| ------------
|
---|
46 | | CS5 Mirror | Fault
|
---|
47 | 0x54000000 |--------------------------| ------------
|
---|
48 | | CS4 Mirror | Fault
|
---|
49 | 0x50000000 |--------------------------| ------------
|
---|
50 | | CS3 Mirror | Fault
|
---|
51 | 0x4c000000 |--------------------------| ------------
|
---|
52 | | CS2 Mirror | Fault
|
---|
53 | 0x48000000 |--------------------------| ------------
|
---|
54 | | CS1 Mirror | Fault
|
---|
55 | 0x44000000 |--------------------------| ------------
|
---|
56 | | CS0 Mirror | Fault
|
---|
57 | 0x40000000 |--------------------------| ------------
|
---|
58 | | BSC | RW
|
---|
59 | 0x3ff00000 |--------------------------| ------------
|
---|
60 | | SPI_MIO_BASE | RW
|
---|
61 | 0x3fe00000 |--------------------------| ------------
|
---|
62 | | Page Fault | Fault
|
---|
63 | 0x20A00000 |--------------------------| ------------
|
---|
64 | | On Chip RAM (10M) | RW
|
---|
65 | 0x20000000 |--------------------------| ------------
|
---|
66 | | SPI multi I/O 64MB | RO
|
---|
67 | 0x1c000000 |--------------------------| ------------
|
---|
68 | | SPI multi I/O 64MB | RO
|
---|
69 | 0x18000000 |--------------------------| ------------
|
---|
70 | | CS5 User Area 64MB | RW
|
---|
71 | 0x14000000 |--------------------------| ------------
|
---|
72 | | CS4 User Area 64MB | RW
|
---|
73 | 0x10000000 |--------------------------| ------------
|
---|
74 | | CS3 SDRAM 64MB | RW
|
---|
75 | 0x0c000000 |--------------------------| ------------
|
---|
76 | | CS2 SDRAM 64MB | RW
|
---|
77 | 0x08000000 |--------------------------| ------------
|
---|
78 | | CS1 NOR Flash 64MB | RO
|
---|
79 | 0x04000000 |--------------------------| ------------
|
---|
80 | | CS0 NOR Flash 64MB | RO
|
---|
81 | 0x00000000 |--------------------------| ------------
|
---|
82 | */
|
---|
83 |
|
---|
84 | // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
|
---|
85 | // Write-Through support *not* available
|
---|
86 | // Write-Back support available.
|
---|
87 | // Read allocation support available.
|
---|
88 | // Write allocation support available.
|
---|
89 |
|
---|
90 | //Note: You should use the Shareable attribute carefully.
|
---|
91 | //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
|
---|
92 | //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
|
---|
93 | //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
|
---|
94 |
|
---|
95 | //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
|
---|
96 | //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
|
---|
97 | //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
|
---|
98 |
|
---|
99 |
|
---|
100 | //Following MMU configuration is expected
|
---|
101 | //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
|
---|
102 | //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
|
---|
103 | //Domain 0 is always the Client domain
|
---|
104 | //Descriptors should place all memory in domain 0
|
---|
105 | //There are no restrictions by privilege level (PL0 can access all memory)
|
---|
106 |
|
---|
107 |
|
---|
108 | #include "RZ_A1H.h"
|
---|
109 |
|
---|
110 | //Import symbols from linker
|
---|
111 | extern uint32_t Image$$VECTORS$$Base;
|
---|
112 | extern uint32_t Image$$RO_DATA$$Base;
|
---|
113 | extern uint32_t Image$$RW_DATA$$Base;
|
---|
114 | extern uint32_t Image$$RW_IRAM1$$Base;
|
---|
115 | extern uint32_t Image$$CMD_AREA$$Base;
|
---|
116 | #if !defined ( __ICCARM__ )
|
---|
117 | extern uint32_t Image$$TTB$$ZI$$Base;
|
---|
118 | #endif
|
---|
119 |
|
---|
120 | #if defined( __CC_ARM )
|
---|
121 | #elif defined( __ICCARM__ )
|
---|
122 | #else
|
---|
123 | extern uint32_t Image$$RW_DATA_NC$$Base;
|
---|
124 | extern uint32_t Image$$ZI_DATA_NC$$Base;
|
---|
125 | #endif
|
---|
126 |
|
---|
127 | extern uint32_t Image$$VECTORS$$Limit;
|
---|
128 | extern uint32_t Image$$RO_DATA$$Limit;
|
---|
129 | extern uint32_t Image$$RW_DATA$$Limit;
|
---|
130 | extern uint32_t Image$$RW_IRAM1$$Limit;
|
---|
131 | extern uint32_t Image$$CMD_AREA$$Limit;
|
---|
132 | #if defined( __CC_ARM )
|
---|
133 | #else
|
---|
134 | extern uint32_t Image$$RW_DATA_NC$$Limit;
|
---|
135 | extern uint32_t Image$$ZI_DATA_NC$$Limit;
|
---|
136 | #endif
|
---|
137 |
|
---|
138 | #if defined( __ICCARM__ )
|
---|
139 | #define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
|
---|
140 | #define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
|
---|
141 | #define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
|
---|
142 | #define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
|
---|
143 | #define CMD_AREA_SIZE (((uint32_t)Image$$CMD_AREA$$Limit >> 20) - ((uint32_t)Image$$CMD_AREA$$Base >> 20) + 1)
|
---|
144 | #else
|
---|
145 | #define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
|
---|
146 | #define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
|
---|
147 | #define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
|
---|
148 | #define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
|
---|
149 | #define CMD_AREA_SIZE (((uint32_t)&Image$$CMD_AREA$$Limit >> 20) - ((uint32_t)&Image$$CMD_AREA$$Base >> 20) + 1)
|
---|
150 | #endif
|
---|
151 |
|
---|
152 | #if defined( __CC_ARM )
|
---|
153 | #else
|
---|
154 | #define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
|
---|
155 | #define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
|
---|
156 | #endif
|
---|
157 |
|
---|
158 | static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
|
---|
159 | static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
|
---|
160 | static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
|
---|
161 | static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
|
---|
162 | static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
|
---|
163 | static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
|
---|
164 | static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
|
---|
165 |
|
---|
166 | /* Define global descriptors */
|
---|
167 | static uint32_t Page_L1_4k = 0x0; //generic
|
---|
168 | static uint32_t Page_L1_64k = 0x0; //generic
|
---|
169 | static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
|
---|
170 | static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
|
---|
171 |
|
---|
172 | #if defined ( __ICCARM__ )
|
---|
173 | __no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
|
---|
174 | uint32_t Image$$VECTORS$$Base;
|
---|
175 | uint32_t Image$$RO_DATA$$Base;
|
---|
176 | uint32_t Image$$RW_DATA$$Base;
|
---|
177 | uint32_t Image$$RW_IRAM1$$Base;
|
---|
178 |
|
---|
179 | uint32_t Image$$VECTORS$$Limit;
|
---|
180 | uint32_t Image$$RO_DATA$$Limit;
|
---|
181 | uint32_t Image$$RW_DATA$$Limit;
|
---|
182 | uint32_t Image$$RW_IRAM1$$Limit;
|
---|
183 | #endif
|
---|
184 |
|
---|
185 | void MMU_CreateTranslationTable(void)
|
---|
186 | {
|
---|
187 | mmu_region_attributes_Type region;
|
---|
188 | #if defined ( __ICCARM__ )
|
---|
189 | #pragma section=".intvec"
|
---|
190 | #pragma section=".rodata"
|
---|
191 | #pragma section=".rwdata"
|
---|
192 | #pragma section=".bss"
|
---|
193 |
|
---|
194 | Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
|
---|
195 | Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
|
---|
196 | Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
|
---|
197 | Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
|
---|
198 | Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
|
---|
199 | Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
|
---|
200 | Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");
|
---|
201 | Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
|
---|
202 | #endif
|
---|
203 | /*
|
---|
204 | * Generate descriptors. Refer to core_ca.h to get information about attributes
|
---|
205 | *
|
---|
206 | */
|
---|
207 | //Create descriptors for Vectors, RO, RW, ZI sections
|
---|
208 | section_normal(Sect_Normal, region);
|
---|
209 | section_normal_cod(Sect_Normal_Cod, region);
|
---|
210 | section_normal_ro(Sect_Normal_RO, region);
|
---|
211 | section_normal(Sect_Normal_RW, region);
|
---|
212 | //Create descriptors for peripherals
|
---|
213 | section_device_ro(Sect_Device_RO, region);
|
---|
214 | section_device_rw(Sect_Device_RW, region);
|
---|
215 | section_normal_nc(Sect_Normal_NC, region);
|
---|
216 | //Create descriptors for 64k pages
|
---|
217 | page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
|
---|
218 | //Create descriptors for 4k pages
|
---|
219 | page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
|
---|
220 |
|
---|
221 | /*
|
---|
222 | * Define MMU flat-map regions and attributes
|
---|
223 | *
|
---|
224 | */
|
---|
225 |
|
---|
226 | //Create 4GB of faulting entries
|
---|
227 | MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
|
---|
228 |
|
---|
229 | // R7S72100 memory map.
|
---|
230 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
|
---|
231 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
|
---|
232 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
|
---|
233 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
|
---|
234 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
|
---|
235 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
|
---|
236 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
|
---|
237 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
|
---|
238 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
|
---|
239 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
|
---|
240 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW);
|
---|
241 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
|
---|
242 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
|
---|
243 |
|
---|
244 | #if defined( __ICCARM__ )
|
---|
245 | //Define Image
|
---|
246 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
|
---|
247 | MMU_TTSection (&Image$$TTB$$ZI$$Base, 0x18200000, (0x18800000 >> 20) - (0x18200000 >> 20) + 1, Sect_Normal_Cod);
|
---|
248 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
|
---|
249 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
|
---|
250 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
|
---|
251 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$CMD_AREA$$Base, CMD_AREA_SIZE, Sect_Normal);
|
---|
252 | #else
|
---|
253 | //Define Image
|
---|
254 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
|
---|
255 | MMU_TTSection (&Image$$TTB$$ZI$$Base, 0x18200000, (0x18800000 >> 20) - (0x18200000 >> 20) + 1, Sect_Normal_Cod);
|
---|
256 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
|
---|
257 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
|
---|
258 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
|
---|
259 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$CMD_AREA$$Base, CMD_AREA_SIZE, Sect_Normal);
|
---|
260 | #endif
|
---|
261 |
|
---|
262 | #if defined( __CC_ARM )
|
---|
263 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
|
---|
264 | #elif defined ( __ICCARM__ )
|
---|
265 | MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
|
---|
266 |
|
---|
267 | #else
|
---|
268 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
|
---|
269 | MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
|
---|
270 | #endif
|
---|
271 |
|
---|
272 | /* Set location of level 1 page table
|
---|
273 | ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
|
---|
274 | ; 13:7 - 0x0
|
---|
275 | ; 6 - IRGN[0] 0x0 (Inner WB WA)
|
---|
276 | ; 5 - NOS 0x0 (Non-shared)
|
---|
277 | ; 4:3 - RGN 0x1 (Outer WB WA)
|
---|
278 | ; 2 - IMP 0x0 (Implementation Defined)
|
---|
279 | ; 1 - S 0x0 (Non-shared)
|
---|
280 | ; 0 - IRGN[1] 0x1 (Inner WB WA) */
|
---|
281 | __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
|
---|
282 | __ISB();
|
---|
283 |
|
---|
284 | /* Set up domain access control register
|
---|
285 | ; We set domain 0 to Client and all other domains to No Access.
|
---|
286 | ; All translation table entries specify domain 0 */
|
---|
287 | __set_DACR(1);
|
---|
288 | __ISB();
|
---|
289 | }
|
---|