[429] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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| 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : vdc5_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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| 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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| 28 | ******************************************************************************/
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| 29 | #ifndef VDC5_IODEFINE_H
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| 30 | #define VDC5_IODEFINE_H
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| 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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| 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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| 36 | #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
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| 37 | #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
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| 38 |
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| 39 |
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| 40 | /* Start of channel array defines of VDC5 */
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| 41 |
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| 42 | /* Channel array defines of VDC5 */
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| 43 | /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
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| 44 | #define VDC5_COUNT (2)
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| 45 | #define VDC5_ADDRESS_LIST \
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| 46 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 47 | &VDC50, &VDC51 \
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| 48 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 49 |
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| 50 |
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| 51 |
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| 52 | /* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */
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| 53 | /*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
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| 54 | #define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2)
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| 55 | #define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
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| 56 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 57 | { \
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| 58 | &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
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| 59 | &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
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| 60 | } \
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| 61 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 62 | #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
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| 63 | #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
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| 64 | #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
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| 65 | #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
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| 66 |
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| 67 |
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| 68 |
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| 69 |
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| 70 | /* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */
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| 71 | /*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
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| 72 | #define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2)
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| 73 | #define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
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| 74 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 75 | { \
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| 76 | &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
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| 77 | &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
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| 78 | } \
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| 79 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 80 | #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
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| 81 | #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
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| 82 | #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
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| 83 | #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
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| 84 |
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| 85 |
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| 86 |
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| 87 |
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| 88 | /* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */
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| 89 | /*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
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| 90 | #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2)
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| 91 | #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
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| 92 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 93 | { \
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| 94 | &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
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| 95 | &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
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| 96 | } \
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| 97 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 98 | #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
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| 99 | #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
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| 100 | #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
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| 101 | #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
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| 102 |
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| 103 |
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| 104 |
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| 105 |
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| 106 | /* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */
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| 107 | /*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
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| 108 | #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2)
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| 109 | #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
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| 110 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 111 | { \
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| 112 | &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
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| 113 | &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
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| 114 | } \
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| 115 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 116 | #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
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| 117 | #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
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| 118 | #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
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| 119 | #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
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| 120 |
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| 121 |
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| 122 |
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| 123 |
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| 124 | /* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */
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| 125 | /*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
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| 126 | #define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2)
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| 127 | #define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
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| 128 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 129 | { \
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| 130 | &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
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| 131 | &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
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| 132 | } \
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| 133 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 134 | #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
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| 135 | #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
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| 136 | #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
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| 137 | #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
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| 138 |
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| 139 |
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| 140 |
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| 141 |
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| 142 | /* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */
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| 143 | /*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
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| 144 | #define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2)
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| 145 | #define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
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| 146 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 147 | { \
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| 148 | &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
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| 149 | &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
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| 150 | } \
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| 151 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 152 | #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
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| 153 | #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
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| 154 | #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
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| 155 | #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
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| 156 |
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| 157 |
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| 158 |
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| 159 |
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| 160 | /* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */
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| 161 | /*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
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| 162 | #define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2)
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| 163 | #define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
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| 164 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 165 | { \
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| 166 | &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
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| 167 | &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
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| 168 | } \
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| 169 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 170 | #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
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| 171 | #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
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| 172 | #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
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| 173 | #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
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| 174 |
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| 175 |
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| 176 | /* End of channel array defines of VDC5 */
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| 177 |
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| 178 |
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| 179 | #define VDC50INP_UPDATE (VDC50.INP_UPDATE)
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| 180 | #define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT)
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| 181 | #define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT)
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| 182 | #define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ)
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| 183 | #define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ)
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| 184 | #define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE)
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| 185 | #define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0)
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| 186 | #define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1)
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| 187 | #define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE)
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| 188 | #define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0)
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| 189 | #define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1)
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| 190 | #define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0)
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| 191 | #define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1)
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| 192 | #define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0)
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| 193 | #define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1)
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| 194 | #define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG)
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| 195 | #define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE)
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| 196 | #define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1)
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| 197 | #define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2)
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| 198 | #define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3)
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| 199 | #define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4)
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| 200 | #define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5)
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| 201 | #define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6)
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| 202 | #define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7)
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| 203 | #define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9)
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| 204 | #define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0)
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| 205 | #define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT)
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| 206 | #define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1)
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| 207 | #define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2)
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| 208 | #define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3)
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| 209 | #define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4)
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| 210 | #define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5)
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| 211 | #define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6)
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| 212 | #define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7)
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| 213 | #define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1)
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| 214 | #define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2)
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| 215 | #define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3)
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| 216 | #define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4)
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| 217 | #define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5)
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| 218 | #define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6)
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| 219 | #define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7)
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| 220 | #define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8)
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| 221 | #define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1)
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| 222 | #define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE)
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| 223 | #define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1)
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| 224 | #define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2)
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| 225 | #define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3)
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| 226 | #define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4)
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| 227 | #define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5)
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| 228 | #define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6)
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| 229 | #define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7)
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| 230 | #define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8)
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| 231 | #define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9)
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| 232 | #define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10)
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| 233 | #define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11)
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| 234 | #define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1)
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| 235 | #define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0)
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| 236 | #define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1)
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| 237 | #define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2)
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| 238 | #define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3)
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| 239 | #define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD)
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| 240 | #define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT)
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| 241 | #define VDC50GR0_UPDATE (VDC50.GR0_UPDATE)
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| 242 | #define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD)
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| 243 | #define VDC50GR0_FLM1 (VDC50.GR0_FLM1)
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| 244 | #define VDC50GR0_FLM2 (VDC50.GR0_FLM2)
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| 245 | #define VDC50GR0_FLM3 (VDC50.GR0_FLM3)
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| 246 | #define VDC50GR0_FLM4 (VDC50.GR0_FLM4)
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| 247 | #define VDC50GR0_FLM5 (VDC50.GR0_FLM5)
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| 248 | #define VDC50GR0_FLM6 (VDC50.GR0_FLM6)
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| 249 | #define VDC50GR0_AB1 (VDC50.GR0_AB1)
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| 250 | #define VDC50GR0_AB2 (VDC50.GR0_AB2)
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| 251 | #define VDC50GR0_AB3 (VDC50.GR0_AB3)
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| 252 | #define VDC50GR0_AB7 (VDC50.GR0_AB7)
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| 253 | #define VDC50GR0_AB8 (VDC50.GR0_AB8)
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| 254 | #define VDC50GR0_AB9 (VDC50.GR0_AB9)
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| 255 | #define VDC50GR0_AB10 (VDC50.GR0_AB10)
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| 256 | #define VDC50GR0_AB11 (VDC50.GR0_AB11)
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| 257 | #define VDC50GR0_BASE (VDC50.GR0_BASE)
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| 258 | #define VDC50GR0_CLUT (VDC50.GR0_CLUT)
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| 259 | #define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE)
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| 260 | #define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET)
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| 261 | #define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1)
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| 262 | #define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2)
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| 263 | #define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3)
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| 264 | #define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1)
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| 265 | #define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2)
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| 266 | #define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3)
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| 267 | #define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4)
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| 268 | #define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5)
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| 269 | #define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6)
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| 270 | #define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1)
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| 271 | #define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2)
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| 272 | #define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE)
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| 273 | #define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0)
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| 274 | #define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1)
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| 275 | #define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0)
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| 276 | #define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1)
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| 277 | #define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0)
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| 278 | #define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1)
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| 279 | #define VDC50GR2_UPDATE (VDC50.GR2_UPDATE)
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| 280 | #define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD)
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| 281 | #define VDC50GR2_FLM1 (VDC50.GR2_FLM1)
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| 282 | #define VDC50GR2_FLM2 (VDC50.GR2_FLM2)
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| 283 | #define VDC50GR2_FLM3 (VDC50.GR2_FLM3)
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| 284 | #define VDC50GR2_FLM4 (VDC50.GR2_FLM4)
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| 285 | #define VDC50GR2_FLM5 (VDC50.GR2_FLM5)
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| 286 | #define VDC50GR2_FLM6 (VDC50.GR2_FLM6)
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| 287 | #define VDC50GR2_AB1 (VDC50.GR2_AB1)
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| 288 | #define VDC50GR2_AB2 (VDC50.GR2_AB2)
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| 289 | #define VDC50GR2_AB3 (VDC50.GR2_AB3)
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| 290 | #define VDC50GR2_AB4 (VDC50.GR2_AB4)
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| 291 | #define VDC50GR2_AB5 (VDC50.GR2_AB5)
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| 292 | #define VDC50GR2_AB6 (VDC50.GR2_AB6)
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| 293 | #define VDC50GR2_AB7 (VDC50.GR2_AB7)
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| 294 | #define VDC50GR2_AB8 (VDC50.GR2_AB8)
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| 295 | #define VDC50GR2_AB9 (VDC50.GR2_AB9)
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| 296 | #define VDC50GR2_AB10 (VDC50.GR2_AB10)
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| 297 | #define VDC50GR2_AB11 (VDC50.GR2_AB11)
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| 298 | #define VDC50GR2_BASE (VDC50.GR2_BASE)
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| 299 | #define VDC50GR2_CLUT (VDC50.GR2_CLUT)
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| 300 | #define VDC50GR2_MON (VDC50.GR2_MON)
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| 301 | #define VDC50GR3_UPDATE (VDC50.GR3_UPDATE)
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| 302 | #define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD)
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| 303 | #define VDC50GR3_FLM1 (VDC50.GR3_FLM1)
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| 304 | #define VDC50GR3_FLM2 (VDC50.GR3_FLM2)
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| 305 | #define VDC50GR3_FLM3 (VDC50.GR3_FLM3)
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| 306 | #define VDC50GR3_FLM4 (VDC50.GR3_FLM4)
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| 307 | #define VDC50GR3_FLM5 (VDC50.GR3_FLM5)
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| 308 | #define VDC50GR3_FLM6 (VDC50.GR3_FLM6)
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| 309 | #define VDC50GR3_AB1 (VDC50.GR3_AB1)
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| 310 | #define VDC50GR3_AB2 (VDC50.GR3_AB2)
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| 311 | #define VDC50GR3_AB3 (VDC50.GR3_AB3)
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| 312 | #define VDC50GR3_AB4 (VDC50.GR3_AB4)
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| 313 | #define VDC50GR3_AB5 (VDC50.GR3_AB5)
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| 314 | #define VDC50GR3_AB6 (VDC50.GR3_AB6)
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| 315 | #define VDC50GR3_AB7 (VDC50.GR3_AB7)
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| 316 | #define VDC50GR3_AB8 (VDC50.GR3_AB8)
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| 317 | #define VDC50GR3_AB9 (VDC50.GR3_AB9)
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| 318 | #define VDC50GR3_AB10 (VDC50.GR3_AB10)
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| 319 | #define VDC50GR3_AB11 (VDC50.GR3_AB11)
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| 320 | #define VDC50GR3_BASE (VDC50.GR3_BASE)
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| 321 | #define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT)
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| 322 | #define VDC50GR3_MON (VDC50.GR3_MON)
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| 323 | #define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE)
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| 324 | #define VDC50GAM_SW (VDC50.GAM_SW)
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| 325 | #define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1)
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| 326 | #define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2)
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| 327 | #define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3)
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| 328 | #define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4)
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| 329 | #define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5)
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| 330 | #define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6)
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| 331 | #define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7)
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| 332 | #define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8)
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| 333 | #define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9)
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| 334 | #define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10)
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| 335 | #define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11)
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| 336 | #define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12)
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| 337 | #define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13)
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| 338 | #define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14)
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| 339 | #define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15)
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| 340 | #define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16)
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| 341 | #define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1)
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| 342 | #define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2)
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| 343 | #define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3)
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| 344 | #define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4)
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| 345 | #define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5)
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| 346 | #define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6)
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| 347 | #define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7)
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| 348 | #define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8)
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| 349 | #define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE)
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| 350 | #define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1)
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| 351 | #define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2)
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| 352 | #define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3)
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| 353 | #define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4)
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| 354 | #define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5)
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| 355 | #define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6)
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| 356 | #define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7)
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| 357 | #define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8)
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| 358 | #define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9)
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| 359 | #define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10)
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| 360 | #define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11)
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| 361 | #define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12)
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| 362 | #define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13)
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| 363 | #define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14)
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| 364 | #define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15)
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| 365 | #define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16)
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| 366 | #define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1)
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| 367 | #define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2)
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| 368 | #define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3)
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| 369 | #define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4)
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| 370 | #define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5)
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| 371 | #define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6)
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| 372 | #define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7)
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| 373 | #define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8)
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| 374 | #define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE)
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| 375 | #define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1)
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| 376 | #define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2)
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| 377 | #define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3)
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| 378 | #define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4)
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| 379 | #define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5)
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| 380 | #define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6)
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| 381 | #define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7)
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| 382 | #define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8)
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| 383 | #define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9)
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| 384 | #define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10)
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| 385 | #define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11)
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| 386 | #define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12)
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| 387 | #define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13)
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| 388 | #define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14)
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| 389 | #define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15)
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| 390 | #define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16)
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| 391 | #define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1)
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| 392 | #define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2)
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| 393 | #define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3)
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| 394 | #define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4)
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| 395 | #define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5)
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| 396 | #define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6)
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| 397 | #define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7)
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| 398 | #define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8)
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| 399 | #define VDC50TCON_UPDATE (VDC50.TCON_UPDATE)
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| 400 | #define VDC50TCON_TIM (VDC50.TCON_TIM)
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| 401 | #define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1)
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| 402 | #define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2)
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| 403 | #define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1)
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| 404 | #define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2)
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| 405 | #define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1)
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| 406 | #define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2)
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| 407 | #define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1)
|
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| 408 | #define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2)
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| 409 | #define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1)
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| 410 | #define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2)
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| 411 | #define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1)
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| 412 | #define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2)
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| 413 | #define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1)
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| 414 | #define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2)
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| 415 | #define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE)
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| 416 | #define VDC50OUT_UPDATE (VDC50.OUT_UPDATE)
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| 417 | #define VDC50OUT_SET (VDC50.OUT_SET)
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| 418 | #define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1)
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| 419 | #define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2)
|
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| 420 | #define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST)
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| 421 | #define VDC50OUT_PDTHA (VDC50.OUT_PDTHA)
|
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| 422 | #define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE)
|
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| 423 | #define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1)
|
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| 424 | #define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2)
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| 425 | #define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3)
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| 426 | #define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4)
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| 427 | #define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5)
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| 428 | #define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6)
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| 429 | #define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK)
|
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| 430 | #define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT)
|
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| 431 | #define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE)
|
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| 432 | #define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1)
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| 433 | #define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2)
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| 434 | #define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3)
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| 435 | #define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4)
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| 436 | #define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5)
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| 437 | #define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6)
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| 438 | #define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7)
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| 439 | #define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9)
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| 440 | #define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0)
|
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| 441 | #define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT)
|
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| 442 | #define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1)
|
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| 443 | #define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2)
|
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| 444 | #define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3)
|
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| 445 | #define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4)
|
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| 446 | #define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5)
|
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| 447 | #define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6)
|
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| 448 | #define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7)
|
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| 449 | #define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1)
|
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| 450 | #define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2)
|
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| 451 | #define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3)
|
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| 452 | #define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4)
|
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| 453 | #define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5)
|
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| 454 | #define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6)
|
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| 455 | #define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7)
|
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| 456 | #define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8)
|
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| 457 | #define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1)
|
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| 458 | #define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE)
|
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| 459 | #define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1)
|
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| 460 | #define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2)
|
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| 461 | #define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3)
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| 462 | #define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4)
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| 463 | #define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5)
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| 464 | #define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6)
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| 465 | #define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7)
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| 466 | #define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8)
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| 467 | #define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9)
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| 468 | #define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10)
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| 469 | #define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11)
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| 470 | #define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1)
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| 471 | #define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0)
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| 472 | #define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1)
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| 473 | #define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2)
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| 474 | #define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3)
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| 475 | #define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD)
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| 476 | #define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT)
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| 477 | #define VDC50GR1_UPDATE (VDC50.GR1_UPDATE)
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| 478 | #define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD)
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| 479 | #define VDC50GR1_FLM1 (VDC50.GR1_FLM1)
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| 480 | #define VDC50GR1_FLM2 (VDC50.GR1_FLM2)
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| 481 | #define VDC50GR1_FLM3 (VDC50.GR1_FLM3)
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| 482 | #define VDC50GR1_FLM4 (VDC50.GR1_FLM4)
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| 483 | #define VDC50GR1_FLM5 (VDC50.GR1_FLM5)
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| 484 | #define VDC50GR1_FLM6 (VDC50.GR1_FLM6)
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| 485 | #define VDC50GR1_AB1 (VDC50.GR1_AB1)
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| 486 | #define VDC50GR1_AB2 (VDC50.GR1_AB2)
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| 487 | #define VDC50GR1_AB3 (VDC50.GR1_AB3)
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| 488 | #define VDC50GR1_AB4 (VDC50.GR1_AB4)
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| 489 | #define VDC50GR1_AB5 (VDC50.GR1_AB5)
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| 490 | #define VDC50GR1_AB6 (VDC50.GR1_AB6)
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| 491 | #define VDC50GR1_AB7 (VDC50.GR1_AB7)
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| 492 | #define VDC50GR1_AB8 (VDC50.GR1_AB8)
|
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| 493 | #define VDC50GR1_AB9 (VDC50.GR1_AB9)
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| 494 | #define VDC50GR1_AB10 (VDC50.GR1_AB10)
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| 495 | #define VDC50GR1_AB11 (VDC50.GR1_AB11)
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| 496 | #define VDC50GR1_BASE (VDC50.GR1_BASE)
|
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| 497 | #define VDC50GR1_CLUT (VDC50.GR1_CLUT)
|
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| 498 | #define VDC50GR1_MON (VDC50.GR1_MON)
|
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| 499 | #define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE)
|
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| 500 | #define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET)
|
---|
| 501 | #define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1)
|
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| 502 | #define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2)
|
---|
| 503 | #define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3)
|
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| 504 | #define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1)
|
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| 505 | #define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2)
|
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| 506 | #define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3)
|
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| 507 | #define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4)
|
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| 508 | #define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5)
|
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| 509 | #define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6)
|
---|
| 510 | #define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1)
|
---|
| 511 | #define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2)
|
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| 512 | #define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE)
|
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| 513 | #define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0)
|
---|
| 514 | #define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1)
|
---|
| 515 | #define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0)
|
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| 516 | #define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1)
|
---|
| 517 | #define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0)
|
---|
| 518 | #define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1)
|
---|
| 519 | #define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE)
|
---|
| 520 | #define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1)
|
---|
| 521 | #define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2)
|
---|
| 522 | #define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3)
|
---|
| 523 | #define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4)
|
---|
| 524 | #define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5)
|
---|
| 525 | #define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6)
|
---|
| 526 | #define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7)
|
---|
| 527 | #define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE)
|
---|
| 528 | #define VDC50GR_VIN_MON (VDC50.GR_VIN_MON)
|
---|
| 529 | #define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE)
|
---|
| 530 | #define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1)
|
---|
| 531 | #define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2)
|
---|
| 532 | #define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3)
|
---|
| 533 | #define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4)
|
---|
| 534 | #define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5)
|
---|
| 535 | #define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6)
|
---|
| 536 | #define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7)
|
---|
| 537 | #define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1)
|
---|
| 538 | #define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2)
|
---|
| 539 | #define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3)
|
---|
| 540 | #define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7)
|
---|
| 541 | #define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1)
|
---|
| 542 | #define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2)
|
---|
| 543 | #define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3)
|
---|
| 544 | #define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8)
|
---|
| 545 | #define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1)
|
---|
| 546 | #define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE)
|
---|
| 547 | #define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1)
|
---|
| 548 | #define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2)
|
---|
| 549 | #define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3)
|
---|
| 550 | #define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4)
|
---|
| 551 | #define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5)
|
---|
| 552 | #define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6)
|
---|
| 553 | #define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7)
|
---|
| 554 | #define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE)
|
---|
| 555 | #define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD)
|
---|
| 556 | #define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1)
|
---|
| 557 | #define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2)
|
---|
| 558 | #define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3)
|
---|
| 559 | #define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4)
|
---|
| 560 | #define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5)
|
---|
| 561 | #define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6)
|
---|
| 562 | #define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1)
|
---|
| 563 | #define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2)
|
---|
| 564 | #define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3)
|
---|
| 565 | #define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7)
|
---|
| 566 | #define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8)
|
---|
| 567 | #define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9)
|
---|
| 568 | #define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10)
|
---|
| 569 | #define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11)
|
---|
| 570 | #define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE)
|
---|
| 571 | #define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT)
|
---|
| 572 | #define VDC50GR_OIR_MON (VDC50.GR_OIR_MON)
|
---|
| 573 | #define VDC51INP_UPDATE (VDC51.INP_UPDATE)
|
---|
| 574 | #define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT)
|
---|
| 575 | #define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT)
|
---|
| 576 | #define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ)
|
---|
| 577 | #define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ)
|
---|
| 578 | #define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE)
|
---|
| 579 | #define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0)
|
---|
| 580 | #define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1)
|
---|
| 581 | #define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE)
|
---|
| 582 | #define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0)
|
---|
| 583 | #define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1)
|
---|
| 584 | #define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0)
|
---|
| 585 | #define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1)
|
---|
| 586 | #define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0)
|
---|
| 587 | #define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1)
|
---|
| 588 | #define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG)
|
---|
| 589 | #define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE)
|
---|
| 590 | #define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1)
|
---|
| 591 | #define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2)
|
---|
| 592 | #define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3)
|
---|
| 593 | #define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4)
|
---|
| 594 | #define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5)
|
---|
| 595 | #define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6)
|
---|
| 596 | #define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7)
|
---|
| 597 | #define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9)
|
---|
| 598 | #define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0)
|
---|
| 599 | #define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT)
|
---|
| 600 | #define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1)
|
---|
| 601 | #define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2)
|
---|
| 602 | #define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3)
|
---|
| 603 | #define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4)
|
---|
| 604 | #define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5)
|
---|
| 605 | #define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6)
|
---|
| 606 | #define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7)
|
---|
| 607 | #define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1)
|
---|
| 608 | #define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2)
|
---|
| 609 | #define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3)
|
---|
| 610 | #define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4)
|
---|
| 611 | #define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5)
|
---|
| 612 | #define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6)
|
---|
| 613 | #define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7)
|
---|
| 614 | #define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8)
|
---|
| 615 | #define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1)
|
---|
| 616 | #define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE)
|
---|
| 617 | #define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1)
|
---|
| 618 | #define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2)
|
---|
| 619 | #define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3)
|
---|
| 620 | #define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4)
|
---|
| 621 | #define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5)
|
---|
| 622 | #define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6)
|
---|
| 623 | #define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7)
|
---|
| 624 | #define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8)
|
---|
| 625 | #define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9)
|
---|
| 626 | #define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10)
|
---|
| 627 | #define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11)
|
---|
| 628 | #define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1)
|
---|
| 629 | #define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0)
|
---|
| 630 | #define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1)
|
---|
| 631 | #define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2)
|
---|
| 632 | #define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3)
|
---|
| 633 | #define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD)
|
---|
| 634 | #define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT)
|
---|
| 635 | #define VDC51GR0_UPDATE (VDC51.GR0_UPDATE)
|
---|
| 636 | #define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD)
|
---|
| 637 | #define VDC51GR0_FLM1 (VDC51.GR0_FLM1)
|
---|
| 638 | #define VDC51GR0_FLM2 (VDC51.GR0_FLM2)
|
---|
| 639 | #define VDC51GR0_FLM3 (VDC51.GR0_FLM3)
|
---|
| 640 | #define VDC51GR0_FLM4 (VDC51.GR0_FLM4)
|
---|
| 641 | #define VDC51GR0_FLM5 (VDC51.GR0_FLM5)
|
---|
| 642 | #define VDC51GR0_FLM6 (VDC51.GR0_FLM6)
|
---|
| 643 | #define VDC51GR0_AB1 (VDC51.GR0_AB1)
|
---|
| 644 | #define VDC51GR0_AB2 (VDC51.GR0_AB2)
|
---|
| 645 | #define VDC51GR0_AB3 (VDC51.GR0_AB3)
|
---|
| 646 | #define VDC51GR0_AB7 (VDC51.GR0_AB7)
|
---|
| 647 | #define VDC51GR0_AB8 (VDC51.GR0_AB8)
|
---|
| 648 | #define VDC51GR0_AB9 (VDC51.GR0_AB9)
|
---|
| 649 | #define VDC51GR0_AB10 (VDC51.GR0_AB10)
|
---|
| 650 | #define VDC51GR0_AB11 (VDC51.GR0_AB11)
|
---|
| 651 | #define VDC51GR0_BASE (VDC51.GR0_BASE)
|
---|
| 652 | #define VDC51GR0_CLUT (VDC51.GR0_CLUT)
|
---|
| 653 | #define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE)
|
---|
| 654 | #define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET)
|
---|
| 655 | #define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1)
|
---|
| 656 | #define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2)
|
---|
| 657 | #define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3)
|
---|
| 658 | #define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1)
|
---|
| 659 | #define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2)
|
---|
| 660 | #define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3)
|
---|
| 661 | #define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4)
|
---|
| 662 | #define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5)
|
---|
| 663 | #define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6)
|
---|
| 664 | #define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1)
|
---|
| 665 | #define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2)
|
---|
| 666 | #define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE)
|
---|
| 667 | #define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0)
|
---|
| 668 | #define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1)
|
---|
| 669 | #define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0)
|
---|
| 670 | #define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1)
|
---|
| 671 | #define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0)
|
---|
| 672 | #define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1)
|
---|
| 673 | #define VDC51GR2_UPDATE (VDC51.GR2_UPDATE)
|
---|
| 674 | #define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD)
|
---|
| 675 | #define VDC51GR2_FLM1 (VDC51.GR2_FLM1)
|
---|
| 676 | #define VDC51GR2_FLM2 (VDC51.GR2_FLM2)
|
---|
| 677 | #define VDC51GR2_FLM3 (VDC51.GR2_FLM3)
|
---|
| 678 | #define VDC51GR2_FLM4 (VDC51.GR2_FLM4)
|
---|
| 679 | #define VDC51GR2_FLM5 (VDC51.GR2_FLM5)
|
---|
| 680 | #define VDC51GR2_FLM6 (VDC51.GR2_FLM6)
|
---|
| 681 | #define VDC51GR2_AB1 (VDC51.GR2_AB1)
|
---|
| 682 | #define VDC51GR2_AB2 (VDC51.GR2_AB2)
|
---|
| 683 | #define VDC51GR2_AB3 (VDC51.GR2_AB3)
|
---|
| 684 | #define VDC51GR2_AB4 (VDC51.GR2_AB4)
|
---|
| 685 | #define VDC51GR2_AB5 (VDC51.GR2_AB5)
|
---|
| 686 | #define VDC51GR2_AB6 (VDC51.GR2_AB6)
|
---|
| 687 | #define VDC51GR2_AB7 (VDC51.GR2_AB7)
|
---|
| 688 | #define VDC51GR2_AB8 (VDC51.GR2_AB8)
|
---|
| 689 | #define VDC51GR2_AB9 (VDC51.GR2_AB9)
|
---|
| 690 | #define VDC51GR2_AB10 (VDC51.GR2_AB10)
|
---|
| 691 | #define VDC51GR2_AB11 (VDC51.GR2_AB11)
|
---|
| 692 | #define VDC51GR2_BASE (VDC51.GR2_BASE)
|
---|
| 693 | #define VDC51GR2_CLUT (VDC51.GR2_CLUT)
|
---|
| 694 | #define VDC51GR2_MON (VDC51.GR2_MON)
|
---|
| 695 | #define VDC51GR3_UPDATE (VDC51.GR3_UPDATE)
|
---|
| 696 | #define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD)
|
---|
| 697 | #define VDC51GR3_FLM1 (VDC51.GR3_FLM1)
|
---|
| 698 | #define VDC51GR3_FLM2 (VDC51.GR3_FLM2)
|
---|
| 699 | #define VDC51GR3_FLM3 (VDC51.GR3_FLM3)
|
---|
| 700 | #define VDC51GR3_FLM4 (VDC51.GR3_FLM4)
|
---|
| 701 | #define VDC51GR3_FLM5 (VDC51.GR3_FLM5)
|
---|
| 702 | #define VDC51GR3_FLM6 (VDC51.GR3_FLM6)
|
---|
| 703 | #define VDC51GR3_AB1 (VDC51.GR3_AB1)
|
---|
| 704 | #define VDC51GR3_AB2 (VDC51.GR3_AB2)
|
---|
| 705 | #define VDC51GR3_AB3 (VDC51.GR3_AB3)
|
---|
| 706 | #define VDC51GR3_AB4 (VDC51.GR3_AB4)
|
---|
| 707 | #define VDC51GR3_AB5 (VDC51.GR3_AB5)
|
---|
| 708 | #define VDC51GR3_AB6 (VDC51.GR3_AB6)
|
---|
| 709 | #define VDC51GR3_AB7 (VDC51.GR3_AB7)
|
---|
| 710 | #define VDC51GR3_AB8 (VDC51.GR3_AB8)
|
---|
| 711 | #define VDC51GR3_AB9 (VDC51.GR3_AB9)
|
---|
| 712 | #define VDC51GR3_AB10 (VDC51.GR3_AB10)
|
---|
| 713 | #define VDC51GR3_AB11 (VDC51.GR3_AB11)
|
---|
| 714 | #define VDC51GR3_BASE (VDC51.GR3_BASE)
|
---|
| 715 | #define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT)
|
---|
| 716 | #define VDC51GR3_MON (VDC51.GR3_MON)
|
---|
| 717 | #define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE)
|
---|
| 718 | #define VDC51GAM_SW (VDC51.GAM_SW)
|
---|
| 719 | #define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1)
|
---|
| 720 | #define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2)
|
---|
| 721 | #define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3)
|
---|
| 722 | #define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4)
|
---|
| 723 | #define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5)
|
---|
| 724 | #define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6)
|
---|
| 725 | #define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7)
|
---|
| 726 | #define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8)
|
---|
| 727 | #define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9)
|
---|
| 728 | #define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10)
|
---|
| 729 | #define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11)
|
---|
| 730 | #define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12)
|
---|
| 731 | #define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13)
|
---|
| 732 | #define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14)
|
---|
| 733 | #define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15)
|
---|
| 734 | #define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16)
|
---|
| 735 | #define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1)
|
---|
| 736 | #define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2)
|
---|
| 737 | #define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3)
|
---|
| 738 | #define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4)
|
---|
| 739 | #define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5)
|
---|
| 740 | #define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6)
|
---|
| 741 | #define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7)
|
---|
| 742 | #define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8)
|
---|
| 743 | #define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE)
|
---|
| 744 | #define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1)
|
---|
| 745 | #define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2)
|
---|
| 746 | #define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3)
|
---|
| 747 | #define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4)
|
---|
| 748 | #define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5)
|
---|
| 749 | #define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6)
|
---|
| 750 | #define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7)
|
---|
| 751 | #define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8)
|
---|
| 752 | #define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9)
|
---|
| 753 | #define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10)
|
---|
| 754 | #define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11)
|
---|
| 755 | #define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12)
|
---|
| 756 | #define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13)
|
---|
| 757 | #define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14)
|
---|
| 758 | #define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15)
|
---|
| 759 | #define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16)
|
---|
| 760 | #define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1)
|
---|
| 761 | #define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2)
|
---|
| 762 | #define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3)
|
---|
| 763 | #define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4)
|
---|
| 764 | #define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5)
|
---|
| 765 | #define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6)
|
---|
| 766 | #define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7)
|
---|
| 767 | #define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8)
|
---|
| 768 | #define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE)
|
---|
| 769 | #define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1)
|
---|
| 770 | #define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2)
|
---|
| 771 | #define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3)
|
---|
| 772 | #define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4)
|
---|
| 773 | #define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5)
|
---|
| 774 | #define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6)
|
---|
| 775 | #define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7)
|
---|
| 776 | #define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8)
|
---|
| 777 | #define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9)
|
---|
| 778 | #define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10)
|
---|
| 779 | #define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11)
|
---|
| 780 | #define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12)
|
---|
| 781 | #define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13)
|
---|
| 782 | #define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14)
|
---|
| 783 | #define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15)
|
---|
| 784 | #define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16)
|
---|
| 785 | #define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1)
|
---|
| 786 | #define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2)
|
---|
| 787 | #define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3)
|
---|
| 788 | #define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4)
|
---|
| 789 | #define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5)
|
---|
| 790 | #define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6)
|
---|
| 791 | #define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7)
|
---|
| 792 | #define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8)
|
---|
| 793 | #define VDC51TCON_UPDATE (VDC51.TCON_UPDATE)
|
---|
| 794 | #define VDC51TCON_TIM (VDC51.TCON_TIM)
|
---|
| 795 | #define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1)
|
---|
| 796 | #define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2)
|
---|
| 797 | #define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1)
|
---|
| 798 | #define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2)
|
---|
| 799 | #define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1)
|
---|
| 800 | #define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2)
|
---|
| 801 | #define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1)
|
---|
| 802 | #define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2)
|
---|
| 803 | #define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1)
|
---|
| 804 | #define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2)
|
---|
| 805 | #define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1)
|
---|
| 806 | #define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2)
|
---|
| 807 | #define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1)
|
---|
| 808 | #define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2)
|
---|
| 809 | #define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE)
|
---|
| 810 | #define VDC51OUT_UPDATE (VDC51.OUT_UPDATE)
|
---|
| 811 | #define VDC51OUT_SET (VDC51.OUT_SET)
|
---|
| 812 | #define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1)
|
---|
| 813 | #define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2)
|
---|
| 814 | #define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST)
|
---|
| 815 | #define VDC51OUT_PDTHA (VDC51.OUT_PDTHA)
|
---|
| 816 | #define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE)
|
---|
| 817 | #define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1)
|
---|
| 818 | #define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2)
|
---|
| 819 | #define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3)
|
---|
| 820 | #define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4)
|
---|
| 821 | #define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5)
|
---|
| 822 | #define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6)
|
---|
| 823 | #define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK)
|
---|
| 824 | #define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT)
|
---|
| 825 | #define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE)
|
---|
| 826 | #define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1)
|
---|
| 827 | #define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2)
|
---|
| 828 | #define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3)
|
---|
| 829 | #define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4)
|
---|
| 830 | #define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5)
|
---|
| 831 | #define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6)
|
---|
| 832 | #define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7)
|
---|
| 833 | #define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9)
|
---|
| 834 | #define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0)
|
---|
| 835 | #define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT)
|
---|
| 836 | #define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1)
|
---|
| 837 | #define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2)
|
---|
| 838 | #define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3)
|
---|
| 839 | #define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4)
|
---|
| 840 | #define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5)
|
---|
| 841 | #define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6)
|
---|
| 842 | #define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7)
|
---|
| 843 | #define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1)
|
---|
| 844 | #define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2)
|
---|
| 845 | #define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3)
|
---|
| 846 | #define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4)
|
---|
| 847 | #define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5)
|
---|
| 848 | #define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6)
|
---|
| 849 | #define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7)
|
---|
| 850 | #define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8)
|
---|
| 851 | #define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1)
|
---|
| 852 | #define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE)
|
---|
| 853 | #define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1)
|
---|
| 854 | #define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2)
|
---|
| 855 | #define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3)
|
---|
| 856 | #define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4)
|
---|
| 857 | #define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5)
|
---|
| 858 | #define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6)
|
---|
| 859 | #define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7)
|
---|
| 860 | #define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8)
|
---|
| 861 | #define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9)
|
---|
| 862 | #define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10)
|
---|
| 863 | #define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11)
|
---|
| 864 | #define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1)
|
---|
| 865 | #define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0)
|
---|
| 866 | #define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1)
|
---|
| 867 | #define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2)
|
---|
| 868 | #define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3)
|
---|
| 869 | #define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD)
|
---|
| 870 | #define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT)
|
---|
| 871 | #define VDC51GR1_UPDATE (VDC51.GR1_UPDATE)
|
---|
| 872 | #define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD)
|
---|
| 873 | #define VDC51GR1_FLM1 (VDC51.GR1_FLM1)
|
---|
| 874 | #define VDC51GR1_FLM2 (VDC51.GR1_FLM2)
|
---|
| 875 | #define VDC51GR1_FLM3 (VDC51.GR1_FLM3)
|
---|
| 876 | #define VDC51GR1_FLM4 (VDC51.GR1_FLM4)
|
---|
| 877 | #define VDC51GR1_FLM5 (VDC51.GR1_FLM5)
|
---|
| 878 | #define VDC51GR1_FLM6 (VDC51.GR1_FLM6)
|
---|
| 879 | #define VDC51GR1_AB1 (VDC51.GR1_AB1)
|
---|
| 880 | #define VDC51GR1_AB2 (VDC51.GR1_AB2)
|
---|
| 881 | #define VDC51GR1_AB3 (VDC51.GR1_AB3)
|
---|
| 882 | #define VDC51GR1_AB4 (VDC51.GR1_AB4)
|
---|
| 883 | #define VDC51GR1_AB5 (VDC51.GR1_AB5)
|
---|
| 884 | #define VDC51GR1_AB6 (VDC51.GR1_AB6)
|
---|
| 885 | #define VDC51GR1_AB7 (VDC51.GR1_AB7)
|
---|
| 886 | #define VDC51GR1_AB8 (VDC51.GR1_AB8)
|
---|
| 887 | #define VDC51GR1_AB9 (VDC51.GR1_AB9)
|
---|
| 888 | #define VDC51GR1_AB10 (VDC51.GR1_AB10)
|
---|
| 889 | #define VDC51GR1_AB11 (VDC51.GR1_AB11)
|
---|
| 890 | #define VDC51GR1_BASE (VDC51.GR1_BASE)
|
---|
| 891 | #define VDC51GR1_CLUT (VDC51.GR1_CLUT)
|
---|
| 892 | #define VDC51GR1_MON (VDC51.GR1_MON)
|
---|
| 893 | #define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE)
|
---|
| 894 | #define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET)
|
---|
| 895 | #define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1)
|
---|
| 896 | #define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2)
|
---|
| 897 | #define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3)
|
---|
| 898 | #define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1)
|
---|
| 899 | #define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2)
|
---|
| 900 | #define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3)
|
---|
| 901 | #define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4)
|
---|
| 902 | #define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5)
|
---|
| 903 | #define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6)
|
---|
| 904 | #define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1)
|
---|
| 905 | #define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2)
|
---|
| 906 | #define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE)
|
---|
| 907 | #define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0)
|
---|
| 908 | #define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1)
|
---|
| 909 | #define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0)
|
---|
| 910 | #define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1)
|
---|
| 911 | #define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0)
|
---|
| 912 | #define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1)
|
---|
| 913 | #define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE)
|
---|
| 914 | #define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1)
|
---|
| 915 | #define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2)
|
---|
| 916 | #define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3)
|
---|
| 917 | #define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4)
|
---|
| 918 | #define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5)
|
---|
| 919 | #define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6)
|
---|
| 920 | #define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7)
|
---|
| 921 | #define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE)
|
---|
| 922 | #define VDC51GR_VIN_MON (VDC51.GR_VIN_MON)
|
---|
| 923 | #define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE)
|
---|
| 924 | #define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1)
|
---|
| 925 | #define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2)
|
---|
| 926 | #define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3)
|
---|
| 927 | #define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4)
|
---|
| 928 | #define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5)
|
---|
| 929 | #define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6)
|
---|
| 930 | #define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7)
|
---|
| 931 | #define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1)
|
---|
| 932 | #define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2)
|
---|
| 933 | #define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3)
|
---|
| 934 | #define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7)
|
---|
| 935 | #define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1)
|
---|
| 936 | #define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2)
|
---|
| 937 | #define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3)
|
---|
| 938 | #define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8)
|
---|
| 939 | #define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1)
|
---|
| 940 | #define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE)
|
---|
| 941 | #define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1)
|
---|
| 942 | #define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2)
|
---|
| 943 | #define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3)
|
---|
| 944 | #define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4)
|
---|
| 945 | #define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5)
|
---|
| 946 | #define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6)
|
---|
| 947 | #define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7)
|
---|
| 948 | #define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE)
|
---|
| 949 | #define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD)
|
---|
| 950 | #define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1)
|
---|
| 951 | #define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2)
|
---|
| 952 | #define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3)
|
---|
| 953 | #define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4)
|
---|
| 954 | #define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5)
|
---|
| 955 | #define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6)
|
---|
| 956 | #define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1)
|
---|
| 957 | #define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2)
|
---|
| 958 | #define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3)
|
---|
| 959 | #define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7)
|
---|
| 960 | #define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8)
|
---|
| 961 | #define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9)
|
---|
| 962 | #define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10)
|
---|
| 963 | #define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11)
|
---|
| 964 | #define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE)
|
---|
| 965 | #define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT)
|
---|
| 966 | #define VDC51GR_OIR_MON (VDC51.GR_OIR_MON)
|
---|
| 967 |
|
---|
| 968 | #define VDC5_IMGCNT_NR_CNT0_COUNT (2)
|
---|
| 969 | #define VDC5_SC0_SCL0_FRC1_COUNT (7)
|
---|
| 970 | #define VDC5_SC0_SCL0_DS1_COUNT (7)
|
---|
| 971 | #define VDC5_SC0_SCL0_US1_COUNT (8)
|
---|
| 972 | #define VDC5_SC0_SCL1_WR1_COUNT (4)
|
---|
| 973 | #define VDC5_SC0_SCL1_PBUF0_COUNT (4)
|
---|
| 974 | #define VDC5_GR0_FLM1_COUNT (6)
|
---|
| 975 | #define VDC5_GR0_AB1_COUNT (3)
|
---|
| 976 | #define VDC5_ADJ0_ENH_TIM1_COUNT (3)
|
---|
| 977 | #define VDC5_ADJ0_ENH_SHP1_COUNT (6)
|
---|
| 978 | #define VDC5_ADJ0_ENH_LTI1_COUNT (2)
|
---|
| 979 | #define VDC5_GR2_FLM1_COUNT (6)
|
---|
| 980 | #define VDC5_GR2_AB1_COUNT (3)
|
---|
| 981 | #define VDC5_GR3_FLM1_COUNT (6)
|
---|
| 982 | #define VDC5_GR3_AB1_COUNT (3)
|
---|
| 983 | #define VDC5_GAM_G_LUT1_COUNT (16)
|
---|
| 984 | #define VDC5_GAM_G_AREA1_COUNT (8)
|
---|
| 985 | #define VDC5_GAM_B_LUT1_COUNT (16)
|
---|
| 986 | #define VDC5_GAM_B_AREA1_COUNT (8)
|
---|
| 987 | #define VDC5_GAM_R_LUT1_COUNT (16)
|
---|
| 988 | #define VDC5_GAM_R_AREA1_COUNT (8)
|
---|
| 989 | #define VDC5_TCON_TIM_STVA1_COUNT (2)
|
---|
| 990 | #define VDC5_TCON_TIM_STVB1_COUNT (2)
|
---|
| 991 | #define VDC5_TCON_TIM_STH1_COUNT (2)
|
---|
| 992 | #define VDC5_TCON_TIM_STB1_COUNT (2)
|
---|
| 993 | #define VDC5_TCON_TIM_CPV1_COUNT (2)
|
---|
| 994 | #define VDC5_TCON_TIM_POLA1_COUNT (2)
|
---|
| 995 | #define VDC5_TCON_TIM_POLB1_COUNT (2)
|
---|
| 996 | #define VDC5_OUT_BRIGHT1_COUNT (2)
|
---|
| 997 | #define VDC5_SYSCNT_INT1_COUNT (6)
|
---|
| 998 | #define VDC5_SC1_SCL0_FRC1_COUNT (7)
|
---|
| 999 | #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7)
|
---|
| 1000 | #define VDC5_SC1_SC1_SCL0_US1_COUNT (8)
|
---|
| 1001 | #define VDC5_SC1_SCL1_WR1_COUNT (4)
|
---|
| 1002 | #define VDC5_SC1_SCL1_PBUF0_COUNT (4)
|
---|
| 1003 | #define VDC5_GR1_FLM1_COUNT (6)
|
---|
| 1004 | #define VDC5_GR1_AB1_COUNT (3)
|
---|
| 1005 | #define VDC5_ADJ1_ENH_TIM1_COUNT (3)
|
---|
| 1006 | #define VDC5_ADJ1_ENH_SHP1_COUNT (6)
|
---|
| 1007 | #define VDC5_ADJ1_ENH_LTI1_COUNT (2)
|
---|
| 1008 | #define VDC5_GR_VIN_AB1_COUNT (7)
|
---|
| 1009 | #define VDC5_OIR_SCL0_FRC1_COUNT (7)
|
---|
| 1010 | #define VDC5_OIR_SCL0_DS1_COUNT (3)
|
---|
| 1011 | #define VDC5_OIR_SCL1_WR1_COUNT (4)
|
---|
| 1012 | #define VDC5_GR_OIR_FLM1_COUNT (6)
|
---|
| 1013 | #define VDC5_GR_OIR_AB1_COUNT (3)
|
---|
| 1014 |
|
---|
| 1015 |
|
---|
| 1016 | typedef struct st_vdc5
|
---|
| 1017 | {
|
---|
| 1018 | /* VDC5 */
|
---|
| 1019 | volatile uint32_t INP_UPDATE; /* INP_UPDATE */
|
---|
| 1020 | volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
|
---|
| 1021 | volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
|
---|
| 1022 | volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
|
---|
| 1023 | volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
|
---|
| 1024 | volatile uint8_t dummy1[108]; /* */
|
---|
| 1025 | volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
|
---|
| 1026 |
|
---|
| 1027 | /* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */
|
---|
| 1028 | volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
|
---|
| 1029 | volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
|
---|
| 1030 | volatile uint8_t dummy2[20]; /* */
|
---|
| 1031 | volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
|
---|
| 1032 | volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
|
---|
| 1033 | volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
|
---|
| 1034 | volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
|
---|
| 1035 | volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
|
---|
| 1036 | volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
|
---|
| 1037 | volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
|
---|
| 1038 | volatile uint8_t dummy3[4]; /* */
|
---|
| 1039 | volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
|
---|
| 1040 | volatile uint8_t dummy4[60]; /* */
|
---|
| 1041 |
|
---|
| 1042 | /* start of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 1043 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
|
---|
| 1044 |
|
---|
| 1045 | /* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */
|
---|
| 1046 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
|
---|
| 1047 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
|
---|
| 1048 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
|
---|
| 1049 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
|
---|
| 1050 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
|
---|
| 1051 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
|
---|
| 1052 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
|
---|
| 1053 | volatile uint8_t dummy5[4]; /* */
|
---|
| 1054 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
|
---|
| 1055 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
|
---|
| 1056 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
|
---|
| 1057 |
|
---|
| 1058 | /* #define VDC5_SC0_SCL0_DS1_COUNT (7) */
|
---|
| 1059 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
|
---|
| 1060 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
|
---|
| 1061 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
|
---|
| 1062 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
|
---|
| 1063 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
|
---|
| 1064 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
|
---|
| 1065 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
|
---|
| 1066 |
|
---|
| 1067 | /* #define VDC5_SC0_SCL0_US1_COUNT (8) */
|
---|
| 1068 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
|
---|
| 1069 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
|
---|
| 1070 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
|
---|
| 1071 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
|
---|
| 1072 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
|
---|
| 1073 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
|
---|
| 1074 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
|
---|
| 1075 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
|
---|
| 1076 | volatile uint8_t dummy6[4]; /* */
|
---|
| 1077 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
|
---|
| 1078 | volatile uint8_t dummy7[16]; /* */
|
---|
| 1079 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
|
---|
| 1080 | volatile uint8_t dummy8[4]; /* */
|
---|
| 1081 |
|
---|
| 1082 | /* #define VDC5_SC0_SCL1_WR1_COUNT (4) */
|
---|
| 1083 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
|
---|
| 1084 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
|
---|
| 1085 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
|
---|
| 1086 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
|
---|
| 1087 | volatile uint8_t dummy9[4]; /* */
|
---|
| 1088 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
|
---|
| 1089 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
|
---|
| 1090 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
|
---|
| 1091 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
|
---|
| 1092 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
|
---|
| 1093 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
|
---|
| 1094 |
|
---|
| 1095 | /* end of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 1096 | volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
|
---|
| 1097 | volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
|
---|
| 1098 |
|
---|
| 1099 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 1100 |
|
---|
| 1101 | /* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */
|
---|
| 1102 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
|
---|
| 1103 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
|
---|
| 1104 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
|
---|
| 1105 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
|
---|
| 1106 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
|
---|
| 1107 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
|
---|
| 1108 |
|
---|
| 1109 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 1110 | volatile uint8_t dummy10[44]; /* */
|
---|
| 1111 |
|
---|
| 1112 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 1113 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
|
---|
| 1114 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
|
---|
| 1115 |
|
---|
| 1116 | /* #define VDC5_GR0_FLM1_COUNT (6) */
|
---|
| 1117 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
|
---|
| 1118 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
|
---|
| 1119 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
|
---|
| 1120 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
|
---|
| 1121 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
|
---|
| 1122 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
|
---|
| 1123 |
|
---|
| 1124 | /* #define VDC5_GR0_AB1_COUNT (3) */
|
---|
| 1125 | volatile uint32_t GR0_AB1; /* GR0_AB1 */
|
---|
| 1126 | volatile uint32_t GR0_AB2; /* GR0_AB2 */
|
---|
| 1127 | volatile uint32_t GR0_AB3; /* GR0_AB3 */
|
---|
| 1128 |
|
---|
| 1129 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 1130 | volatile uint8_t dummy11[12]; /* */
|
---|
| 1131 |
|
---|
| 1132 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1133 | volatile uint32_t GR0_AB7; /* GR0_AB7 */
|
---|
| 1134 | volatile uint32_t GR0_AB8; /* GR0_AB8 */
|
---|
| 1135 | volatile uint32_t GR0_AB9; /* GR0_AB9 */
|
---|
| 1136 | volatile uint32_t GR0_AB10; /* GR0_AB10 */
|
---|
| 1137 | volatile uint32_t GR0_AB11; /* GR0_AB11 */
|
---|
| 1138 | volatile uint32_t GR0_BASE; /* GR0_BASE */
|
---|
| 1139 |
|
---|
| 1140 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1141 | volatile uint32_t GR0_CLUT; /* GR0_CLUT */
|
---|
| 1142 | volatile uint8_t dummy12[44]; /* */
|
---|
| 1143 |
|
---|
| 1144 | /* start of struct st_vdc5_from_adj0_update */
|
---|
| 1145 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
|
---|
| 1146 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
|
---|
| 1147 |
|
---|
| 1148 | /* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */
|
---|
| 1149 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
|
---|
| 1150 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
|
---|
| 1151 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
|
---|
| 1152 |
|
---|
| 1153 | /* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */
|
---|
| 1154 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
|
---|
| 1155 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
|
---|
| 1156 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
|
---|
| 1157 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
|
---|
| 1158 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
|
---|
| 1159 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
|
---|
| 1160 |
|
---|
| 1161 | /* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */
|
---|
| 1162 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
|
---|
| 1163 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
|
---|
| 1164 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
|
---|
| 1165 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
|
---|
| 1166 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
|
---|
| 1167 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
|
---|
| 1168 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
|
---|
| 1169 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
|
---|
| 1170 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
|
---|
| 1171 |
|
---|
| 1172 | /* end of struct st_vdc5_from_adj0_update */
|
---|
| 1173 | volatile uint8_t dummy13[48]; /* */
|
---|
| 1174 |
|
---|
| 1175 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 1176 | volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
|
---|
| 1177 | volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
|
---|
| 1178 |
|
---|
| 1179 | /* #define VDC5_GR2_FLM1_COUNT (6) */
|
---|
| 1180 | volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
|
---|
| 1181 | volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
|
---|
| 1182 | volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
|
---|
| 1183 | volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
|
---|
| 1184 | volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
|
---|
| 1185 | volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
|
---|
| 1186 |
|
---|
| 1187 | /* #define VDC5_GR2_AB1_COUNT (3) */
|
---|
| 1188 | volatile uint32_t GR2_AB1; /* GR2_AB1 */
|
---|
| 1189 | volatile uint32_t GR2_AB2; /* GR2_AB2 */
|
---|
| 1190 | volatile uint32_t GR2_AB3; /* GR2_AB3 */
|
---|
| 1191 |
|
---|
| 1192 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 1193 | volatile uint32_t GR2_AB4; /* GR2_AB4 */
|
---|
| 1194 | volatile uint32_t GR2_AB5; /* GR2_AB5 */
|
---|
| 1195 | volatile uint32_t GR2_AB6; /* GR2_AB6 */
|
---|
| 1196 |
|
---|
| 1197 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1198 | volatile uint32_t GR2_AB7; /* GR2_AB7 */
|
---|
| 1199 | volatile uint32_t GR2_AB8; /* GR2_AB8 */
|
---|
| 1200 | volatile uint32_t GR2_AB9; /* GR2_AB9 */
|
---|
| 1201 | volatile uint32_t GR2_AB10; /* GR2_AB10 */
|
---|
| 1202 | volatile uint32_t GR2_AB11; /* GR2_AB11 */
|
---|
| 1203 | volatile uint32_t GR2_BASE; /* GR2_BASE */
|
---|
| 1204 |
|
---|
| 1205 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1206 | volatile uint32_t GR2_CLUT; /* GR2_CLUT */
|
---|
| 1207 | volatile uint32_t GR2_MON; /* GR2_MON */
|
---|
| 1208 | volatile uint8_t dummy14[40]; /* */
|
---|
| 1209 |
|
---|
| 1210 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 1211 | volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
|
---|
| 1212 | volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
|
---|
| 1213 |
|
---|
| 1214 | /* #define VDC5_GR3_FLM1_COUNT (6) */
|
---|
| 1215 | volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
|
---|
| 1216 | volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
|
---|
| 1217 | volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
|
---|
| 1218 | volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
|
---|
| 1219 | volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
|
---|
| 1220 | volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
|
---|
| 1221 |
|
---|
| 1222 | /* #define VDC5_GR3_AB1_COUNT (3) */
|
---|
| 1223 | volatile uint32_t GR3_AB1; /* GR3_AB1 */
|
---|
| 1224 | volatile uint32_t GR3_AB2; /* GR3_AB2 */
|
---|
| 1225 | volatile uint32_t GR3_AB3; /* GR3_AB3 */
|
---|
| 1226 |
|
---|
| 1227 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 1228 | volatile uint32_t GR3_AB4; /* GR3_AB4 */
|
---|
| 1229 | volatile uint32_t GR3_AB5; /* GR3_AB5 */
|
---|
| 1230 | volatile uint32_t GR3_AB6; /* GR3_AB6 */
|
---|
| 1231 |
|
---|
| 1232 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1233 | volatile uint32_t GR3_AB7; /* GR3_AB7 */
|
---|
| 1234 | volatile uint32_t GR3_AB8; /* GR3_AB8 */
|
---|
| 1235 | volatile uint32_t GR3_AB9; /* GR3_AB9 */
|
---|
| 1236 | volatile uint32_t GR3_AB10; /* GR3_AB10 */
|
---|
| 1237 | volatile uint32_t GR3_AB11; /* GR3_AB11 */
|
---|
| 1238 | volatile uint32_t GR3_BASE; /* GR3_BASE */
|
---|
| 1239 |
|
---|
| 1240 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1241 | volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
|
---|
| 1242 | volatile uint32_t GR3_MON; /* GR3_MON */
|
---|
| 1243 | volatile uint8_t dummy15[40]; /* */
|
---|
| 1244 | volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
|
---|
| 1245 | volatile uint32_t GAM_SW; /* GAM_SW */
|
---|
| 1246 |
|
---|
| 1247 | /* #define VDC5_GAM_G_LUT1_COUNT (16) */
|
---|
| 1248 | volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
|
---|
| 1249 | volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
|
---|
| 1250 | volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
|
---|
| 1251 | volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
|
---|
| 1252 | volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
|
---|
| 1253 | volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
|
---|
| 1254 | volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
|
---|
| 1255 | volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
|
---|
| 1256 | volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
|
---|
| 1257 | volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
|
---|
| 1258 | volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
|
---|
| 1259 | volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
|
---|
| 1260 | volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
|
---|
| 1261 | volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
|
---|
| 1262 | volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
|
---|
| 1263 | volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
|
---|
| 1264 |
|
---|
| 1265 | /* #define VDC5_GAM_G_AREA1_COUNT (8) */
|
---|
| 1266 | volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
|
---|
| 1267 | volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
|
---|
| 1268 | volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
|
---|
| 1269 | volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
|
---|
| 1270 | volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
|
---|
| 1271 | volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
|
---|
| 1272 | volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
|
---|
| 1273 | volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
|
---|
| 1274 | volatile uint8_t dummy16[24]; /* */
|
---|
| 1275 | volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
|
---|
| 1276 | volatile uint8_t dummy17[4]; /* */
|
---|
| 1277 |
|
---|
| 1278 | /* #define VDC5_GAM_B_LUT1_COUNT (16) */
|
---|
| 1279 | volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
|
---|
| 1280 | volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
|
---|
| 1281 | volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
|
---|
| 1282 | volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
|
---|
| 1283 | volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
|
---|
| 1284 | volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
|
---|
| 1285 | volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
|
---|
| 1286 | volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
|
---|
| 1287 | volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
|
---|
| 1288 | volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
|
---|
| 1289 | volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
|
---|
| 1290 | volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
|
---|
| 1291 | volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
|
---|
| 1292 | volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
|
---|
| 1293 | volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
|
---|
| 1294 | volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
|
---|
| 1295 |
|
---|
| 1296 | /* #define VDC5_GAM_B_AREA1_COUNT (8) */
|
---|
| 1297 | volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
|
---|
| 1298 | volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
|
---|
| 1299 | volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
|
---|
| 1300 | volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
|
---|
| 1301 | volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
|
---|
| 1302 | volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
|
---|
| 1303 | volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
|
---|
| 1304 | volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
|
---|
| 1305 | volatile uint8_t dummy18[24]; /* */
|
---|
| 1306 | volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
|
---|
| 1307 | volatile uint8_t dummy19[4]; /* */
|
---|
| 1308 |
|
---|
| 1309 | /* #define VDC5_GAM_R_LUT1_COUNT (16) */
|
---|
| 1310 | volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
|
---|
| 1311 | volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
|
---|
| 1312 | volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
|
---|
| 1313 | volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
|
---|
| 1314 | volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
|
---|
| 1315 | volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
|
---|
| 1316 | volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
|
---|
| 1317 | volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
|
---|
| 1318 | volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
|
---|
| 1319 | volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
|
---|
| 1320 | volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
|
---|
| 1321 | volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
|
---|
| 1322 | volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
|
---|
| 1323 | volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
|
---|
| 1324 | volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
|
---|
| 1325 | volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
|
---|
| 1326 |
|
---|
| 1327 | /* #define VDC5_GAM_R_AREA1_COUNT (8) */
|
---|
| 1328 | volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
|
---|
| 1329 | volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
|
---|
| 1330 | volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
|
---|
| 1331 | volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
|
---|
| 1332 | volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
|
---|
| 1333 | volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
|
---|
| 1334 | volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
|
---|
| 1335 | volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
|
---|
| 1336 | volatile uint8_t dummy20[24]; /* */
|
---|
| 1337 | volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
|
---|
| 1338 | volatile uint32_t TCON_TIM; /* TCON_TIM */
|
---|
| 1339 |
|
---|
| 1340 | /* #define VDC5_TCON_TIM_STVA1_COUNT (2) */
|
---|
| 1341 | volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
|
---|
| 1342 | volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
|
---|
| 1343 |
|
---|
| 1344 | /* #define VDC5_TCON_TIM_STVB1_COUNT (2) */
|
---|
| 1345 | volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
|
---|
| 1346 | volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
|
---|
| 1347 |
|
---|
| 1348 | /* #define VDC5_TCON_TIM_STH1_COUNT (2) */
|
---|
| 1349 | volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
|
---|
| 1350 | volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
|
---|
| 1351 |
|
---|
| 1352 | /* #define VDC5_TCON_TIM_STB1_COUNT (2) */
|
---|
| 1353 | volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
|
---|
| 1354 | volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
|
---|
| 1355 |
|
---|
| 1356 | /* #define VDC5_TCON_TIM_CPV1_COUNT (2) */
|
---|
| 1357 | volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
|
---|
| 1358 | volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
|
---|
| 1359 |
|
---|
| 1360 | /* #define VDC5_TCON_TIM_POLA1_COUNT (2) */
|
---|
| 1361 | volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
|
---|
| 1362 | volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
|
---|
| 1363 |
|
---|
| 1364 | /* #define VDC5_TCON_TIM_POLB1_COUNT (2) */
|
---|
| 1365 | volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
|
---|
| 1366 | volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
|
---|
| 1367 | volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
|
---|
| 1368 | volatile uint8_t dummy21[60]; /* */
|
---|
| 1369 | volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
|
---|
| 1370 | volatile uint32_t OUT_SET; /* OUT_SET */
|
---|
| 1371 |
|
---|
| 1372 | /* #define VDC5_OUT_BRIGHT1_COUNT (2) */
|
---|
| 1373 | volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
|
---|
| 1374 | volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
|
---|
| 1375 | volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
|
---|
| 1376 | volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
|
---|
| 1377 | volatile uint8_t dummy22[12]; /* */
|
---|
| 1378 | volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
|
---|
| 1379 | volatile uint8_t dummy23[88]; /* */
|
---|
| 1380 |
|
---|
| 1381 | /* #define VDC5_SYSCNT_INT1_COUNT (6) */
|
---|
| 1382 | volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
|
---|
| 1383 | volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
|
---|
| 1384 | volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
|
---|
| 1385 | volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
|
---|
| 1386 | volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
|
---|
| 1387 | volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
|
---|
| 1388 | volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
|
---|
| 1389 | volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
|
---|
| 1390 | volatile uint8_t dummy24[356]; /* */
|
---|
| 1391 |
|
---|
| 1392 | /* start of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 1393 | volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
|
---|
| 1394 |
|
---|
| 1395 | /* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */
|
---|
| 1396 | volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
|
---|
| 1397 | volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
|
---|
| 1398 | volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
|
---|
| 1399 | volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
|
---|
| 1400 | volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
|
---|
| 1401 | volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
|
---|
| 1402 | volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
|
---|
| 1403 | volatile uint8_t dummy25[4]; /* */
|
---|
| 1404 | volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
|
---|
| 1405 | volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
|
---|
| 1406 | volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
|
---|
| 1407 |
|
---|
| 1408 | /* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */
|
---|
| 1409 | volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
|
---|
| 1410 | volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
|
---|
| 1411 | volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
|
---|
| 1412 | volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
|
---|
| 1413 | volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
|
---|
| 1414 | volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
|
---|
| 1415 | volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
|
---|
| 1416 |
|
---|
| 1417 | /* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */
|
---|
| 1418 | volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
|
---|
| 1419 | volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
|
---|
| 1420 | volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
|
---|
| 1421 | volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
|
---|
| 1422 | volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
|
---|
| 1423 | volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
|
---|
| 1424 | volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
|
---|
| 1425 | volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
|
---|
| 1426 | volatile uint8_t dummy26[4]; /* */
|
---|
| 1427 | volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
|
---|
| 1428 | volatile uint8_t dummy27[16]; /* */
|
---|
| 1429 | volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
|
---|
| 1430 | volatile uint8_t dummy28[4]; /* */
|
---|
| 1431 |
|
---|
| 1432 | /* #define VDC5_SC1_SCL1_WR1_COUNT (4) */
|
---|
| 1433 | volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
|
---|
| 1434 | volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
|
---|
| 1435 | volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
|
---|
| 1436 | volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
|
---|
| 1437 | volatile uint8_t dummy29[4]; /* */
|
---|
| 1438 | volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
|
---|
| 1439 | volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
|
---|
| 1440 | volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
|
---|
| 1441 | volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
|
---|
| 1442 | volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
|
---|
| 1443 | volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
|
---|
| 1444 |
|
---|
| 1445 | /* end of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 1446 | volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
|
---|
| 1447 | volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
|
---|
| 1448 |
|
---|
| 1449 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 1450 |
|
---|
| 1451 | /* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */
|
---|
| 1452 | volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
|
---|
| 1453 | volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
|
---|
| 1454 | volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
|
---|
| 1455 | volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
|
---|
| 1456 | volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
|
---|
| 1457 | volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
|
---|
| 1458 |
|
---|
| 1459 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 1460 | volatile uint8_t dummy30[44]; /* */
|
---|
| 1461 |
|
---|
| 1462 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 1463 | volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
|
---|
| 1464 | volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
|
---|
| 1465 |
|
---|
| 1466 | /* #define VDC5_GR1_FLM1_COUNT (6) */
|
---|
| 1467 | volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
|
---|
| 1468 | volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
|
---|
| 1469 | volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
|
---|
| 1470 | volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
|
---|
| 1471 | volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
|
---|
| 1472 | volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
|
---|
| 1473 |
|
---|
| 1474 | /* #define VDC5_GR1_AB1_COUNT (3) */
|
---|
| 1475 | volatile uint32_t GR1_AB1; /* GR1_AB1 */
|
---|
| 1476 | volatile uint32_t GR1_AB2; /* GR1_AB2 */
|
---|
| 1477 | volatile uint32_t GR1_AB3; /* GR1_AB3 */
|
---|
| 1478 |
|
---|
| 1479 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 1480 | volatile uint32_t GR1_AB4; /* GR1_AB4 */
|
---|
| 1481 | volatile uint32_t GR1_AB5; /* GR1_AB5 */
|
---|
| 1482 | volatile uint32_t GR1_AB6; /* GR1_AB6 */
|
---|
| 1483 |
|
---|
| 1484 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1485 | volatile uint32_t GR1_AB7; /* GR1_AB7 */
|
---|
| 1486 | volatile uint32_t GR1_AB8; /* GR1_AB8 */
|
---|
| 1487 | volatile uint32_t GR1_AB9; /* GR1_AB9 */
|
---|
| 1488 | volatile uint32_t GR1_AB10; /* GR1_AB10 */
|
---|
| 1489 | volatile uint32_t GR1_AB11; /* GR1_AB11 */
|
---|
| 1490 | volatile uint32_t GR1_BASE; /* GR1_BASE */
|
---|
| 1491 |
|
---|
| 1492 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 1493 | volatile uint32_t GR1_CLUT; /* GR1_CLUT */
|
---|
| 1494 | volatile uint32_t GR1_MON; /* GR1_MON */
|
---|
| 1495 | volatile uint8_t dummy31[40]; /* */
|
---|
| 1496 |
|
---|
| 1497 | /* start of struct st_vdc5_from_adj0_update */
|
---|
| 1498 | volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
|
---|
| 1499 | volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
|
---|
| 1500 |
|
---|
| 1501 | /* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */
|
---|
| 1502 | volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
|
---|
| 1503 | volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
|
---|
| 1504 | volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
|
---|
| 1505 |
|
---|
| 1506 | /* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */
|
---|
| 1507 | volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
|
---|
| 1508 | volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
|
---|
| 1509 | volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
|
---|
| 1510 | volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
|
---|
| 1511 | volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
|
---|
| 1512 | volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
|
---|
| 1513 |
|
---|
| 1514 | /* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */
|
---|
| 1515 | volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
|
---|
| 1516 | volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
|
---|
| 1517 | volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
|
---|
| 1518 | volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
|
---|
| 1519 | volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
|
---|
| 1520 | volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
|
---|
| 1521 | volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
|
---|
| 1522 | volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
|
---|
| 1523 | volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
|
---|
| 1524 |
|
---|
| 1525 | /* end of struct st_vdc5_from_adj0_update */
|
---|
| 1526 | volatile uint8_t dummy32[48]; /* */
|
---|
| 1527 | volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
|
---|
| 1528 | volatile uint8_t dummy33[28]; /* */
|
---|
| 1529 |
|
---|
| 1530 | /* #define VDC5_GR_VIN_AB1_COUNT (7) */
|
---|
| 1531 | volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
|
---|
| 1532 | volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
|
---|
| 1533 | volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
|
---|
| 1534 | volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
|
---|
| 1535 | volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
|
---|
| 1536 | volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
|
---|
| 1537 | volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
|
---|
| 1538 | volatile uint8_t dummy34[16]; /* */
|
---|
| 1539 | volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
|
---|
| 1540 | volatile uint8_t dummy35[4]; /* */
|
---|
| 1541 | volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
|
---|
| 1542 | volatile uint8_t dummy36[40]; /* */
|
---|
| 1543 | volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
|
---|
| 1544 |
|
---|
| 1545 | /* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */
|
---|
| 1546 | volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
|
---|
| 1547 | volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
|
---|
| 1548 | volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
|
---|
| 1549 | volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
|
---|
| 1550 | volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
|
---|
| 1551 | volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
|
---|
| 1552 | volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
|
---|
| 1553 | volatile uint8_t dummy37[12]; /* */
|
---|
| 1554 |
|
---|
| 1555 | /* #define VDC5_OIR_SCL0_DS1_COUNT (3) */
|
---|
| 1556 | volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
|
---|
| 1557 | volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
|
---|
| 1558 | volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
|
---|
| 1559 | volatile uint8_t dummy38[12]; /* */
|
---|
| 1560 | volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
|
---|
| 1561 | volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
|
---|
| 1562 | volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
|
---|
| 1563 | volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
|
---|
| 1564 | volatile uint8_t dummy39[16]; /* */
|
---|
| 1565 | volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
|
---|
| 1566 | volatile uint8_t dummy40[4]; /* */
|
---|
| 1567 | volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
|
---|
| 1568 | volatile uint8_t dummy41[16]; /* */
|
---|
| 1569 | volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
|
---|
| 1570 | volatile uint8_t dummy42[4]; /* */
|
---|
| 1571 |
|
---|
| 1572 | /* #define VDC5_OIR_SCL1_WR1_COUNT (4) */
|
---|
| 1573 | volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
|
---|
| 1574 | volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
|
---|
| 1575 | volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
|
---|
| 1576 | volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
|
---|
| 1577 | volatile uint8_t dummy43[4]; /* */
|
---|
| 1578 | volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
|
---|
| 1579 | volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
|
---|
| 1580 | volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
|
---|
| 1581 | volatile uint8_t dummy44[88]; /* */
|
---|
| 1582 | volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
|
---|
| 1583 | volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
|
---|
| 1584 |
|
---|
| 1585 | /* #define VDC5_GR_OIR_FLM1_COUNT (6) */
|
---|
| 1586 | volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
|
---|
| 1587 | volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
|
---|
| 1588 | volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
|
---|
| 1589 | volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
|
---|
| 1590 | volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
|
---|
| 1591 | volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
|
---|
| 1592 |
|
---|
| 1593 | /* #define VDC5_GR_OIR_AB1_COUNT (3) */
|
---|
| 1594 | volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
|
---|
| 1595 | volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
|
---|
| 1596 | volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
|
---|
| 1597 | volatile uint8_t dummy45[12]; /* */
|
---|
| 1598 | volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
|
---|
| 1599 | volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
|
---|
| 1600 | volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
|
---|
| 1601 | volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
|
---|
| 1602 | volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
|
---|
| 1603 | volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
|
---|
| 1604 | volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
|
---|
| 1605 | volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
|
---|
| 1606 | } r_io_vdc5_t;
|
---|
| 1607 |
|
---|
| 1608 |
|
---|
| 1609 | typedef struct st_vdc5_from_gr0_update
|
---|
| 1610 | {
|
---|
| 1611 |
|
---|
| 1612 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
|
---|
| 1613 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
|
---|
| 1614 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
|
---|
| 1615 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
|
---|
| 1616 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
|
---|
| 1617 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
|
---|
| 1618 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
|
---|
| 1619 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
|
---|
| 1620 | volatile uint32_t GR0_AB1; /* GR0_AB1 */
|
---|
| 1621 | volatile uint32_t GR0_AB2; /* GR0_AB2 */
|
---|
| 1622 | volatile uint32_t GR0_AB3; /* GR0_AB3 */
|
---|
| 1623 | } r_io_vdc5_from_gr0_update_t;
|
---|
| 1624 |
|
---|
| 1625 |
|
---|
| 1626 | typedef struct st_vdc5_from_gr0_ab7
|
---|
| 1627 | {
|
---|
| 1628 |
|
---|
| 1629 | volatile uint32_t GR0_AB7; /* GR0_AB7 */
|
---|
| 1630 | volatile uint32_t GR0_AB8; /* GR0_AB8 */
|
---|
| 1631 | volatile uint32_t GR0_AB9; /* GR0_AB9 */
|
---|
| 1632 | volatile uint32_t GR0_AB10; /* GR0_AB10 */
|
---|
| 1633 | volatile uint32_t GR0_AB11; /* GR0_AB11 */
|
---|
| 1634 | volatile uint32_t GR0_BASE; /* GR0_BASE */
|
---|
| 1635 | } r_io_vdc5_from_gr0_ab7_t;
|
---|
| 1636 |
|
---|
| 1637 |
|
---|
| 1638 | typedef struct st_vdc5_from_adj0_update
|
---|
| 1639 | {
|
---|
| 1640 |
|
---|
| 1641 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
|
---|
| 1642 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
|
---|
| 1643 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
|
---|
| 1644 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
|
---|
| 1645 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
|
---|
| 1646 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
|
---|
| 1647 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
|
---|
| 1648 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
|
---|
| 1649 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
|
---|
| 1650 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
|
---|
| 1651 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
|
---|
| 1652 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
|
---|
| 1653 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
|
---|
| 1654 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
|
---|
| 1655 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
|
---|
| 1656 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
|
---|
| 1657 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
|
---|
| 1658 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
|
---|
| 1659 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
|
---|
| 1660 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
|
---|
| 1661 | } r_io_vdc5_from_adj0_update_t;
|
---|
| 1662 |
|
---|
| 1663 |
|
---|
| 1664 | typedef struct st_vdc5_from_sc0_scl0_update
|
---|
| 1665 | {
|
---|
| 1666 |
|
---|
| 1667 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
|
---|
| 1668 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
|
---|
| 1669 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
|
---|
| 1670 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
|
---|
| 1671 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
|
---|
| 1672 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
|
---|
| 1673 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
|
---|
| 1674 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
|
---|
| 1675 | volatile uint8_t dummy5[4]; /* */
|
---|
| 1676 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
|
---|
| 1677 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
|
---|
| 1678 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
|
---|
| 1679 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
|
---|
| 1680 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
|
---|
| 1681 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
|
---|
| 1682 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
|
---|
| 1683 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
|
---|
| 1684 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
|
---|
| 1685 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
|
---|
| 1686 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
|
---|
| 1687 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
|
---|
| 1688 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
|
---|
| 1689 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
|
---|
| 1690 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
|
---|
| 1691 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
|
---|
| 1692 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
|
---|
| 1693 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
|
---|
| 1694 | volatile uint8_t dummy6[4]; /* */
|
---|
| 1695 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
|
---|
| 1696 | volatile uint8_t dummy7[16]; /* */
|
---|
| 1697 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
|
---|
| 1698 | volatile uint8_t dummy8[4]; /* */
|
---|
| 1699 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
|
---|
| 1700 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
|
---|
| 1701 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
|
---|
| 1702 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
|
---|
| 1703 | volatile uint8_t dummy9[4]; /* */
|
---|
| 1704 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
|
---|
| 1705 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
|
---|
| 1706 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
|
---|
| 1707 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
|
---|
| 1708 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
|
---|
| 1709 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
|
---|
| 1710 | } r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */;
|
---|
| 1711 |
|
---|
| 1712 |
|
---|
| 1713 | typedef struct st_vdc5_from_sc0_scl1_pbuf0
|
---|
| 1714 | {
|
---|
| 1715 |
|
---|
| 1716 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
|
---|
| 1717 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
|
---|
| 1718 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
|
---|
| 1719 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
|
---|
| 1720 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
|
---|
| 1721 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
|
---|
| 1722 | } r_io_vdc5_from_sc0_scl1_pbuf0_t;
|
---|
| 1723 |
|
---|
| 1724 |
|
---|
| 1725 | /* Channel array defines of VDC5 (2)*/
|
---|
| 1726 | #ifdef DECLARE_VDC5_CHANNELS
|
---|
| 1727 | volatile struct st_vdc5* VDC5[ VDC5_COUNT ] =
|
---|
| 1728 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1729 | VDC5_ADDRESS_LIST;
|
---|
| 1730 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1731 | #endif /* DECLARE_VDC5_CHANNELS */
|
---|
| 1732 |
|
---|
| 1733 | #ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS
|
---|
| 1734 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] =
|
---|
| 1735 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1736 | VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST;
|
---|
| 1737 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1738 | #endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */
|
---|
| 1739 |
|
---|
| 1740 | #ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS
|
---|
| 1741 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] =
|
---|
| 1742 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1743 | VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST;
|
---|
| 1744 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1745 | #endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */
|
---|
| 1746 |
|
---|
| 1747 | #ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS
|
---|
| 1748 | volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] =
|
---|
| 1749 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1750 | VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST;
|
---|
| 1751 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1752 | #endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */
|
---|
| 1753 |
|
---|
| 1754 | #ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS
|
---|
| 1755 | volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] =
|
---|
| 1756 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1757 | VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST;
|
---|
| 1758 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1759 | #endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */
|
---|
| 1760 |
|
---|
| 1761 | #ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS
|
---|
| 1762 | volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] =
|
---|
| 1763 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1764 | VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST;
|
---|
| 1765 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1766 | #endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */
|
---|
| 1767 |
|
---|
| 1768 | #ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS
|
---|
| 1769 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] =
|
---|
| 1770 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1771 | VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST;
|
---|
| 1772 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1773 | #endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */
|
---|
| 1774 |
|
---|
| 1775 | #ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS
|
---|
| 1776 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] =
|
---|
| 1777 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 1778 | VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST;
|
---|
| 1779 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 1780 | #endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */
|
---|
| 1781 | /* End of channel array defines of VDC5 (2)*/
|
---|
| 1782 |
|
---|
| 1783 |
|
---|
| 1784 | /* <-SEC M1.10.1 */
|
---|
| 1785 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
|
---|
| 1786 | /* <-QAC 0857 */
|
---|
| 1787 | /* <-QAC 0639 */
|
---|
| 1788 | #endif
|
---|