[429] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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| 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : rspi_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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| 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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| 28 | ******************************************************************************/
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| 29 | #ifndef RSPI_IODEFINE_H
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| 30 | #define RSPI_IODEFINE_H
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| 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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| 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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| 36 | #define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
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| 37 | #define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
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| 38 | #define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
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| 39 | #define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
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| 40 | #define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
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| 41 |
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| 42 |
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| 43 | /* Start of channel array defines of RSPI */
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| 44 |
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| 45 | /* Channel array defines of RSPI */
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| 46 | /*(Sample) value = RSPI[ channel ]->SPCR; */
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| 47 | #define RSPI_COUNT (5)
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| 48 | #define RSPI_ADDRESS_LIST \
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| 49 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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| 50 | &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
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| 51 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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| 52 |
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| 53 | /* End of channel array defines of RSPI */
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| 54 |
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| 55 |
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| 56 | #define SPCR_0 (RSPI0.SPCR)
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| 57 | #define SSLP_0 (RSPI0.SSLP)
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| 58 | #define SPPCR_0 (RSPI0.SPPCR)
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| 59 | #define SPSR_0 (RSPI0.SPSR)
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| 60 | #define SPDR_0 (RSPI0.SPDR.UINT32)
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| 61 | #define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L])
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| 62 | #define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H])
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| 63 | #define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
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| 64 | #define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
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| 65 | #define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
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| 66 | #define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
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| 67 | #define SPSCR_0 (RSPI0.SPSCR)
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| 68 | #define SPSSR_0 (RSPI0.SPSSR)
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| 69 | #define SPBR_0 (RSPI0.SPBR)
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| 70 | #define SPDCR_0 (RSPI0.SPDCR)
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| 71 | #define SPCKD_0 (RSPI0.SPCKD)
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| 72 | #define SSLND_0 (RSPI0.SSLND)
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| 73 | #define SPND_0 (RSPI0.SPND)
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| 74 | #define SPCMD0_0 (RSPI0.SPCMD0)
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| 75 | #define SPCMD1_0 (RSPI0.SPCMD1)
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| 76 | #define SPCMD2_0 (RSPI0.SPCMD2)
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| 77 | #define SPCMD3_0 (RSPI0.SPCMD3)
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| 78 | #define SPBFCR_0 (RSPI0.SPBFCR)
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| 79 | #define SPBFDR_0 (RSPI0.SPBFDR)
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| 80 | #define SPCR_1 (RSPI1.SPCR)
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| 81 | #define SSLP_1 (RSPI1.SSLP)
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| 82 | #define SPPCR_1 (RSPI1.SPPCR)
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| 83 | #define SPSR_1 (RSPI1.SPSR)
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| 84 | #define SPDR_1 (RSPI1.SPDR.UINT32)
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| 85 | #define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L])
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| 86 | #define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H])
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| 87 | #define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
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| 88 | #define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
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| 89 | #define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
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| 90 | #define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
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| 91 | #define SPSCR_1 (RSPI1.SPSCR)
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| 92 | #define SPSSR_1 (RSPI1.SPSSR)
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| 93 | #define SPBR_1 (RSPI1.SPBR)
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| 94 | #define SPDCR_1 (RSPI1.SPDCR)
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| 95 | #define SPCKD_1 (RSPI1.SPCKD)
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| 96 | #define SSLND_1 (RSPI1.SSLND)
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| 97 | #define SPND_1 (RSPI1.SPND)
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| 98 | #define SPCMD0_1 (RSPI1.SPCMD0)
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| 99 | #define SPCMD1_1 (RSPI1.SPCMD1)
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| 100 | #define SPCMD2_1 (RSPI1.SPCMD2)
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| 101 | #define SPCMD3_1 (RSPI1.SPCMD3)
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| 102 | #define SPBFCR_1 (RSPI1.SPBFCR)
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| 103 | #define SPBFDR_1 (RSPI1.SPBFDR)
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| 104 | #define SPCR_2 (RSPI2.SPCR)
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| 105 | #define SSLP_2 (RSPI2.SSLP)
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| 106 | #define SPPCR_2 (RSPI2.SPPCR)
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| 107 | #define SPSR_2 (RSPI2.SPSR)
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| 108 | #define SPDR_2 (RSPI2.SPDR.UINT32)
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| 109 | #define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L])
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| 110 | #define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H])
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| 111 | #define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
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| 112 | #define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
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| 113 | #define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
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| 114 | #define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
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| 115 | #define SPSCR_2 (RSPI2.SPSCR)
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| 116 | #define SPSSR_2 (RSPI2.SPSSR)
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| 117 | #define SPBR_2 (RSPI2.SPBR)
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| 118 | #define SPDCR_2 (RSPI2.SPDCR)
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| 119 | #define SPCKD_2 (RSPI2.SPCKD)
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| 120 | #define SSLND_2 (RSPI2.SSLND)
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| 121 | #define SPND_2 (RSPI2.SPND)
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| 122 | #define SPCMD0_2 (RSPI2.SPCMD0)
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| 123 | #define SPCMD1_2 (RSPI2.SPCMD1)
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| 124 | #define SPCMD2_2 (RSPI2.SPCMD2)
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| 125 | #define SPCMD3_2 (RSPI2.SPCMD3)
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| 126 | #define SPBFCR_2 (RSPI2.SPBFCR)
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| 127 | #define SPBFDR_2 (RSPI2.SPBFDR)
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| 128 | #define SPCR_3 (RSPI3.SPCR)
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| 129 | #define SSLP_3 (RSPI3.SSLP)
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| 130 | #define SPPCR_3 (RSPI3.SPPCR)
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| 131 | #define SPSR_3 (RSPI3.SPSR)
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| 132 | #define SPDR_3 (RSPI3.SPDR.UINT32)
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| 133 | #define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L])
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| 134 | #define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H])
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| 135 | #define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
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| 136 | #define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
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| 137 | #define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
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| 138 | #define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
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| 139 | #define SPSCR_3 (RSPI3.SPSCR)
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| 140 | #define SPSSR_3 (RSPI3.SPSSR)
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| 141 | #define SPBR_3 (RSPI3.SPBR)
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| 142 | #define SPDCR_3 (RSPI3.SPDCR)
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| 143 | #define SPCKD_3 (RSPI3.SPCKD)
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| 144 | #define SSLND_3 (RSPI3.SSLND)
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| 145 | #define SPND_3 (RSPI3.SPND)
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| 146 | #define SPCMD0_3 (RSPI3.SPCMD0)
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| 147 | #define SPCMD1_3 (RSPI3.SPCMD1)
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| 148 | #define SPCMD2_3 (RSPI3.SPCMD2)
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| 149 | #define SPCMD3_3 (RSPI3.SPCMD3)
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| 150 | #define SPBFCR_3 (RSPI3.SPBFCR)
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| 151 | #define SPBFDR_3 (RSPI3.SPBFDR)
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| 152 | #define SPCR_4 (RSPI4.SPCR)
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| 153 | #define SSLP_4 (RSPI4.SSLP)
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| 154 | #define SPPCR_4 (RSPI4.SPPCR)
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| 155 | #define SPSR_4 (RSPI4.SPSR)
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| 156 | #define SPDR_4 (RSPI4.SPDR.UINT32)
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| 157 | #define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L])
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| 158 | #define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H])
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| 159 | #define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
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| 160 | #define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
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| 161 | #define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
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| 162 | #define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
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| 163 | #define SPSCR_4 (RSPI4.SPSCR)
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| 164 | #define SPSSR_4 (RSPI4.SPSSR)
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| 165 | #define SPBR_4 (RSPI4.SPBR)
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| 166 | #define SPDCR_4 (RSPI4.SPDCR)
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| 167 | #define SPCKD_4 (RSPI4.SPCKD)
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| 168 | #define SSLND_4 (RSPI4.SSLND)
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| 169 | #define SPND_4 (RSPI4.SPND)
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| 170 | #define SPCMD0_4 (RSPI4.SPCMD0)
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| 171 | #define SPCMD1_4 (RSPI4.SPCMD1)
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| 172 | #define SPCMD2_4 (RSPI4.SPCMD2)
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| 173 | #define SPCMD3_4 (RSPI4.SPCMD3)
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| 174 | #define SPBFCR_4 (RSPI4.SPBFCR)
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| 175 | #define SPBFDR_4 (RSPI4.SPBFDR)
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| 176 |
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| 177 | #define SPCMD_COUNT (4)
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| 178 |
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| 179 |
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| 180 | typedef struct st_rspi
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| 181 | {
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| 182 | /* RSPI */
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| 183 | volatile uint8_t SPCR; /* SPCR */
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| 184 | volatile uint8_t SSLP; /* SSLP */
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| 185 | volatile uint8_t SPPCR; /* SPPCR */
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| 186 | volatile uint8_t SPSR; /* SPSR */
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| 187 | union iodefine_reg32_t SPDR; /* SPDR */
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| 188 |
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| 189 | volatile uint8_t SPSCR; /* SPSCR */
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| 190 | volatile uint8_t SPSSR; /* SPSSR */
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| 191 | volatile uint8_t SPBR; /* SPBR */
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| 192 | volatile uint8_t SPDCR; /* SPDCR */
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| 193 | volatile uint8_t SPCKD; /* SPCKD */
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| 194 | volatile uint8_t SSLND; /* SSLND */
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| 195 | volatile uint8_t SPND; /* SPND */
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| 196 | volatile uint8_t dummy1[1]; /* */
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| 197 |
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| 198 | /* #define SPCMD_COUNT (4) */
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| 199 | volatile uint16_t SPCMD0; /* SPCMD0 */
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| 200 | volatile uint16_t SPCMD1; /* SPCMD1 */
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| 201 | volatile uint16_t SPCMD2; /* SPCMD2 */
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| 202 | volatile uint16_t SPCMD3; /* SPCMD3 */
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| 203 | volatile uint8_t dummy2[8]; /* */
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| 204 | volatile uint8_t SPBFCR; /* SPBFCR */
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| 205 | volatile uint8_t dummy3[1]; /* */
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| 206 | volatile uint16_t SPBFDR; /* SPBFDR */
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| 207 | } r_io_rspi_t;
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| 208 |
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| 209 |
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| 210 | /* Channel array defines of RSPI (2)*/
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| 211 | #ifdef DECLARE_RSPI_CHANNELS
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| 212 | volatile struct st_rspi* RSPI[ RSPI_COUNT ] =
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| 213 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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| 214 | RSPI_ADDRESS_LIST;
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| 215 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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| 216 | #endif /* DECLARE_RSPI_CHANNELS */
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| 217 | /* End of channel array defines of RSPI (2)*/
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| 218 |
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| 219 |
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| 220 | /* <-SEC M1.10.1 */
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| 221 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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| 222 | /* <-QAC 0857 */
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| 223 | /* <-QAC 0639 */
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| 224 | #endif
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