[429] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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| 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : mmc_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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| 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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| 28 | ******************************************************************************/
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| 29 | #ifndef MMC_IODEFINE_H
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| 30 | #define MMC_IODEFINE_H
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| 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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| 34 | /* ->SEC M1.10.1 : Not magic number */
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| 35 |
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| 36 | #define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
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| 37 |
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| 38 |
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| 39 | #define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
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| 40 | #define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
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| 41 | #define MMCCE_ARG (MMC.CE_ARG)
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| 42 | #define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
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| 43 | #define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
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| 44 | #define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
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| 45 | #define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
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| 46 | #define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
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| 47 | #define MMCCE_RESP3 (MMC.CE_RESP3)
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| 48 | #define MMCCE_RESP2 (MMC.CE_RESP2)
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| 49 | #define MMCCE_RESP1 (MMC.CE_RESP1)
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| 50 | #define MMCCE_RESP0 (MMC.CE_RESP0)
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| 51 | #define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
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| 52 | #define MMCCE_DATA (MMC.CE_DATA)
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| 53 | #define MMCCE_INT (MMC.CE_INT)
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| 54 | #define MMCCE_INT_EN (MMC.CE_INT_EN)
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| 55 | #define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
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| 56 | #define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
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| 57 | #define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
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| 58 | #define MMCCE_DETECT (MMC.CE_DETECT)
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| 59 | #define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
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| 60 | #define MMCCE_VERSION (MMC.CE_VERSION)
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| 61 |
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| 62 | #define MMC_CE_RESPn_COUNT (4)
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| 63 |
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| 64 |
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| 65 | typedef struct st_mmc
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| 66 | {
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| 67 | /* MMC */
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| 68 | volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
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| 69 | volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
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| 70 | volatile uint8_t dummy182[4]; /* */
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| 71 | volatile uint32_t CE_ARG; /* CE_ARG */
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| 72 | volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
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| 73 | volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
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| 74 | volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
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| 75 | volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
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| 76 | volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
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| 77 |
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| 78 | /* #define MMC_CE_RESPn_COUNT (4) */
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| 79 | volatile uint32_t CE_RESP3; /* CE_RESP3 */
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| 80 | volatile uint32_t CE_RESP2; /* CE_RESP2 */
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| 81 | volatile uint32_t CE_RESP1; /* CE_RESP1 */
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| 82 | volatile uint32_t CE_RESP0; /* CE_RESP0 */
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| 83 | volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
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| 84 | volatile uint32_t CE_DATA; /* CE_DATA */
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| 85 | volatile uint8_t dummy183[8]; /* */
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| 86 | volatile uint32_t CE_INT; /* CE_INT */
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| 87 | volatile uint32_t CE_INT_EN; /* CE_INT_EN */
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| 88 | volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
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| 89 | volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
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| 90 | volatile uint8_t dummy184[12]; /* */
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| 91 | volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
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| 92 | volatile uint8_t dummy185[16]; /* */
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| 93 | volatile uint32_t CE_DETECT; /* CE_DETECT */
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| 94 | volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
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| 95 | volatile uint8_t dummy186[4]; /* */
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| 96 | volatile uint32_t CE_VERSION; /* CE_VERSION */
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| 97 | } r_io_mmc_t;
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| 98 |
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| 99 |
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| 100 | /* <-SEC M1.10.1 */
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| 101 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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| 102 | /* <-QAC 0857 */
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| 103 | /* <-QAC 0639 */
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| 104 | #endif
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