1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : l2c_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef L2C_IODEFINE_H
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30 | #define L2C_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
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37 |
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38 |
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39 | /* Start of channel array defines of L2C */
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40 |
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41 | /* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
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42 | /*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
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43 | #define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8)
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44 | #define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
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45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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46 | &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
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47 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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48 | #define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
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49 | #define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
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50 | #define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
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51 | #define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
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52 | #define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
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53 | #define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
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54 | #define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
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55 | #define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
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56 |
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57 | /* End of channel array defines of L2C */
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58 |
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59 |
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60 | #define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
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61 | #define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
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62 | #define L2CREG1_CONTROL (L2C.REG1_CONTROL)
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63 | #define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
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64 | #define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
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65 | #define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
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66 | #define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
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67 | #define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
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68 | #define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
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69 | #define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
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70 | #define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
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71 | #define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
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72 | #define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
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73 | #define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
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74 | #define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
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75 | #define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
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76 | #define L2CREG7_INV_PA (L2C.REG7_INV_PA)
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77 | #define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
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78 | #define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
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79 | #define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
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80 | #define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
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81 | #define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
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82 | #define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
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83 | #define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
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84 | #define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
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85 | #define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
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86 | #define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
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87 | #define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
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88 | #define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
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89 | #define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
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90 | #define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
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91 | #define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
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92 | #define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
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93 | #define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
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94 | #define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
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95 | #define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
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96 | #define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
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97 | #define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
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98 | #define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
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99 | #define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
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100 | #define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
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101 | #define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
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102 | #define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
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103 | #define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
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104 | #define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
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105 | #define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
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106 | #define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
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107 |
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108 |
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109 | typedef struct st_l2c
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110 | {
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111 | /* L2C */
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112 | volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
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113 | volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
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114 | volatile uint8_t dummy8[248]; /* */
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115 | volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
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116 | volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
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117 | volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
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118 | volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
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119 | volatile uint8_t dummy9[240]; /* */
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120 | volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
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121 | volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
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122 | volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
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123 | volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
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124 | volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
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125 | volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
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126 | volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
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127 | volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
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128 | volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
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129 | volatile uint8_t dummy10[1292]; /* */
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130 | volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
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131 | volatile uint8_t dummy11[60]; /* */
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132 | volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
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133 | volatile uint8_t dummy12[8]; /* */
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134 | volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
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135 | volatile uint8_t dummy13[48]; /* */
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136 | volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
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137 | volatile uint8_t dummy14[4]; /* */
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138 | volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
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139 | volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
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140 | volatile uint8_t dummy15[48]; /* */
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141 | volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
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142 | volatile uint8_t dummy16[4]; /* */
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143 | volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
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144 | volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
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145 | volatile uint8_t dummy17[256]; /* */
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146 |
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147 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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148 | volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
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149 | volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
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150 |
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151 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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152 |
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153 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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154 | volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
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155 | volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
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156 |
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157 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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158 |
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159 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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160 | volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
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161 | volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
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162 |
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163 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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164 |
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165 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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166 | volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
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167 | volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
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168 |
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169 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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170 |
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171 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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172 | volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
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173 | volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
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174 |
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175 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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176 |
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177 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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178 | volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
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179 | volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
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180 |
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181 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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182 |
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183 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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184 | volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
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185 | volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
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186 |
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187 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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188 |
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189 | /* start of struct st_l2c_from_reg9_d_lockdown0 */
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190 | volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
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191 | volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
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192 |
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193 | /* end of struct st_l2c_from_reg9_d_lockdown0 */
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194 | volatile uint8_t dummy18[16]; /* */
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195 | volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
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196 | volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
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197 | volatile uint8_t dummy19[680]; /* */
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198 | volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
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199 | volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
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200 | volatile uint8_t dummy20[824]; /* */
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201 | volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
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202 | volatile uint8_t dummy21[28]; /* */
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203 | volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
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204 | volatile uint8_t dummy22[28]; /* */
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205 | volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
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206 | } r_io_l2c_t;
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207 |
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208 |
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209 | typedef struct st_l2c_from_reg9_d_lockdown0
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210 | {
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211 |
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212 | volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
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213 | volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
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214 | } r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
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215 |
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216 |
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217 | /* Channel array defines of L2C (2)*/
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218 | #ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
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219 | volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
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220 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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221 | L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
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222 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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223 | #endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
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224 | /* End of channel array defines of L2C (2)*/
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225 |
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226 |
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227 | /* <-SEC M1.10.1 */
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228 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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229 | /* <-QAC 0857 */
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230 | /* <-QAC 0639 */
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231 | #endif
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