1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : iodefine_typedef.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef IODEFINE_TYPEDEF_H
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30 | #define IODEFINE_TYPEDEF_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | /* Shared types and macros for iodefine.h */
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37 |
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38 | /***********************************************************************
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39 | * Macro: IODEFINE_H_VERSION
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40 | ************************************************************************/
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41 | #define IODEFINE_H_VERSION (200)
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42 |
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43 |
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44 | /***********************************************************************
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45 | * Enum: iodefine_byte_select_t
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46 | *
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47 | * R_IO_L - Low 16bit or Low 8 bit
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48 | * R_IO_H - High 16bit or Low 8 bit
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49 | * R_IO_LL - Low 8 bit
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50 | * R_IO_LH - Middle Low 8 bit
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51 | * R_IO_HL - Middle High 8 bit
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52 | * R_IO_HH - High 8 bit
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53 | ************************************************************************/
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54 | typedef enum iodefine_byte_select_t
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55 | {
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56 | R_IO_L = 0, R_IO_H = 1,
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57 | R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
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58 | L = 0, H = 1,
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59 | LL= 0, LH = 1, HL = 2, HH = 3
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60 | } iodefine_byte_select_t;
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61 |
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62 |
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63 | /***********************************************************************
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64 | * Type: iodefine_reg32_t
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65 | * 32/16/8 bit access register
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66 | *
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67 | * - Padding : sizeof(iodefine_reg32_t) == 4
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68 | * - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
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69 | * &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
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70 | * - Endian : Independent (Same as CPU endian as register endian)
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71 | * - Bit-Order : Independent
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72 | ************************************************************************/
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73 | typedef union iodefine_reg32_t
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74 | {
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75 | volatile uint32_t UINT32; /* 32-bit Access */
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76 | volatile uint16_t UINT16[2]; /* 16-bit Access */
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77 | volatile uint8_t UINT8[4]; /* 8-bit Access */
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78 | } iodefine_reg32_t;
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79 |
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80 |
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81 | /***********************************************************************
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82 | * Type: iodefine_reg32_16_t
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83 | * 32/16 bit access register
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84 | *
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85 | * - Padding : sizeof(iodefine_reg32_16_t) == 4
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86 | * - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
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87 | * - Endian : Independent (Same as CPU endian as register endian)
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88 | * - Bit-Order : Independent
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89 | ************************************************************************/
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90 | typedef union iodefine_reg32_16_t
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91 | {
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92 | volatile uint32_t UINT32; /* 32-bit Access */
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93 | volatile uint16_t UINT16[2]; /* 16-bit Access */
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94 | } iodefine_reg32_16_t;
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95 |
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96 |
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97 | /***********************************************************************
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98 | * Type: iodefine_reg16_8_t
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99 | * 16/8 bit access register
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100 | *
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101 | * - Padding : sizeof(iodefine_reg16_8_t) == 2
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102 | * - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
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103 | * - Endian : Independent (Same as CPU endian as register endian)
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104 | * - Bit-Order : Independent
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105 | ************************************************************************/
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106 | typedef union iodefine_reg16_8_t
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107 | {
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108 | volatile uint16_t UINT16; /* 16-bit Access */
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109 | volatile uint8_t UINT8[2]; /* 8-bit Access */
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110 | } iodefine_reg16_8_t;
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111 |
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112 |
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113 | /* End of shared types and macros for iodefine.h */
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114 | /* <-SEC M1.10.1 */
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115 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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116 | /* <-QAC 0857 */
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117 | /* <-QAC 0639 */
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118 | #endif
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