source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h@ 439

Last change on this file since 439 was 439, checked in by coas-nagasima, 4 years ago

mrubyを2.1.1に更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 5.5 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : inb_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef INB_IODEFINE_H
30#define INB_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
37
38
39#define INBRMPR (INB.RMPR)
40#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
41#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
42#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
43#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
44#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
45#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
46#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
47#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
48#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
49#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
50#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
51#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
52#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
53#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
54#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
55#define INBAXIRERRST0 (INB.AXIRERRST0)
56#define INBAXIRERRST1 (INB.AXIRERRST1)
57#define INBAXIRERRST2 (INB.AXIRERRST2)
58#define INBAXIRERRST3 (INB.AXIRERRST3)
59#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
60#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
61#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
62#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
63
64#define INB_AXIBUSCTLn_COUNT (11)
65#define INB_AXIRERRCTLn_COUNT (4)
66#define INB_AXIRERRSTn_COUNT (4)
67#define INB_AXIRERRCLRn_COUNT (4)
68
69
70typedef struct st_inb
71{
72 /* INB */
73 volatile uint32_t RMPR; /* RMPR */
74
75/* #define INB_AXIBUSCTLn_COUNT (11) */
76 volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
77 volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
78 volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
79 volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
80 volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
81 volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
82 volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
83 volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
84 volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
85 volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
86 volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
87
88/* #define INB_AXIRERRCTLn_COUNT (4) */
89 volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
90 volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
91 volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
92 volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
93
94/* #define INB_AXIRERRSTn_COUNT (4) */
95 volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
96 volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
97 volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
98 volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
99
100/* #define INB_AXIRERRCLRn_COUNT (4) */
101 volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
102 volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
103 volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
104 volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
105} r_io_inb_t;
106
107
108/* <-SEC M1.10.1 */
109/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
110/* <-QAC 0857 */
111/* <-QAC 0639 */
112#endif
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