1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : ceu_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef CEU_IODEFINE_H
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30 | #define CEU_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
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37 |
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38 |
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39 | /* Start of channel array defines of CEU */
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40 |
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41 | /* Channel array defines of CEUn */
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42 | /*(Sample) value = CEUn[ channel ]->CAMOR; */
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43 | #define CEUn_COUNT (3)
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44 | #define CEUn_ADDRESS_LIST \
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45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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46 | (volatile struct st_ceu_n*)&CEU_A, \
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47 | (volatile struct st_ceu_n*)&CEU_B, \
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48 | (volatile struct st_ceu_n*)&CEU_M \
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49 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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50 | #define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
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51 | #define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
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52 | #define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
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53 |
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54 | /* End of channel array defines of CEU */
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55 |
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56 |
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57 | #define CEUCAPSR (CEU.CAPSR)
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58 | #define CEUCAPCR (CEU.CAPCR)
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59 | #define CEUCAMCR (CEU.CAMCR)
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60 | #define CEUCMCYR (CEU.CMCYR)
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61 | #define CEUCAMOR_A (CEU.CAMOR_A)
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62 | #define CEUCAPWR_A (CEU.CAPWR_A)
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63 | #define CEUCAIFR (CEU.CAIFR)
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64 | #define CEUCRCNTR (CEU.CRCNTR)
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65 | #define CEUCRCMPR (CEU.CRCMPR)
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66 | #define CEUCFLCR_A (CEU.CFLCR_A)
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67 | #define CEUCFSZR_A (CEU.CFSZR_A)
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68 | #define CEUCDWDR_A (CEU.CDWDR_A)
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69 | #define CEUCDAYR_A (CEU.CDAYR_A)
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70 | #define CEUCDACR_A (CEU.CDACR_A)
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71 | #define CEUCDBYR_A (CEU.CDBYR_A)
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72 | #define CEUCDBCR_A (CEU.CDBCR_A)
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73 | #define CEUCBDSR_A (CEU.CBDSR_A)
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74 | #define CEUCFWCR (CEU.CFWCR)
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75 | #define CEUCLFCR_A (CEU.CLFCR_A)
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76 | #define CEUCDOCR_A (CEU.CDOCR_A)
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77 | #define CEUCEIER (CEU.CEIER)
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78 | #define CEUCETCR (CEU.CETCR)
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79 | #define CEUCSTSR (CEU.CSTSR)
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80 | #define CEUCDSSR (CEU.CDSSR)
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81 | #define CEUCDAYR2_A (CEU.CDAYR2_A)
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82 | #define CEUCDACR2_A (CEU.CDACR2_A)
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83 | #define CEUCDBYR2_A (CEU.CDBYR2_A)
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84 | #define CEUCDBCR2_A (CEU.CDBCR2_A)
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85 | #define CEUCAMOR_B (CEU.CAMOR_B)
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86 | #define CEUCAPWR_B (CEU.CAPWR_B)
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87 | #define CEUCFLCR_B (CEU.CFLCR_B)
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88 | #define CEUCFSZR_B (CEU.CFSZR_B)
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89 | #define CEUCDWDR_B (CEU.CDWDR_B)
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90 | #define CEUCDAYR_B (CEU.CDAYR_B)
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91 | #define CEUCDACR_B (CEU.CDACR_B)
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92 | #define CEUCDBYR_B (CEU.CDBYR_B)
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93 | #define CEUCDBCR_B (CEU.CDBCR_B)
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94 | #define CEUCBDSR_B (CEU.CBDSR_B)
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95 | #define CEUCLFCR_B (CEU.CLFCR_B)
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96 | #define CEUCDOCR_B (CEU.CDOCR_B)
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97 | #define CEUCDAYR2_B (CEU.CDAYR2_B)
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98 | #define CEUCDACR2_B (CEU.CDACR2_B)
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99 | #define CEUCDBYR2_B (CEU.CDBYR2_B)
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100 | #define CEUCDBCR2_B (CEU.CDBCR2_B)
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101 | #define CEUCAMOR_M (CEU.CAMOR_M)
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102 | #define CEUCAPWR_M (CEU.CAPWR_M)
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103 | #define CEUCFLCR_M (CEU.CFLCR_M)
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104 | #define CEUCFSZR_M (CEU.CFSZR_M)
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105 | #define CEUCDWDR_M (CEU.CDWDR_M)
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106 | #define CEUCDAYR_M (CEU.CDAYR_M)
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107 | #define CEUCDACR_M (CEU.CDACR_M)
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108 | #define CEUCDBYR_M (CEU.CDBYR_M)
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109 | #define CEUCDBCR_M (CEU.CDBCR_M)
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110 | #define CEUCBDSR_M (CEU.CBDSR_M)
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111 | #define CEUCLFCR_M (CEU.CLFCR_M)
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112 | #define CEUCDOCR_M (CEU.CDOCR_M)
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113 | #define CEUCDAYR2_M (CEU.CDAYR2_M)
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114 | #define CEUCDACR2_M (CEU.CDACR2_M)
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115 | #define CEUCDBYR2_M (CEU.CDBYR2_M)
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116 | #define CEUCDBCR2_M (CEU.CDBCR2_M)
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117 |
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118 |
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119 | typedef struct st_ceu
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120 | {
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121 | /* CEU */
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122 |
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123 | /* start of struct st_ceu_n */
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124 | volatile uint32_t CAPSR; /* CAPSR */
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125 | volatile uint32_t CAPCR; /* CAPCR */
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126 | volatile uint32_t CAMCR; /* CAMCR */
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127 | volatile uint32_t CMCYR; /* CMCYR */
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128 | volatile uint32_t CAMOR_A; /* CAMOR_A */
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129 | volatile uint32_t CAPWR_A; /* CAPWR_A */
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130 | volatile uint32_t CAIFR; /* CAIFR */
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131 | volatile uint8_t dummy305[12]; /* */
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132 | volatile uint32_t CRCNTR; /* CRCNTR */
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133 | volatile uint32_t CRCMPR; /* CRCMPR */
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134 | volatile uint32_t CFLCR_A; /* CFLCR_A */
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135 | volatile uint32_t CFSZR_A; /* CFSZR_A */
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136 | volatile uint32_t CDWDR_A; /* CDWDR_A */
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137 | volatile uint32_t CDAYR_A; /* CDAYR_A */
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138 | volatile uint32_t CDACR_A; /* CDACR_A */
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139 | volatile uint32_t CDBYR_A; /* CDBYR_A */
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140 | volatile uint32_t CDBCR_A; /* CDBCR_A */
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141 | volatile uint32_t CBDSR_A; /* CBDSR_A */
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142 | volatile uint8_t dummy306[12]; /* */
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143 | volatile uint32_t CFWCR; /* CFWCR */
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144 | volatile uint32_t CLFCR_A; /* CLFCR_A */
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145 | volatile uint32_t CDOCR_A; /* CDOCR_A */
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146 | volatile uint8_t dummy307[8]; /* */
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147 | volatile uint32_t CEIER; /* CEIER */
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148 | volatile uint32_t CETCR; /* CETCR */
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149 | volatile uint8_t dummy308[4]; /* */
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150 | volatile uint32_t CSTSR; /* CSTSR */
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151 | volatile uint8_t dummy309[4]; /* */
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152 | volatile uint32_t CDSSR; /* CDSSR */
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153 | volatile uint8_t dummy310[8]; /* */
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154 | volatile uint32_t CDAYR2_A; /* CDAYR2_A */
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155 | volatile uint32_t CDACR2_A; /* CDACR2_A */
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156 | volatile uint32_t CDBYR2_A; /* CDBYR2_A */
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157 | volatile uint32_t CDBCR2_A; /* CDBCR2_A */
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158 |
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159 | /* end of struct st_ceu_n */
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160 | volatile uint8_t dummy3110[3936]; /* */
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161 |
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162 | /* start of struct st_ceu_n */
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163 | volatile uint8_t dummy3111[4]; /* */
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164 | volatile uint8_t dummy3112[4]; /* */
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165 | volatile uint8_t dummy3113[4]; /* */
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166 | volatile uint8_t dummy3114[4]; /* */
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167 | volatile uint32_t CAMOR_B; /* CAMOR_B */
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168 | volatile uint32_t CAPWR_B; /* CAPWR_B */
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169 | volatile uint8_t dummy3120[4]; /* */
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170 | volatile uint8_t dummy3121[12]; /* */
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171 | volatile uint8_t dummy3122[4]; /* */
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172 | volatile uint8_t dummy3123[4]; /* */
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173 | volatile uint32_t CFLCR_B; /* CFLCR_B */
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174 | volatile uint32_t CFSZR_B; /* CFSZR_B */
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175 | volatile uint32_t CDWDR_B; /* CDWDR_B */
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176 | volatile uint32_t CDAYR_B; /* CDAYR_B */
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177 | volatile uint32_t CDACR_B; /* CDACR_B */
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178 | volatile uint32_t CDBYR_B; /* CDBYR_B */
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179 | volatile uint32_t CDBCR_B; /* CDBCR_B */
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180 | volatile uint32_t CBDSR_B; /* CBDSR_B */
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181 | volatile uint8_t dummy3130[12]; /* */
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182 | volatile uint8_t dummy3131[4]; /* */
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183 | volatile uint32_t CLFCR_B; /* CLFCR_B */
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184 | volatile uint32_t CDOCR_B; /* CDOCR_B */
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185 | volatile uint8_t dummy3140[8]; /* */
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186 | volatile uint8_t dummy3141[4]; /* */
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187 | volatile uint8_t dummy3142[4]; /* */
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188 | volatile uint8_t dummy3143[4]; /* */
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189 | volatile uint8_t dummy3144[4]; /* */
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190 | volatile uint8_t dummy3145[4]; /* */
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191 | volatile uint8_t dummy3146[4]; /* */
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192 | volatile uint8_t dummy3147[8]; /* */
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193 | volatile uint32_t CDAYR2_B; /* CDAYR2_B */
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194 | volatile uint32_t CDACR2_B; /* CDACR2_B */
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195 | volatile uint32_t CDBYR2_B; /* CDBYR2_B */
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196 | volatile uint32_t CDBCR2_B; /* CDBCR2_B */
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197 |
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198 | /* end of struct st_ceu_n */
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199 | volatile uint8_t dummy3150[3936]; /* */
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200 |
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201 | /* start of struct st_ceu_n */
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202 | volatile uint8_t dummy3151[4]; /* */
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203 | volatile uint8_t dummy3152[4]; /* */
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204 | volatile uint8_t dummy3153[4]; /* */
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205 | volatile uint8_t dummy3154[4]; /* */
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206 | volatile uint32_t CAMOR_M; /* CAMOR_M */
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207 | volatile uint32_t CAPWR_M; /* CAPWR_M */
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208 | volatile uint8_t dummy3160[4]; /* */
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209 | volatile uint8_t dummy3161[12]; /* */
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210 | volatile uint8_t dummy3162[4]; /* */
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211 | volatile uint8_t dummy3163[4]; /* */
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212 | volatile uint32_t CFLCR_M; /* CFLCR_M */
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213 | volatile uint32_t CFSZR_M; /* CFSZR_M */
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214 | volatile uint32_t CDWDR_M; /* CDWDR_M */
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215 | volatile uint32_t CDAYR_M; /* CDAYR_M */
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216 | volatile uint32_t CDACR_M; /* CDACR_M */
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217 | volatile uint32_t CDBYR_M; /* CDBYR_M */
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218 | volatile uint32_t CDBCR_M; /* CDBCR_M */
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219 | volatile uint32_t CBDSR_M; /* CBDSR_M */
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220 | volatile uint8_t dummy3170[12]; /* */
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221 | volatile uint8_t dummy3171[4]; /* */
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222 | volatile uint32_t CLFCR_M; /* CLFCR_M */
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223 | volatile uint32_t CDOCR_M; /* CDOCR_M */
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224 | volatile uint8_t dummy3180[8]; /* */
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225 | volatile uint8_t dummy3181[4]; /* */
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226 | volatile uint8_t dummy3182[4]; /* */
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227 | volatile uint8_t dummy3183[4]; /* */
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228 | volatile uint8_t dummy3184[4]; /* */
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229 | volatile uint8_t dummy3185[4]; /* */
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230 | volatile uint8_t dummy3186[4]; /* */
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231 | volatile uint8_t dummy3187[8]; /* */
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232 | volatile uint32_t CDAYR2_M; /* CDAYR2_M */
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233 | volatile uint32_t CDACR2_M; /* CDACR2_M */
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234 | volatile uint32_t CDBYR2_M; /* CDBYR2_M */
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235 | volatile uint32_t CDBCR2_M; /* CDBCR2_M */
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236 |
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237 | /* end of struct st_ceu_n */
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238 | } r_io_ceu_t;
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239 |
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240 |
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241 | typedef struct st_ceu_n
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242 | {
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243 |
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244 | volatile uint32_t not_common1; /* */
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245 | volatile uint32_t not_common2; /* */
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246 | volatile uint32_t not_common3; /* */
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247 | volatile uint32_t not_common4; /* */
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248 | volatile uint32_t CAMOR; /* CAMOR */
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249 | volatile uint32_t CAPWR; /* CAPWR */
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250 | volatile uint32_t not_common5; /* */
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251 | volatile uint8_t dummy322[12]; /* */
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252 | volatile uint32_t not_common6; /* */
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253 | volatile uint32_t not_common7; /* */
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254 | volatile uint32_t CFLCR; /* CFLCR */
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255 | volatile uint32_t CFSZR; /* CFSZR */
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256 | volatile uint32_t CDWDR; /* CDWDR */
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257 | volatile uint32_t CDAYR; /* CDAYR */
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258 | volatile uint32_t CDACR; /* CDACR */
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259 | volatile uint32_t CDBYR; /* CDBYR */
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260 | volatile uint32_t CDBCR; /* CDBCR */
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261 | volatile uint32_t CBDSR; /* CBDSR */
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262 | volatile uint8_t dummy323[12]; /* */
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263 | volatile uint32_t not_common8; /* */
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264 | volatile uint32_t CLFCR; /* CLFCR */
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265 | volatile uint32_t CDOCR; /* CDOCR */
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266 | volatile uint8_t dummy324[8]; /* */
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267 | volatile uint32_t not_common9; /* */
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268 | volatile uint32_t not_common10; /* */
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269 | volatile uint8_t dummy325[4]; /* */
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270 | volatile uint32_t not_common11; /* */
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271 | volatile uint8_t dummy326[4]; /* */
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272 | volatile uint32_t not_common12; /* */
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273 | volatile uint8_t dummy327[8]; /* */
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274 | volatile uint32_t CDAYR2; /* CDAYR2 */
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275 | volatile uint32_t CDACR2; /* CDACR2 */
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276 | volatile uint32_t CDBYR2; /* CDBYR2 */
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277 | volatile uint32_t CDBCR2; /* CDBCR2 */
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278 | } r_io_ceu_n_t;
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279 |
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280 |
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281 | /* Channel array defines of CEUn (2)*/
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282 | #ifdef DECLARE_CEUn_CHANNELS
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283 | volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] =
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284 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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285 | CEUn_ADDRESS_LIST;
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286 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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287 | #endif /* DECLARE_CEUn_CHANNELS */
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288 | /* End of channel array defines of CEUn (2)*/
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289 |
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290 |
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291 | /* <-SEC M1.10.1 */
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292 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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293 | /* <-QAC 0857 */
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294 | /* <-QAC 0639 */
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295 | #endif
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