1 | /*******************************************************************************
|
---|
2 | * DISCLAIMER
|
---|
3 | * This software is supplied by Renesas Electronics Corporation and is only
|
---|
4 | * intended for use with Renesas products. No other uses are authorized. This
|
---|
5 | * software is owned by Renesas Electronics Corporation and is protected under
|
---|
6 | * all applicable laws, including copyright laws.
|
---|
7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
---|
8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
---|
9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
---|
10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
---|
11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
---|
12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
---|
13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
---|
14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
---|
15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
---|
16 | * Renesas reserves the right, without notice, to make changes to this software
|
---|
17 | * and to discontinue the availability of this software. By using this software,
|
---|
18 | * you agree to the additional terms and conditions found by accessing the
|
---|
19 | * following link:
|
---|
20 | * http://www.renesas.com/disclaimer*
|
---|
21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
|
---|
22 | *******************************************************************************/
|
---|
23 | /*******************************************************************************
|
---|
24 | * File Name : bsc_iodefine.h
|
---|
25 | * $Rev: $
|
---|
26 | * $Date:: $
|
---|
27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
|
---|
28 | ******************************************************************************/
|
---|
29 | #ifndef BSC_IODEFINE_H
|
---|
30 | #define BSC_IODEFINE_H
|
---|
31 | /* ->QAC 0639 : Over 127 members (C90) */
|
---|
32 | /* ->QAC 0857 : Over 1024 #define (C90) */
|
---|
33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
|
---|
34 | /* ->SEC M1.10.1 : Not magic number */
|
---|
35 |
|
---|
36 | #define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
|
---|
37 |
|
---|
38 |
|
---|
39 | #define BSCCMNCR (BSC.CMNCR)
|
---|
40 | #define BSCCS0BCR (BSC.CS0BCR)
|
---|
41 | #define BSCCS1BCR (BSC.CS1BCR)
|
---|
42 | #define BSCCS2BCR (BSC.CS2BCR)
|
---|
43 | #define BSCCS3BCR (BSC.CS3BCR)
|
---|
44 | #define BSCCS4BCR (BSC.CS4BCR)
|
---|
45 | #define BSCCS5BCR (BSC.CS5BCR)
|
---|
46 | #define BSCCS0WCR (BSC.CS0WCR)
|
---|
47 | #define BSCCS1WCR (BSC.CS1WCR)
|
---|
48 | #define BSCCS2WCR (BSC.CS2WCR)
|
---|
49 | #define BSCCS3WCR (BSC.CS3WCR)
|
---|
50 | #define BSCCS4WCR (BSC.CS4WCR)
|
---|
51 | #define BSCCS5WCR (BSC.CS5WCR)
|
---|
52 | #define BSCSDCR (BSC.SDCR)
|
---|
53 | #define BSCRTCSR (BSC.RTCSR)
|
---|
54 | #define BSCRTCNT (BSC.RTCNT)
|
---|
55 | #define BSCRTCOR (BSC.RTCOR)
|
---|
56 | #define BSCTOSCOR0 (BSC.TOSCOR0)
|
---|
57 | #define BSCTOSCOR1 (BSC.TOSCOR1)
|
---|
58 | #define BSCTOSCOR2 (BSC.TOSCOR2)
|
---|
59 | #define BSCTOSCOR3 (BSC.TOSCOR3)
|
---|
60 | #define BSCTOSCOR4 (BSC.TOSCOR4)
|
---|
61 | #define BSCTOSCOR5 (BSC.TOSCOR5)
|
---|
62 | #define BSCTOSTR (BSC.TOSTR)
|
---|
63 | #define BSCTOENR (BSC.TOENR)
|
---|
64 |
|
---|
65 | #define BSC_CSnBCR_COUNT (6)
|
---|
66 | #define BSC_CSnWCR_COUNT (6)
|
---|
67 | #define BSC_TOSCORn_COUNT (6)
|
---|
68 |
|
---|
69 |
|
---|
70 | typedef struct st_bsc
|
---|
71 | {
|
---|
72 | /* BSC */
|
---|
73 | volatile uint32_t CMNCR; /* CMNCR */
|
---|
74 |
|
---|
75 | /* #define BSC_CSnBCR_COUNT (6) */
|
---|
76 | volatile uint32_t CS0BCR; /* CS0BCR */
|
---|
77 | volatile uint32_t CS1BCR; /* CS1BCR */
|
---|
78 | volatile uint32_t CS2BCR; /* CS2BCR */
|
---|
79 | volatile uint32_t CS3BCR; /* CS3BCR */
|
---|
80 | volatile uint32_t CS4BCR; /* CS4BCR */
|
---|
81 | volatile uint32_t CS5BCR; /* CS5BCR */
|
---|
82 | volatile uint8_t dummy4[12]; /* */
|
---|
83 |
|
---|
84 | /* #define BSC_CSnWCR_COUNT (6) */
|
---|
85 | volatile uint32_t CS0WCR; /* CS0WCR */
|
---|
86 | volatile uint32_t CS1WCR; /* CS1WCR */
|
---|
87 | volatile uint32_t CS2WCR; /* CS2WCR */
|
---|
88 | volatile uint32_t CS3WCR; /* CS3WCR */
|
---|
89 | volatile uint32_t CS4WCR; /* CS4WCR */
|
---|
90 | volatile uint32_t CS5WCR; /* CS5WCR */
|
---|
91 | volatile uint8_t dummy5[12]; /* */
|
---|
92 | volatile uint32_t SDCR; /* SDCR */
|
---|
93 | volatile uint32_t RTCSR; /* RTCSR */
|
---|
94 | volatile uint32_t RTCNT; /* RTCNT */
|
---|
95 | volatile uint32_t RTCOR; /* RTCOR */
|
---|
96 | volatile uint8_t dummy6[4]; /* */
|
---|
97 |
|
---|
98 | /* #define BSC_TOSCORn_COUNT (6) */
|
---|
99 | volatile uint32_t TOSCOR0; /* TOSCOR0 */
|
---|
100 | volatile uint32_t TOSCOR1; /* TOSCOR1 */
|
---|
101 | volatile uint32_t TOSCOR2; /* TOSCOR2 */
|
---|
102 | volatile uint32_t TOSCOR3; /* TOSCOR3 */
|
---|
103 | volatile uint32_t TOSCOR4; /* TOSCOR4 */
|
---|
104 | volatile uint32_t TOSCOR5; /* TOSCOR5 */
|
---|
105 | volatile uint8_t dummy7[8]; /* */
|
---|
106 | volatile uint32_t TOSTR; /* TOSTR */
|
---|
107 | volatile uint32_t TOENR; /* TOENR */
|
---|
108 | } r_io_bsc_t;
|
---|
109 |
|
---|
110 |
|
---|
111 | /* <-SEC M1.10.1 */
|
---|
112 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
|
---|
113 | /* <-QAC 0857 */
|
---|
114 | /* <-QAC 0639 */
|
---|
115 | #endif
|
---|