1 | /******************************************************************************
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2 | * @file RZ_A1H.h
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3 | * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
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4 | * @version V1.00
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5 | * @data 10 Mar 2017
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /*
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11 | * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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12 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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13 | *
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14 | * SPDX-License-Identifier: Apache-2.0
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15 | *
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16 | * Licensed under the Apache License, Version 2.0 (the License); you may
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17 | * not use this file except in compliance with the License.
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18 | * You may obtain a copy of the License at
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19 | *
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20 | * www.apache.org/licenses/LICENSE-2.0
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21 | *
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22 | * Unless required by applicable law or agreed to in writing, software
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23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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25 | * See the License for the specific language governing permissions and
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26 | * limitations under the License.
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27 | */
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28 |
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29 | #ifndef __RZ_A1H_H__
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30 | #define __RZ_A1H_H__
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31 |
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32 | #ifdef __cplusplus
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33 | extern "C" {
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34 | #endif
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35 |
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36 | /* ------------------------- Interrupt Number Definition ------------------------ */
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37 |
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38 | typedef enum IRQn
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39 | {
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40 | /****** SGI Interrupts Numbers ****************************************/
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41 | SGI0_IRQn = 0,
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42 | SGI1_IRQn = 1,
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43 | SGI2_IRQn = 2,
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44 | SGI3_IRQn = 3,
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45 | SGI4_IRQn = 4,
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46 | SGI5_IRQn = 5,
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47 | SGI6_IRQn = 6,
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48 | SGI7_IRQn = 7,
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49 | SGI8_IRQn = 8,
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50 | SGI9_IRQn = 9,
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51 | SGI10_IRQn = 10,
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52 | SGI11_IRQn = 11,
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53 | SGI12_IRQn = 12,
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54 | SGI13_IRQn = 13,
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55 | SGI14_IRQn = 14,
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56 | SGI15_IRQn = 15,
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57 |
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58 | /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
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59 | /* 16 - 578 */
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60 | PMUIRQ0_IRQn = 16,
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61 | COMMRX0_IRQn = 17,
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62 | COMMTX0_IRQn = 18,
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63 | CTIIRQ0_IRQn = 19,
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64 |
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65 | IRQ0_IRQn = 32,
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66 | IRQ1_IRQn = 33,
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67 | IRQ2_IRQn = 34,
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68 | IRQ3_IRQn = 35,
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69 | IRQ4_IRQn = 36,
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70 | IRQ5_IRQn = 37,
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71 | IRQ6_IRQn = 38,
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72 | IRQ7_IRQn = 39,
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73 |
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74 | PL310ERR_IRQn = 40,
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75 |
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76 | DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
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77 | DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
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78 | DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
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79 | DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
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80 | DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
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81 | DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
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82 | DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
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83 | DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
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84 | DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
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85 | DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
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86 | DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
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87 | DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
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88 | DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
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89 | DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
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90 | DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
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91 | DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
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92 | DMAERR_IRQn = 57, /*!< DMAC Interrupt */
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93 |
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94 | /* 58-72 Reserved */
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95 |
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96 | USBI0_IRQn = 73,
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97 | USBI1_IRQn = 74,
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98 |
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99 | S0_VI_VSYNC0_IRQn = 75,
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100 | S0_LO_VSYNC0_IRQn = 76,
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101 | S0_VSYNCERR0_IRQn = 77,
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102 | GR3_VLINE0_IRQn = 78,
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103 | S0_VFIELD0_IRQn = 79,
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104 | IV1_VBUFERR0_IRQn = 80,
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105 | IV3_VBUFERR0_IRQn = 81,
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106 | IV5_VBUFERR0_IRQn = 82,
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107 | IV6_VBUFERR0_IRQn = 83,
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108 | S0_WLINE0_IRQn = 84,
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109 | S1_VI_VSYNC0_IRQn = 85,
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110 | S1_LO_VSYNC0_IRQn = 86,
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111 | S1_VSYNCERR0_IRQn = 87,
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112 | S1_VFIELD0_IRQn = 88,
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113 | IV2_VBUFERR0_IRQn = 89,
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114 | IV4_VBUFERR0_IRQn = 90,
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115 | S1_WLINE0_IRQn = 91,
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116 | OIR_VI_VSYNC0_IRQn = 92,
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117 | OIR_LO_VSYNC0_IRQn = 93,
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118 | OIR_VSYNCERR0_IRQn = 94,
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119 | OIR_VFIELD0_IRQn = 95,
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120 | IV7_VBUFERR0_IRQn = 96,
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121 | IV8_VBUFERR0_IRQn = 97,
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122 | /* 98 Reserved */
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123 | S0_VI_VSYNC1_IRQn = 99,
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124 | S0_LO_VSYNC1_IRQn = 100,
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125 | S0_VSYNCERR1_IRQn = 101,
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126 | GR3_VLINE1_IRQn = 102,
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127 | S0_VFIELD1_IRQn = 103,
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128 | IV1_VBUFERR1_IRQn = 104,
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129 | IV3_VBUFERR1_IRQn = 105,
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130 | IV5_VBUFERR1_IRQn = 106,
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131 | IV6_VBUFERR1_IRQn = 107,
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132 | S0_WLINE1_IRQn = 108,
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133 | S1_VI_VSYNC1_IRQn = 109,
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134 | S1_LO_VSYNC1_IRQn = 110,
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135 | S1_VSYNCERR1_IRQn = 111,
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136 | S1_VFIELD1_IRQn = 112,
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137 | IV2_VBUFERR1_IRQn = 113,
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138 | IV4_VBUFERR1_IRQn = 114,
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139 | S1_WLINE1_IRQn = 115,
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140 | OIR_VI_VSYNC1_IRQn = 116,
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141 | OIR_LO_VSYNC1_IRQn = 117,
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142 | OIR_VSYNCERR1_IRQn = 118,
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143 | OIR_VFIELD1_IRQn = 119,
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144 | IV7_VBUFERR1_IRQn = 120,
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145 | IV8_VBUFERR1_IRQn = 121,
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146 | /* Reserved = 122 */
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147 |
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148 | IMRDI_IRQn = 123,
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149 | IMR2I0_IRQn = 124,
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150 | IMR2I1_IRQn = 125,
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151 |
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152 | JEDI_IRQn = 126,
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153 | JDTI_IRQn = 127,
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154 |
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155 | CMP0_IRQn = 128,
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156 | CMP1_IRQn = 129,
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157 |
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158 | INT0_IRQn = 130,
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159 | INT1_IRQn = 131,
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160 | INT2_IRQn = 132,
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161 | INT3_IRQn = 133,
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162 |
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163 | OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
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164 | OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
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165 |
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166 | CMI_IRQn = 136,
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167 | WTOUT_IRQn = 137,
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168 |
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169 | ITI_IRQn = 138,
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170 |
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171 | TGI0A_IRQn = 139,
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172 | TGI0B_IRQn = 140,
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173 | TGI0C_IRQn = 141,
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174 | TGI0D_IRQn = 142,
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175 | TGI0V_IRQn = 143,
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176 | TGI0E_IRQn = 144,
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177 | TGI0F_IRQn = 145,
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178 | TGI1A_IRQn = 146,
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179 | TGI1B_IRQn = 147,
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180 | TGI1V_IRQn = 148,
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181 | TGI1U_IRQn = 149,
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182 | TGI2A_IRQn = 150,
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183 | TGI2B_IRQn = 151,
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184 | TGI2V_IRQn = 152,
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185 | TGI2U_IRQn = 153,
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186 | TGI3A_IRQn = 154,
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187 | TGI3B_IRQn = 155,
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188 | TGI3C_IRQn = 156,
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189 | TGI3D_IRQn = 157,
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190 | TGI3V_IRQn = 158,
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191 | TGI4A_IRQn = 159,
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192 | TGI4B_IRQn = 160,
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193 | TGI4C_IRQn = 161,
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194 | TGI4D_IRQn = 162,
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195 | TGI4V_IRQn = 163,
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196 |
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197 | CMI1_IRQn = 164,
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198 | CMI2_IRQn = 165,
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199 |
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200 | SGDEI0_IRQn = 166,
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201 | SGDEI1_IRQn = 167,
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202 | SGDEI2_IRQn = 168,
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203 | SGDEI3_IRQn = 169,
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204 |
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205 | ADI_IRQn = 170,
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206 | LMTI_IRQn = 171,
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207 |
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208 | SSII0_IRQn = 172, /*!< SSIF Interrupt */
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209 | SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
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210 | SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
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211 | SSII1_IRQn = 175, /*!< SSIF Interrupt */
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212 | SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
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213 | SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
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214 | SSII2_IRQn = 178, /*!< SSIF Interrupt */
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215 | SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
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216 | SSII3_IRQn = 180, /*!< SSIF Interrupt */
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217 | SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
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218 | SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
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219 | SSII4_IRQn = 183, /*!< SSIF Interrupt */
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220 | SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
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221 | SSII5_IRQn = 185, /*!< SSIF Interrupt */
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222 | SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
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223 | SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
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224 |
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225 | SPDIFI_IRQn = 188,
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226 |
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227 | INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
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228 | INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
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229 | INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
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230 | INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
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231 | INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
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232 | INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
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233 | INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
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234 | INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
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235 | INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
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236 | INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
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237 | INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
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238 | INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
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239 | INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
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240 | INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
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241 | INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
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242 | INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
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243 | INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
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244 | INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
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245 | INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
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246 | INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
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247 | INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
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248 | INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
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249 | INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
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250 | INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
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251 | INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
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252 | INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
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253 | INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
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254 | INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
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255 | INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
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256 | INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
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257 | INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
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258 | INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
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259 |
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260 | SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
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261 | SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
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262 | SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
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263 | SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
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264 | SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
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265 | SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
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266 | SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
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267 | SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
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268 | SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
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269 | SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
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270 | SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
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271 | SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
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272 | SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
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273 | SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
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274 | SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
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275 | SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
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276 | SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
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277 | SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
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278 | SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
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279 | SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
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280 | SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
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281 | SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
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282 | SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
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283 | SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
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284 | SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
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285 | SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
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286 | SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
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287 | SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
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288 | SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
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289 | SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
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290 | SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
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291 | SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
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292 |
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293 | INTRCANGERR_IRQn = 253,
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294 | INTRCANGRECC_IRQn = 254,
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295 | INTRCAN0REC_IRQn = 255,
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296 | INTRCAN0ERR_IRQn = 256,
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297 | INTRCAN0TRX_IRQn = 257,
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298 | INTRCAN1REC_IRQn = 258,
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299 | INTRCAN1ERR_IRQn = 259,
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300 | INTRCAN1TRX_IRQn = 260,
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301 | INTRCAN2REC_IRQn = 261,
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302 | INTRCAN2ERR_IRQn = 262,
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303 | INTRCAN2TRX_IRQn = 263,
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304 | INTRCAN3REC_IRQn = 264,
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305 | INTRCAN3ERR_IRQn = 265,
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306 | INTRCAN3TRX_IRQn = 266,
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307 | INTRCAN4REC_IRQn = 267,
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308 | INTRCAN4ERR_IRQn = 268,
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309 | INTRCAN4TRX_IRQn = 269,
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310 |
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311 | RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
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312 | RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
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313 | RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
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314 | RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
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315 | RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
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316 | RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
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317 | RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
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318 | RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
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319 | RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
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320 | RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
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321 | RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
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322 | RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
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323 | RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
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324 | RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
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325 | RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
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326 |
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327 | IEBBTD_IRQn = 285,
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328 | IEBBTERR_IRQn = 286,
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329 | IEBBTSTA_IRQn = 287,
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330 | IEBBTV_IRQn = 288,
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331 |
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332 | ISY_IRQn = 289,
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333 | IERR_IRQn = 290,
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334 | ITARG_IRQn = 291,
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335 | ISEC_IRQn = 292,
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336 | IBUF_IRQn = 293,
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337 | IREADY_IRQn = 294,
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338 |
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339 | STERB_IRQn = 295,
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340 | FLTENDI_IRQn = 296,
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341 | FLTREQ0I_IRQn = 297,
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342 | FLTREQ1I_IRQn = 298,
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343 |
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344 | MMC0_IRQn = 299,
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345 | MMC1_IRQn = 300,
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346 | MMC2_IRQn = 301,
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347 |
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348 | SCHI0_3_IRQn = 302,
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349 | SDHI0_0_IRQn = 303,
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350 | SDHI0_1_IRQn = 304,
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351 | SCHI1_3_IRQn = 305,
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352 | SDHI1_0_IRQn = 306,
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353 | SDHI1_1_IRQn = 307,
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354 |
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355 | ARM_IRQn = 308,
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356 | PRD_IRQn = 309,
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357 | CUP_IRQn = 310,
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358 |
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359 | SCUAI0_IRQn = 311,
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360 | SCUAI1_IRQn = 312,
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361 | SCUFDI0_IRQn = 313,
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362 | SCUFDI1_IRQn = 314,
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363 | SCUFDI2_IRQn = 315,
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364 | SCUFDI3_IRQn = 316,
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365 | SCUFUI0_IRQn = 317,
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366 | SCUFUI1_IRQn = 318,
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367 | SCUFUI2_IRQn = 319,
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368 | SCUFUI3_IRQn = 320,
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369 | SCUDVI0_IRQn = 321,
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370 | SCUDVI1_IRQn = 322,
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371 | SCUDVI2_IRQn = 323,
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372 | SCUDVI3_IRQn = 324,
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373 |
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374 | MLB_CINT_IRQn = 325,
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375 | MLB_SINT_IRQn = 326,
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376 |
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377 | DRC10_IRQn = 327,
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378 | DRC11_IRQn = 328,
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379 |
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380 | /* 329-330 Reserved */
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381 |
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382 | LINI0_INT_T_IRQn = 331,
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383 | LINI0_INT_R_IRQn = 332,
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384 | LINI0_INT_S_IRQn = 333,
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385 | LINI0_INT_M_IRQn = 334,
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386 | LINI1_INT_T_IRQn = 335,
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387 | LINI1_INT_R_IRQn = 336,
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388 | LINI1_INT_S_IRQn = 337,
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389 | LINI1_INT_M_IRQn = 338,
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390 |
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391 | /* 339-346 Reserved */
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392 |
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393 | SCIERI0_IRQn = 347,
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394 | SCIRXI0_IRQn = 348,
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395 | SCITXI0_IRQn = 349,
|
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396 | SCITEI0_IRQn = 350,
|
---|
397 | SCIERI1_IRQn = 351,
|
---|
398 | SCIRXI1_IRQn = 352,
|
---|
399 | SCITXI1_IRQn = 353,
|
---|
400 | SCITEI1_IRQn = 354,
|
---|
401 |
|
---|
402 | AVBI_DATA = 355,
|
---|
403 | AVBI_ERROR = 356,
|
---|
404 | AVBI_MANAGE = 357,
|
---|
405 | AVBI_MAC = 358,
|
---|
406 |
|
---|
407 | ETHERI_IRQn = 359,
|
---|
408 |
|
---|
409 | /* 360-363 Reserved */
|
---|
410 |
|
---|
411 | CEUI_IRQn = 364,
|
---|
412 |
|
---|
413 | /* 365-380 Reserved */
|
---|
414 |
|
---|
415 | H2XMLB_ERRINT_IRQn = 381,
|
---|
416 | H2XIC1_ERRINT_IRQn = 382,
|
---|
417 | X2HPERI1_ERRINT_IRQn = 383,
|
---|
418 | X2HPERR2_ERRINT_IRQn = 384,
|
---|
419 | X2HPERR34_ERRINT_IRQn= 385,
|
---|
420 | X2HPERR5_ERRINT_IRQn = 386,
|
---|
421 | X2HPERR67_ERRINT_IRQn= 387,
|
---|
422 | X2HDBGR_ERRINT_IRQn = 388,
|
---|
423 | X2HBSC_ERRINT_IRQn = 389,
|
---|
424 | X2HSPI1_ERRINT_IRQn = 390,
|
---|
425 | X2HSPI2_ERRINT_IRQn = 391,
|
---|
426 | PRRI_IRQn = 392,
|
---|
427 |
|
---|
428 | IFEI0_IRQn = 393,
|
---|
429 | OFFI0_IRQn = 394,
|
---|
430 | PFVEI0_IRQn = 395,
|
---|
431 | IFEI1_IRQn = 396,
|
---|
432 | OFFI1_IRQn = 397,
|
---|
433 | PFVEI1_IRQn = 398,
|
---|
434 |
|
---|
435 | /* 399-415 Reserved */
|
---|
436 |
|
---|
437 | TINT0_IRQn = 416,
|
---|
438 | TINT1_IRQn = 417,
|
---|
439 | TINT2_IRQn = 418,
|
---|
440 | TINT3_IRQn = 419,
|
---|
441 | TINT4_IRQn = 420,
|
---|
442 | TINT5_IRQn = 421,
|
---|
443 | TINT6_IRQn = 422,
|
---|
444 | TINT7_IRQn = 423,
|
---|
445 | TINT8_IRQn = 424,
|
---|
446 | TINT9_IRQn = 425,
|
---|
447 | TINT10_IRQn = 426,
|
---|
448 | TINT11_IRQn = 427,
|
---|
449 | TINT12_IRQn = 428,
|
---|
450 | TINT13_IRQn = 429,
|
---|
451 | TINT14_IRQn = 430,
|
---|
452 | TINT15_IRQn = 431,
|
---|
453 | TINT16_IRQn = 432,
|
---|
454 | TINT17_IRQn = 433,
|
---|
455 | TINT18_IRQn = 434,
|
---|
456 | TINT19_IRQn = 435,
|
---|
457 | TINT20_IRQn = 436,
|
---|
458 | TINT21_IRQn = 437,
|
---|
459 | TINT22_IRQn = 438,
|
---|
460 | TINT23_IRQn = 439,
|
---|
461 | TINT24_IRQn = 440,
|
---|
462 | TINT25_IRQn = 441,
|
---|
463 | TINT26_IRQn = 442,
|
---|
464 | TINT27_IRQn = 443,
|
---|
465 | TINT28_IRQn = 444,
|
---|
466 | TINT29_IRQn = 445,
|
---|
467 | TINT30_IRQn = 446,
|
---|
468 | TINT31_IRQn = 447,
|
---|
469 | TINT32_IRQn = 448,
|
---|
470 | TINT33_IRQn = 449,
|
---|
471 | TINT34_IRQn = 450,
|
---|
472 | TINT35_IRQn = 451,
|
---|
473 | TINT36_IRQn = 452,
|
---|
474 | TINT37_IRQn = 453,
|
---|
475 | TINT38_IRQn = 454,
|
---|
476 | TINT39_IRQn = 455,
|
---|
477 | TINT40_IRQn = 456,
|
---|
478 | TINT41_IRQn = 457,
|
---|
479 | TINT42_IRQn = 458,
|
---|
480 | TINT43_IRQn = 459,
|
---|
481 | TINT44_IRQn = 460,
|
---|
482 | TINT45_IRQn = 461,
|
---|
483 | TINT46_IRQn = 462,
|
---|
484 | TINT47_IRQn = 463,
|
---|
485 | TINT48_IRQn = 464,
|
---|
486 | TINT49_IRQn = 465,
|
---|
487 | TINT50_IRQn = 466,
|
---|
488 | TINT51_IRQn = 467,
|
---|
489 | TINT52_IRQn = 468,
|
---|
490 | TINT53_IRQn = 469,
|
---|
491 | TINT54_IRQn = 470,
|
---|
492 | TINT55_IRQn = 471,
|
---|
493 | TINT56_IRQn = 472,
|
---|
494 | TINT57_IRQn = 473,
|
---|
495 | TINT58_IRQn = 474,
|
---|
496 | TINT59_IRQn = 475,
|
---|
497 | TINT60_IRQn = 476,
|
---|
498 | TINT61_IRQn = 477,
|
---|
499 | TINT62_IRQn = 478,
|
---|
500 | TINT63_IRQn = 479,
|
---|
501 | TINT64_IRQn = 480,
|
---|
502 | TINT65_IRQn = 481,
|
---|
503 | TINT66_IRQn = 482,
|
---|
504 | TINT67_IRQn = 483,
|
---|
505 | TINT68_IRQn = 484,
|
---|
506 | TINT69_IRQn = 485,
|
---|
507 | TINT70_IRQn = 486,
|
---|
508 | TINT71_IRQn = 487,
|
---|
509 | TINT72_IRQn = 488,
|
---|
510 | TINT73_IRQn = 489,
|
---|
511 | TINT74_IRQn = 490,
|
---|
512 | TINT75_IRQn = 491,
|
---|
513 | TINT76_IRQn = 492,
|
---|
514 | TINT77_IRQn = 493,
|
---|
515 | TINT78_IRQn = 494,
|
---|
516 | TINT79_IRQn = 495,
|
---|
517 | TINT80_IRQn = 496,
|
---|
518 | TINT81_IRQn = 497,
|
---|
519 | TINT82_IRQn = 498,
|
---|
520 | TINT83_IRQn = 499,
|
---|
521 | TINT84_IRQn = 500,
|
---|
522 | TINT85_IRQn = 501,
|
---|
523 | TINT86_IRQn = 502,
|
---|
524 | TINT87_IRQn = 503,
|
---|
525 | TINT88_IRQn = 504,
|
---|
526 | TINT89_IRQn = 505,
|
---|
527 | TINT90_IRQn = 506,
|
---|
528 | TINT91_IRQn = 507,
|
---|
529 | TINT92_IRQn = 508,
|
---|
530 | TINT93_IRQn = 509,
|
---|
531 | TINT94_IRQn = 510,
|
---|
532 | TINT95_IRQn = 511,
|
---|
533 | TINT96_IRQn = 512,
|
---|
534 | TINT97_IRQn = 513,
|
---|
535 | TINT98_IRQn = 514,
|
---|
536 | TINT99_IRQn = 515,
|
---|
537 | TINT100_IRQn = 516,
|
---|
538 | TINT101_IRQn = 517,
|
---|
539 | TINT102_IRQn = 518,
|
---|
540 | TINT103_IRQn = 519,
|
---|
541 | TINT104_IRQn = 520,
|
---|
542 | TINT105_IRQn = 521,
|
---|
543 | TINT106_IRQn = 522,
|
---|
544 | TINT107_IRQn = 523,
|
---|
545 | TINT108_IRQn = 524,
|
---|
546 | TINT109_IRQn = 525,
|
---|
547 | TINT110_IRQn = 526,
|
---|
548 | TINT111_IRQn = 527,
|
---|
549 | TINT112_IRQn = 528,
|
---|
550 | TINT113_IRQn = 529,
|
---|
551 | TINT114_IRQn = 530,
|
---|
552 | TINT115_IRQn = 531,
|
---|
553 | TINT116_IRQn = 532,
|
---|
554 | TINT117_IRQn = 533,
|
---|
555 | TINT118_IRQn = 534,
|
---|
556 | TINT119_IRQn = 535,
|
---|
557 | TINT120_IRQn = 536,
|
---|
558 | TINT121_IRQn = 537,
|
---|
559 | TINT122_IRQn = 538,
|
---|
560 | TINT123_IRQn = 539,
|
---|
561 | TINT124_IRQn = 540,
|
---|
562 | TINT125_IRQn = 541,
|
---|
563 | TINT126_IRQn = 542,
|
---|
564 | TINT127_IRQn = 543,
|
---|
565 | TINT128_IRQn = 544,
|
---|
566 | TINT129_IRQn = 545,
|
---|
567 | TINT130_IRQn = 546,
|
---|
568 | TINT131_IRQn = 547,
|
---|
569 | TINT132_IRQn = 548,
|
---|
570 | TINT133_IRQn = 549,
|
---|
571 | TINT134_IRQn = 550,
|
---|
572 | TINT135_IRQn = 551,
|
---|
573 | TINT136_IRQn = 552,
|
---|
574 | TINT137_IRQn = 553,
|
---|
575 | TINT138_IRQn = 554,
|
---|
576 | TINT139_IRQn = 555,
|
---|
577 | TINT140_IRQn = 556,
|
---|
578 | TINT141_IRQn = 557,
|
---|
579 | TINT142_IRQn = 558,
|
---|
580 | TINT143_IRQn = 559,
|
---|
581 | TINT144_IRQn = 560,
|
---|
582 | TINT145_IRQn = 561,
|
---|
583 | TINT146_IRQn = 562,
|
---|
584 | TINT147_IRQn = 563,
|
---|
585 | TINT148_IRQn = 564,
|
---|
586 | TINT149_IRQn = 565,
|
---|
587 | TINT150_IRQn = 566,
|
---|
588 | TINT151_IRQn = 567,
|
---|
589 | TINT152_IRQn = 568,
|
---|
590 | TINT153_IRQn = 569,
|
---|
591 | TINT154_IRQn = 570,
|
---|
592 | TINT155_IRQn = 571,
|
---|
593 | TINT156_IRQn = 572,
|
---|
594 | TINT157_IRQn = 573,
|
---|
595 | TINT158_IRQn = 574,
|
---|
596 | TINT159_IRQn = 575,
|
---|
597 | TINT160_IRQn = 576,
|
---|
598 | TINT161_IRQn = 577,
|
---|
599 | TINT162_IRQn = 578,
|
---|
600 | TINT163_IRQn = 579,
|
---|
601 | TINT164_IRQn = 580,
|
---|
602 | TINT165_IRQn = 581,
|
---|
603 | TINT166_IRQn = 582,
|
---|
604 | TINT167_IRQn = 583,
|
---|
605 | TINT168_IRQn = 584,
|
---|
606 | TINT169_IRQn = 585,
|
---|
607 | TINT170_IRQn = 586
|
---|
608 |
|
---|
609 | } IRQn_Type;
|
---|
610 |
|
---|
611 | #define RZ_A1_IRQ_MAX TINT170_IRQn
|
---|
612 |
|
---|
613 | /******************************************************************************/
|
---|
614 | /* Peripheral memory map */
|
---|
615 | /******************************************************************************/
|
---|
616 |
|
---|
617 | #define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
|
---|
618 | #define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
|
---|
619 | #define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
|
---|
620 | #define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
|
---|
621 | #define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
|
---|
622 | #define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
|
---|
623 | #define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
|
---|
624 | #define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
|
---|
625 | #define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
|
---|
626 | #define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
|
---|
627 | #define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
|
---|
628 | #define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
|
---|
629 | #define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
|
---|
630 | #define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
|
---|
631 | #define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
|
---|
632 | #define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
|
---|
633 | #define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
|
---|
634 | #define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
|
---|
635 | #define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
|
---|
636 | #define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
|
---|
637 | #define L2C_310_BASE RZ_A1_PL310_BASE
|
---|
638 | #define TIMER_BASE RZ_A1_PRIVATE_TIMER
|
---|
639 |
|
---|
640 | /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
|
---|
641 | #define __CA_REV 0x0000U /*!< Core revision r0p0 */
|
---|
642 | #define __CORTEX_A 9U /*!< Cortex-A9 Core */
|
---|
643 | #if (__FPU_PRESENT != 1)
|
---|
644 | #undef __FPU_PRESENT
|
---|
645 | #define __FPU_PRESENT 1U /* FPU present */
|
---|
646 | #endif
|
---|
647 | #define __GIC_PRESENT 1U /* GIC present */
|
---|
648 | #define __TIM_PRESENT 0U /* TIM present */
|
---|
649 | #define __L2C_PRESENT 1U /* L2C present */
|
---|
650 |
|
---|
651 | #include "core_ca.h"
|
---|
652 | #include "nvic_wrapper.h"
|
---|
653 | #include <system_RZ_A1H.h>
|
---|
654 | #include "iodefine.h"
|
---|
655 |
|
---|
656 | /******************************************************************************/
|
---|
657 | /* Clock Settings */
|
---|
658 | /******************************************************************************/
|
---|
659 | /*
|
---|
660 | * Clock Mode 0 settings
|
---|
661 | * SW1-4(MD_CLK):ON
|
---|
662 | * SW1-5(MD_CLKS):ON
|
---|
663 | * FRQCR=0x1035
|
---|
664 | * CLKEN2 = 0b - unstable
|
---|
665 | * CLKEN[1:0]=01b - Output, Low, Low
|
---|
666 | * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
|
---|
667 | * FRQCR2=0x0001
|
---|
668 | * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
|
---|
669 | */
|
---|
670 | #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
|
---|
671 | #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
|
---|
672 | #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
|
---|
673 | #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
|
---|
674 | #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
|
---|
675 | #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
|
---|
676 | #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
|
---|
677 |
|
---|
678 | /*
|
---|
679 | * Clock Mode 1 settings
|
---|
680 | * SW1-4(MD_CLK):OFF
|
---|
681 | * SW1-5(MD_CLKS):ON
|
---|
682 | * FRQCR=0x1335
|
---|
683 | * CLKEN2 = 0b - unstable
|
---|
684 | * CLKEN[1:0]=01b - Output, Low, Low
|
---|
685 | * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
|
---|
686 | * FRQCR2=0x0003
|
---|
687 | * GFC[1:0] =11b - graphic clock is 1/3 bus clock
|
---|
688 | */
|
---|
689 | #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
|
---|
690 | #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
|
---|
691 | #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
|
---|
692 | #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
|
---|
693 | #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
|
---|
694 | #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
|
---|
695 | #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
|
---|
696 |
|
---|
697 | /******************************************************************************/
|
---|
698 | /* CPG Settings */
|
---|
699 | /******************************************************************************/
|
---|
700 | #define CPG_FRQCR_SHIFT_CKOEN2 (14)
|
---|
701 | #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
|
---|
702 | #define CPG_FRQCR_SHIFT_CKOEN0 (12)
|
---|
703 | #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
|
---|
704 | #define CPG_FRQCR_SHIFT_IFC (8)
|
---|
705 | #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
|
---|
706 |
|
---|
707 | #define CPG_FRQCR2_SHIFT_GFC (0)
|
---|
708 | #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
|
---|
709 |
|
---|
710 |
|
---|
711 | #define CPG_STBCR1_BIT_STBY (0x80u)
|
---|
712 | #define CPG_STBCR1_BIT_DEEP (0x40u)
|
---|
713 | #define CPG_STBCR2_BIT_HIZ (0x80u)
|
---|
714 | #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
|
---|
715 | #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
|
---|
716 | #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
|
---|
717 | #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
|
---|
718 | #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
|
---|
719 | #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
|
---|
720 | #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
|
---|
721 | #define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
|
---|
722 | #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
|
---|
723 | #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
|
---|
724 | #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
|
---|
725 | #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
|
---|
726 | #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
|
---|
727 | #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
|
---|
728 | #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
|
---|
729 | #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
|
---|
730 | #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
|
---|
731 | #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
|
---|
732 | #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
|
---|
733 | #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
|
---|
734 | #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
|
---|
735 | #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
|
---|
736 | #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
|
---|
737 | #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
|
---|
738 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
|
---|
739 | #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
|
---|
740 | #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
|
---|
741 | #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
|
---|
742 | #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
|
---|
743 | #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
|
---|
744 | #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
|
---|
745 | #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
|
---|
746 | #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
|
---|
747 | #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
|
---|
748 | #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
|
---|
749 | #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
|
---|
750 | #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
|
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751 | #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
|
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752 | #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
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753 | #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
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754 | #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
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755 | #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
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756 | #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
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757 | #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
|
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758 | #define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
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759 | #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
|
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760 | #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
|
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761 | #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
|
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762 | #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
|
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763 | #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
|
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764 | #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
|
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765 | #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
|
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766 | #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
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767 | #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
|
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768 | #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
|
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769 | #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
|
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770 | #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
|
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771 | #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
|
---|
772 | #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
|
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773 | #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
|
---|
774 | #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
|
---|
775 | #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
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776 | #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
|
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777 | #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
|
---|
778 | #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
|
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779 | #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
|
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780 | #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
|
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781 | #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
|
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782 | #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
|
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783 | #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
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784 | #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
|
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785 | #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
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786 | #define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
|
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787 | #define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
|
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788 | #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
|
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789 | #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
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790 | #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
|
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791 | #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
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---|
792 | #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
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793 | #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
|
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794 | #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
|
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795 | #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
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796 | #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
|
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797 | #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
|
---|
798 | #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
|
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799 | #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
|
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800 | #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
|
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801 | #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
|
---|
802 | #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
|
---|
803 | #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
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---|
804 | #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
|
---|
805 | #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
|
---|
806 | #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
|
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807 | #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
|
---|
808 | #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
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809 | #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
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810 | #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
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811 | #define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
|
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812 | #define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
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813 | #define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
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814 | #define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
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815 | #define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
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816 | #define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
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817 | #define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
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818 | #define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
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819 | #define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
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820 | #define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
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821 | #define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
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822 | #define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
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823 | #define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
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824 | #define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
|
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825 | #define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
|
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826 | #define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
|
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827 | #define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
|
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828 | #define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
|
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829 | #define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
|
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830 | #define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
|
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831 | #define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
|
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832 | #define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
|
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833 | #define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
|
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834 | #define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
|
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835 | #define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
|
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836 | #define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
|
---|
837 | #define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
|
---|
838 | #define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
|
---|
839 | #define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
|
---|
840 | #define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
|
---|
841 | #define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
|
---|
842 | #define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
|
---|
843 | #define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
|
---|
844 | #define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
|
---|
845 | #define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
|
---|
846 | #define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
|
---|
847 | #define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
|
---|
848 | #define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
|
---|
849 | #define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
|
---|
850 | #define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
|
---|
851 | #define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
|
---|
852 | #define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
|
---|
853 | #define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
|
---|
854 | #define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
|
---|
855 | #define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
|
---|
856 | #define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
|
---|
857 | #define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
|
---|
858 | #define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
|
---|
859 | #define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
|
---|
860 | #define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
|
---|
861 | #define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
|
---|
862 | #define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
|
---|
863 | #define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
|
---|
864 | #define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
|
---|
865 | #define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
|
---|
866 | #define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
|
---|
867 | #define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
|
---|
868 | #define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
|
---|
869 | #define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
|
---|
870 | #define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
|
---|
871 | #define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
|
---|
872 | #define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
|
---|
873 | #define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
|
---|
874 | #define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
|
---|
875 | #define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
|
---|
876 | #define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
|
---|
877 | #define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
|
---|
878 | #define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
|
---|
879 | #define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
|
---|
880 | #define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
|
---|
881 | #define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
|
---|
882 | #define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
|
---|
883 | #define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
|
---|
884 | #define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
|
---|
885 | #define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
|
---|
886 |
|
---|
887 | /******************************************************************************/
|
---|
888 | /* GPIO Settings */
|
---|
889 | /******************************************************************************/
|
---|
890 | #define GPIO_BIT_N0 (1u << 0)
|
---|
891 | #define GPIO_BIT_N1 (1u << 1)
|
---|
892 | #define GPIO_BIT_N2 (1u << 2)
|
---|
893 | #define GPIO_BIT_N3 (1u << 3)
|
---|
894 | #define GPIO_BIT_N4 (1u << 4)
|
---|
895 | #define GPIO_BIT_N5 (1u << 5)
|
---|
896 | #define GPIO_BIT_N6 (1u << 6)
|
---|
897 | #define GPIO_BIT_N7 (1u << 7)
|
---|
898 | #define GPIO_BIT_N8 (1u << 8)
|
---|
899 | #define GPIO_BIT_N9 (1u << 9)
|
---|
900 | #define GPIO_BIT_N10 (1u << 10)
|
---|
901 | #define GPIO_BIT_N11 (1u << 11)
|
---|
902 | #define GPIO_BIT_N12 (1u << 12)
|
---|
903 | #define GPIO_BIT_N13 (1u << 13)
|
---|
904 | #define GPIO_BIT_N14 (1u << 14)
|
---|
905 | #define GPIO_BIT_N15 (1u << 15)
|
---|
906 |
|
---|
907 | #define MD_BOOT10_MASK (0x3)
|
---|
908 |
|
---|
909 | #define MD_BOOT10_BM0 (0x0)
|
---|
910 | #define MD_BOOT10_BM1 (0x2)
|
---|
911 | #define MD_BOOT10_BM3 (0x1)
|
---|
912 | #define MD_BOOT10_BM4_5 (0x3)
|
---|
913 |
|
---|
914 | #define MD_CLK (1u << 2)
|
---|
915 | #define MD_CLKS (1u << 3)
|
---|
916 |
|
---|
917 |
|
---|
918 | #ifdef __cplusplus
|
---|
919 | }
|
---|
920 | #endif
|
---|
921 |
|
---|
922 | #endif // __RZ_A1H_H__
|
---|