1 | /* File: startup_ARMCM3.s
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2 | * Purpose: startup file for Cortex-M3/M4 devices. Should use with
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3 | * GNU Tools for ARM Embedded Processors
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4 | * Version: V1.1
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5 | * Date: 17 June 2011
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6 | *
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7 | * Copyright (C) 2011 ARM Limited. All rights reserved.
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8 | * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
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9 | * processor based microcontrollers. This file can be freely distributed
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10 | * within development tools that are supporting such ARM based processors.
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11 | *
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12 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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13 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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15 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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16 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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17 | */
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18 | .syntax unified
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19 | .extern _start
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20 |
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21 | @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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22 | .equ Mode_USR , 0x10
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23 | .equ Mode_FIQ , 0x11
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24 | .equ Mode_IRQ , 0x12
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25 | .equ Mode_SVC , 0x13
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26 | .equ Mode_ABT , 0x17
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27 | .equ Mode_UND , 0x1B
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28 | .equ Mode_SYS , 0x1F
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29 |
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30 | .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
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31 | .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
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32 | .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
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33 |
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34 | @ Stack Configuration
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35 |
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36 | .EQU UND_Stack_Size , 0x00000100
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37 | .EQU SVC_Stack_Size , 0x00008000
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38 | .EQU ABT_Stack_Size , 0x00000100
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39 | .EQU FIQ_Stack_Size , 0x00000100
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40 | .EQU IRQ_Stack_Size , 0x00008000
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41 | .EQU USR_Stack_Size , 0x00004000
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42 |
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43 | .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
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44 |
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45 | .section .stack
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46 | .align 3
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47 | .globl __StackTop
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48 | .globl __StackLimit
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49 | __StackLimit:
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50 | .space ISR_Stack_Size
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51 | __initial_sp:
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52 | .space USR_Stack_Size
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53 | .size __StackLimit, . - __StackLimit
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54 | __StackTop:
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55 | .size __StackTop, . - __StackTop
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56 |
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57 |
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58 | @ Heap Configuration
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59 |
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60 | .EQU Heap_Size , 0x00080000
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61 |
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62 | .section .heap
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63 | .align 3
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64 | .globl __HeapBase
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65 | .globl __HeapLimit
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66 | __HeapBase:
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67 | .space Heap_Size
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68 | .size __HeapBase, . - __HeapBase
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69 | __HeapLimit:
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70 | .size __HeapLimit, . - __HeapLimit
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71 |
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72 |
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73 | .section .isr_vector
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74 | .align 2
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75 | .globl __isr_vector
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76 | __isr_vector:
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77 | .long 0xe59ff018 /* 0x00 */
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78 | .long 0xe59ff018 /* 0x04 */
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79 | .long 0xe59ff018 /* 0x08 */
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80 | .long 0xe59ff018 /* 0x0c */
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81 | .long 0xe59ff018 /* 0x10 */
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82 | .long 0xe59ff018 /* 0x14 */
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83 | .long 0xe59ff018 /* 0x18 */
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84 | .long 0xe59ff018 /* 0x1c */
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85 |
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86 | .long Reset_Handler /* 0x20 */
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87 | .long _kernel_undef_handler /* 0x24 */
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88 | .long _kernel_svc_handler /* 0x28 */
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89 | .long _kernel_pabort_handler /* 0x2c */
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90 | .long _kernel_dabort_handler /* 0x30 */
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91 | .long 0 /* Reserved */
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92 | .long _kernel_irq_handler /* IRQ */
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93 | .long _kernel_fiq_handler /* FIQ */
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94 |
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95 |
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96 | .size __isr_vector, . - __isr_vector
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97 |
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98 | .text
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99 | .align 2
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100 | .globl Reset_Handler
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101 | .type Reset_Handler, %function
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102 | Reset_Handler:
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103 | @ Mask interrupts
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104 | CPSID if
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105 |
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106 | @ Put any cores other than 0 to sleep
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107 | mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
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108 | ands r0, r0, #3
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109 | goToSleep:
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110 | wfine
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111 | bne goToSleep
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112 |
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113 | @ Reset SCTLR Settings
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114 | mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
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115 | bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
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116 | bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
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117 | bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
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118 | bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
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119 | bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
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120 | mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
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121 | isb
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122 |
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123 | @ Configure ACTLR
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124 | MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register
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125 | ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1)
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126 | MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register
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127 |
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128 | @ Set Vector Base Address Register (VBAR) to point to this application's vector table
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129 | ldr r0, =__isr_vector
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130 | mcr p15, 0, r0, c12, c0, 0
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131 |
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132 | @ Setup Stack for each exceptional mode
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133 | /* ldr r0, =__StackTop */
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134 | ldr r0, =(__StackTop - USR_Stack_Size)
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135 |
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136 | @ Enter Undefined Instruction Mode and set its Stack Pointer
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137 | msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
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138 | mov sp, r0
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139 | sub r0, r0, #UND_Stack_Size
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140 |
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141 | @ Enter Abort Mode and set its Stack Pointer
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142 | msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
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143 | mov sp, r0
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144 | sub r0, r0, #ABT_Stack_Size
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145 |
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146 | @ Enter FIQ Mode and set its Stack Pointer
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147 | msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
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148 | mov sp, r0
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149 | sub r0, r0, #FIQ_Stack_Size
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150 |
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151 | @ Enter IRQ Mode and set its Stack Pointer
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152 | msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
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153 | mov sp, r0
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154 | sub r0, r0, #IRQ_Stack_Size
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155 |
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156 | @ Enter Supervisor Mode and set its Stack Pointer
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157 | msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
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158 | mov sp, r0
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159 | sub r0, r0, #SVC_Stack_Size
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160 |
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161 | @ Enter System Mode to complete initialization and enter kernel
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162 | msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
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163 | mov sp, r0
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164 |
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165 | @ USR/SYS stack pointer will be set during kernel init
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166 | ldr r0, =SystemInit
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167 | blx r0
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168 |
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169 | @ Unmask interrupts
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170 | CPSIE if
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171 |
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172 | @ data sections copy
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173 | ldr r4, =__copy_table_start__
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174 | ldr r5, =__copy_table_end__
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175 |
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176 | .L_loop0:
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177 | cmp r4, r5
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178 | bge .L_loop0_done
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179 | ldr r1, [r4]
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180 | ldr r2, [r4, #4]
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181 | ldr r3, [r4, #8]
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182 |
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183 | .L_loop0_0:
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184 | subs r3, #4
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185 | ittt ge
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186 | ldrge r0, [r1, r3]
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187 | strge r0, [r2, r3]
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188 | bge .L_loop0_0
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189 |
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190 | adds r4, #12
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191 | b .L_loop0
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192 |
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193 | .L_loop0_done:
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194 |
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195 | @ bss sections clear
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196 | ldr r3, =__zero_table_start__
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197 | ldr r4, =__zero_table_end__
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198 |
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199 | .L_loop2:
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200 | cmp r3, r4
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201 | bge .L_loop2_done
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202 | ldr r1, [r3]
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203 | ldr r2, [r3, #4]
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204 | movs r0, 0
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205 |
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206 | .L_loop2_0:
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207 | subs r2, #4
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208 | itt ge
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209 | strge r0, [r1, r2]
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210 | bge .L_loop2_0
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211 |
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212 | adds r3, #8
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213 | b .L_loop2
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214 | .L_loop2_done:
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215 |
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216 |
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217 | ldr r0, =_start
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218 | bx r0
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219 |
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220 | ldr r0, sf_boot @ dummy to keep boot loader area
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221 | loop_here:
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222 | b loop_here
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223 |
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224 | sf_boot:
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225 | .word boot_loader
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226 |
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227 | .pool
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228 | .size Reset_Handler, . - Reset_Handler
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229 |
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230 |
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231 | .text
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232 |
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233 | /* Macro to define default handlers. Default handler
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234 | * will be weak symbol and just dead loops. They can be
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235 | * overwritten by other handlers */
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236 | .macro def_default_handler handler_name
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237 | .align 1
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238 | .thumb_func
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239 | .weak \handler_name
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240 | .type \handler_name, %function
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241 | \handler_name :
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242 | b .
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243 | .size \handler_name, . - \handler_name
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244 | .endm
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245 |
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246 | def_default_handler Undef_Handler
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247 | def_default_handler SVC_Handler
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248 | def_default_handler PAbt_Handler
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249 | def_default_handler DAbt_Handler
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250 | def_default_handler IRQ_Handler
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251 | def_default_handler FIQ_Handler
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252 |
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253 | .END
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