[429] | 1 | /**************************************************************************//**
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| 2 | * @file cmsis_gcc.h
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| 3 | * @brief CMSIS compiler specific macros, functions, instructions
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| 4 | * @version V1.0.2
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| 5 | * @date 09. April 2018
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| 6 | ******************************************************************************/
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| 7 | /*
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| 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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| 9 | *
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| 10 | * SPDX-License-Identifier: Apache-2.0
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| 11 | *
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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| 13 | * not use this file except in compliance with the License.
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| 14 | * You may obtain a copy of the License at
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| 15 | *
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| 16 | * www.apache.org/licenses/LICENSE-2.0
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| 17 | *
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| 18 | * Unless required by applicable law or agreed to in writing, software
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 21 | * See the License for the specific language governing permissions and
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| 22 | * limitations under the License.
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| 23 | */
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| 24 |
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| 25 | #ifndef __CMSIS_GCC_H
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| 26 | #define __CMSIS_GCC_H
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| 27 |
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| 28 | /* ignore some GCC warnings */
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| 29 | #pragma GCC diagnostic push
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| 30 | #pragma GCC diagnostic ignored "-Wsign-conversion"
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| 31 | #pragma GCC diagnostic ignored "-Wconversion"
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| 32 | #pragma GCC diagnostic ignored "-Wunused-parameter"
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| 33 |
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| 34 | /* Fallback for __has_builtin */
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| 35 | #ifndef __has_builtin
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| 36 | #define __has_builtin(x) (0)
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| 37 | #endif
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| 38 |
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| 39 | /* CMSIS compiler specific defines */
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| 40 | #ifndef __ASM
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| 41 | #define __ASM asm
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| 42 | #endif
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| 43 | #ifndef __INLINE
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| 44 | #define __INLINE inline
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| 45 | #endif
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| 46 | #ifndef __FORCEINLINE
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| 47 | #define __FORCEINLINE __attribute__((always_inline))
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| 48 | #endif
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| 49 | #ifndef __STATIC_INLINE
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| 50 | #define __STATIC_INLINE static inline
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| 51 | #endif
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| 52 | #ifndef __STATIC_FORCEINLINE
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| 53 | #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
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| 54 | #endif
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| 55 | #ifndef __NO_RETURN
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| 56 | #define __NO_RETURN __attribute__((__noreturn__))
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| 57 | #endif
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| 58 | #ifndef CMSIS_DEPRECATED
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| 59 | #define CMSIS_DEPRECATED __attribute__((deprecated))
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| 60 | #endif
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| 61 | #ifndef __USED
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| 62 | #define __USED __attribute__((used))
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| 63 | #endif
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| 64 | #ifndef __WEAK
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| 65 | #define __WEAK __attribute__((weak))
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| 66 | #endif
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| 67 | #ifndef __PACKED
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| 68 | #define __PACKED __attribute__((packed, aligned(1)))
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| 69 | #endif
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| 70 | #ifndef __PACKED_STRUCT
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| 71 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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| 72 | #endif
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| 73 | #ifndef __UNALIGNED_UINT16_WRITE
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| 74 | #pragma GCC diagnostic push
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| 75 | #pragma GCC diagnostic ignored "-Wpacked"
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| 76 | /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
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| 77 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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| 78 | #pragma GCC diagnostic pop
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| 79 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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| 80 | #endif
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| 81 | #ifndef __UNALIGNED_UINT16_READ
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| 82 | #pragma GCC diagnostic push
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| 83 | #pragma GCC diagnostic ignored "-Wpacked"
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| 84 | /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
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| 85 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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| 86 | #pragma GCC diagnostic pop
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| 87 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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| 88 | #endif
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| 89 | #ifndef __UNALIGNED_UINT32_WRITE
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| 90 | #pragma GCC diagnostic push
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| 91 | #pragma GCC diagnostic ignored "-Wpacked"
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| 92 | /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
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| 93 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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| 94 | #pragma GCC diagnostic pop
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| 95 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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| 96 | #endif
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| 97 | #ifndef __UNALIGNED_UINT32_READ
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| 98 | #pragma GCC diagnostic push
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| 99 | #pragma GCC diagnostic ignored "-Wpacked"
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| 100 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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| 101 | #pragma GCC diagnostic pop
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| 102 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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| 103 | #endif
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| 104 | #ifndef __ALIGNED
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| 105 | #define __ALIGNED(x) __attribute__((aligned(x)))
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| 106 | #endif
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| 107 |
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| 108 | /* ########################## Core Instruction Access ######################### */
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| 109 | /**
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| 110 | \brief No Operation
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| 111 | */
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| 112 | #define __NOP() __ASM volatile ("nop")
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| 113 |
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| 114 | /**
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| 115 | \brief Wait For Interrupt
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| 116 | */
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| 117 | #define __WFI() __ASM volatile ("wfi")
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| 118 |
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| 119 | /**
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| 120 | \brief Wait For Event
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| 121 | */
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| 122 | #define __WFE() __ASM volatile ("wfe")
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| 123 |
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| 124 | /**
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| 125 | \brief Send Event
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| 126 | */
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| 127 | #define __SEV() __ASM volatile ("sev")
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| 128 |
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| 129 | /**
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| 130 | \brief Instruction Synchronization Barrier
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| 131 | \details Instruction Synchronization Barrier flushes the pipeline in the processor,
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| 132 | so that all instructions following the ISB are fetched from cache or memory,
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| 133 | after the instruction has been completed.
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| 134 | */
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| 135 | __STATIC_FORCEINLINE void __ISB(void)
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| 136 | {
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| 137 | __ASM volatile ("isb 0xF":::"memory");
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| 138 | }
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| 139 |
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| 140 |
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| 141 | /**
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| 142 | \brief Data Synchronization Barrier
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| 143 | \details Acts as a special kind of Data Memory Barrier.
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| 144 | It completes when all explicit memory accesses before this instruction complete.
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| 145 | */
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| 146 | __STATIC_FORCEINLINE void __DSB(void)
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| 147 | {
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| 148 | __ASM volatile ("dsb 0xF":::"memory");
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| 149 | }
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| 150 |
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| 151 | /**
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| 152 | \brief Data Memory Barrier
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| 153 | \details Ensures the apparent order of the explicit memory operations before
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| 154 | and after the instruction, without ensuring their completion.
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| 155 | */
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| 156 | __STATIC_FORCEINLINE void __DMB(void)
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| 157 | {
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| 158 | __ASM volatile ("dmb 0xF":::"memory");
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| 159 | }
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| 160 |
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| 161 | /**
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| 162 | \brief Reverse byte order (32 bit)
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| 163 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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| 164 | \param [in] value Value to reverse
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| 165 | \return Reversed value
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| 166 | */
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| 167 | __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
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| 168 | {
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| 169 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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| 170 | return __builtin_bswap32(value);
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| 171 | #else
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| 172 | uint32_t result;
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| 173 |
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| 174 | __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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| 175 | return result;
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| 176 | #endif
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| 177 | }
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| 178 |
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| 179 | /**
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| 180 | \brief Reverse byte order (16 bit)
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| 181 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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| 182 | \param [in] value Value to reverse
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| 183 | \return Reversed value
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| 184 | */
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| 185 | #ifndef __NO_EMBEDDED_ASM
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| 186 | __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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| 187 | {
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| 188 | uint32_t result;
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| 189 | __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
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| 190 | return result;
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| 191 | }
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| 192 | #endif
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| 193 |
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| 194 | /**
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| 195 | \brief Reverse byte order (16 bit)
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| 196 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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| 197 | \param [in] value Value to reverse
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| 198 | \return Reversed value
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| 199 | */
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| 200 | __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
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| 201 | {
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| 202 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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| 203 | return (int16_t)__builtin_bswap16(value);
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| 204 | #else
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| 205 | int16_t result;
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| 206 |
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| 207 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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| 208 | return result;
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| 209 | #endif
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| 210 | }
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| 211 |
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| 212 | /**
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| 213 | \brief Rotate Right in unsigned value (32 bit)
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| 214 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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| 215 | \param [in] op1 Value to rotate
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| 216 | \param [in] op2 Number of Bits to rotate
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| 217 | \return Rotated value
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| 218 | */
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| 219 | __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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| 220 | {
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| 221 | op2 %= 32U;
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| 222 | if (op2 == 0U) {
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| 223 | return op1;
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| 224 | }
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| 225 | return (op1 >> op2) | (op1 << (32U - op2));
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| 226 | }
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| 227 |
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| 228 |
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| 229 | /**
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| 230 | \brief Breakpoint
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| 231 | \param [in] value is ignored by the processor.
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| 232 | If required, a debugger can use it to store additional information about the breakpoint.
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| 233 | */
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| 234 | #define __BKPT(value) __ASM volatile ("bkpt "#value)
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| 235 |
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| 236 | /**
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| 237 | \brief Reverse bit order of value
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| 238 | \details Reverses the bit order of the given value.
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| 239 | \param [in] value Value to reverse
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| 240 | \return Reversed value
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| 241 | */
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| 242 | __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
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| 243 | {
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| 244 | uint32_t result;
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| 245 |
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| 246 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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| 247 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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| 248 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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| 249 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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| 250 | #else
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| 251 | int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
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| 252 |
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| 253 | result = value; /* r will be reversed bits of v; first get LSB of v */
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| 254 | for (value >>= 1U; value; value >>= 1U)
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| 255 | {
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| 256 | result <<= 1U;
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| 257 | result |= value & 1U;
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| 258 | s--;
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| 259 | }
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| 260 | result <<= s; /* shift when v's highest bits are zero */
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| 261 | #endif
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| 262 | return result;
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| 263 | }
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| 264 |
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| 265 | /**
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| 266 | \brief Count leading zeros
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| 267 | \param [in] value Value to count the leading zeros
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| 268 | \return number of leading zeros in value
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| 269 | */
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| 270 | #define __CLZ (uint8_t)__builtin_clz
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| 271 |
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| 272 | /**
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| 273 | \brief LDR Exclusive (8 bit)
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| 274 | \details Executes a exclusive LDR instruction for 8 bit value.
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| 275 | \param [in] ptr Pointer to data
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| 276 | \return value of type uint8_t at (*ptr)
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| 277 | */
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| 278 | __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
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| 279 | {
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| 280 | uint32_t result;
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| 281 |
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| 282 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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| 283 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
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| 284 | #else
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| 285 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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| 286 | accepted by assembler. So has to use following less efficient pattern.
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| 287 | */
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| 288 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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| 289 | #endif
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| 290 | return ((uint8_t) result); /* Add explicit type cast here */
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| 291 | }
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| 292 |
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| 293 |
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| 294 | /**
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| 295 | \brief LDR Exclusive (16 bit)
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| 296 | \details Executes a exclusive LDR instruction for 16 bit values.
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| 297 | \param [in] ptr Pointer to data
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| 298 | \return value of type uint16_t at (*ptr)
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| 299 | */
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| 300 | __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
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| 301 | {
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| 302 | uint32_t result;
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| 303 |
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| 304 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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| 305 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
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| 306 | #else
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| 307 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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| 308 | accepted by assembler. So has to use following less efficient pattern.
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| 309 | */
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| 310 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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| 311 | #endif
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| 312 | return ((uint16_t) result); /* Add explicit type cast here */
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| 313 | }
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| 314 |
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| 315 |
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| 316 | /**
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| 317 | \brief LDR Exclusive (32 bit)
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| 318 | \details Executes a exclusive LDR instruction for 32 bit values.
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| 319 | \param [in] ptr Pointer to data
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| 320 | \return value of type uint32_t at (*ptr)
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| 321 | */
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| 322 | __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
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| 323 | {
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| 324 | uint32_t result;
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| 325 |
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| 326 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
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| 327 | return(result);
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| 328 | }
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| 329 |
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| 330 |
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| 331 | /**
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| 332 | \brief STR Exclusive (8 bit)
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| 333 | \details Executes a exclusive STR instruction for 8 bit values.
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| 334 | \param [in] value Value to store
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| 335 | \param [in] ptr Pointer to location
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| 336 | \return 0 Function succeeded
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| 337 | \return 1 Function failed
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| 338 | */
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| 339 | __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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| 340 | {
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| 341 | uint32_t result;
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| 342 |
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| 343 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
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| 344 | return(result);
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| 345 | }
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| 346 |
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| 347 |
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| 348 | /**
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| 349 | \brief STR Exclusive (16 bit)
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| 350 | \details Executes a exclusive STR instruction for 16 bit values.
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| 351 | \param [in] value Value to store
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| 352 | \param [in] ptr Pointer to location
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| 353 | \return 0 Function succeeded
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| 354 | \return 1 Function failed
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| 355 | */
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| 356 | __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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| 357 | {
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| 358 | uint32_t result;
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| 359 |
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| 360 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
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| 361 | return(result);
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| 362 | }
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| 363 |
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| 364 |
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| 365 | /**
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| 366 | \brief STR Exclusive (32 bit)
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| 367 | \details Executes a exclusive STR instruction for 32 bit values.
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| 368 | \param [in] value Value to store
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| 369 | \param [in] ptr Pointer to location
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| 370 | \return 0 Function succeeded
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| 371 | \return 1 Function failed
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| 372 | */
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| 373 | __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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| 374 | {
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| 375 | uint32_t result;
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| 376 |
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| 377 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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| 378 | return(result);
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| 379 | }
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| 380 |
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| 381 |
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| 382 | /**
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| 383 | \brief Remove the exclusive lock
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| 384 | \details Removes the exclusive lock which is created by LDREX.
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| 385 | */
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| 386 | __STATIC_FORCEINLINE void __CLREX(void)
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| 387 | {
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| 388 | __ASM volatile ("clrex" ::: "memory");
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| 389 | }
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| 390 |
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| 391 | /**
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| 392 | \brief Signed Saturate
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| 393 | \details Saturates a signed value.
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| 394 | \param [in] value Value to be saturated
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| 395 | \param [in] sat Bit position to saturate to (1..32)
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| 396 | \return Saturated value
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| 397 | */
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| 398 | #define __SSAT(ARG1,ARG2) \
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| 399 | __extension__ \
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| 400 | ({ \
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| 401 | int32_t __RES, __ARG1 = (ARG1); \
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| 402 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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| 403 | __RES; \
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| 404 | })
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| 405 |
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| 406 |
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| 407 | /**
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| 408 | \brief Unsigned Saturate
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| 409 | \details Saturates an unsigned value.
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| 410 | \param [in] value Value to be saturated
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| 411 | \param [in] sat Bit position to saturate to (0..31)
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| 412 | \return Saturated value
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| 413 | */
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| 414 | #define __USAT(ARG1,ARG2) \
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| 415 | __extension__ \
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| 416 | ({ \
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| 417 | uint32_t __RES, __ARG1 = (ARG1); \
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| 418 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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| 419 | __RES; \
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| 420 | })
|
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| 421 |
|
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| 422 | /* ########################### Core Function Access ########################### */
|
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| 423 |
|
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| 424 | /**
|
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| 425 | \brief Enable IRQ Interrupts
|
---|
| 426 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
---|
| 427 | Can only be executed in Privileged modes.
|
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| 428 | */
|
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| 429 | __STATIC_FORCEINLINE void __enable_irq(void)
|
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| 430 | {
|
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| 431 | __ASM volatile ("cpsie i" : : : "memory");
|
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| 432 | }
|
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| 433 |
|
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| 434 | /**
|
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| 435 | \brief Disable IRQ Interrupts
|
---|
| 436 | \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
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| 437 | Can only be executed in Privileged modes.
|
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| 438 | */
|
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| 439 | __STATIC_FORCEINLINE void __disable_irq(void)
|
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| 440 | {
|
---|
| 441 | __ASM volatile ("cpsid i" : : : "memory");
|
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| 442 | }
|
---|
| 443 |
|
---|
| 444 | /**
|
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| 445 | \brief Get FPSCR
|
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| 446 | \details Returns the current value of the Floating Point Status/Control register.
|
---|
| 447 | \return Floating Point Status/Control register value
|
---|
| 448 | */
|
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| 449 | __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
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| 450 | {
|
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| 451 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
---|
| 452 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
---|
| 453 | #if __has_builtin(__builtin_arm_get_fpscr)
|
---|
| 454 | // Re-enable using built-in when GCC has been fixed
|
---|
| 455 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
---|
| 456 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
---|
| 457 | return __builtin_arm_get_fpscr();
|
---|
| 458 | #else
|
---|
| 459 | uint32_t result;
|
---|
| 460 |
|
---|
| 461 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
---|
| 462 | return(result);
|
---|
| 463 | #endif
|
---|
| 464 | #else
|
---|
| 465 | return(0U);
|
---|
| 466 | #endif
|
---|
| 467 | }
|
---|
| 468 |
|
---|
| 469 | /**
|
---|
| 470 | \brief Set FPSCR
|
---|
| 471 | \details Assigns the given value to the Floating Point Status/Control register.
|
---|
| 472 | \param [in] fpscr Floating Point Status/Control value to set
|
---|
| 473 | */
|
---|
| 474 | __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
---|
| 475 | {
|
---|
| 476 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
---|
| 477 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
---|
| 478 | #if __has_builtin(__builtin_arm_set_fpscr)
|
---|
| 479 | // Re-enable using built-in when GCC has been fixed
|
---|
| 480 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
|
---|
| 481 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
|
---|
| 482 | __builtin_arm_set_fpscr(fpscr);
|
---|
| 483 | #else
|
---|
| 484 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
|
---|
| 485 | #endif
|
---|
| 486 | #else
|
---|
| 487 | (void)fpscr;
|
---|
| 488 | #endif
|
---|
| 489 | }
|
---|
| 490 |
|
---|
| 491 | /** \brief Get CPSR Register
|
---|
| 492 | \return CPSR Register value
|
---|
| 493 | */
|
---|
| 494 | __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
|
---|
| 495 | {
|
---|
| 496 | uint32_t result;
|
---|
| 497 | __ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
---|
| 498 | return(result);
|
---|
| 499 | }
|
---|
| 500 |
|
---|
| 501 | /** \brief Set CPSR Register
|
---|
| 502 | \param [in] cpsr CPSR value to set
|
---|
| 503 | */
|
---|
| 504 | __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
---|
| 505 | {
|
---|
| 506 | __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
|
---|
| 507 | }
|
---|
| 508 |
|
---|
| 509 | /** \brief Get Mode
|
---|
| 510 | \return Processor Mode
|
---|
| 511 | */
|
---|
| 512 | __STATIC_FORCEINLINE uint32_t __get_mode(void)
|
---|
| 513 | {
|
---|
| 514 | return (__get_CPSR() & 0x1FU);
|
---|
| 515 | }
|
---|
| 516 |
|
---|
| 517 | /** \brief Set Mode
|
---|
| 518 | \param [in] mode Mode value to set
|
---|
| 519 | */
|
---|
| 520 | __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
---|
| 521 | {
|
---|
| 522 | __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
---|
| 523 | }
|
---|
| 524 |
|
---|
| 525 | /** \brief Get Stack Pointer
|
---|
| 526 | \return Stack Pointer value
|
---|
| 527 | */
|
---|
| 528 | __STATIC_FORCEINLINE uint32_t __get_SP(void)
|
---|
| 529 | {
|
---|
| 530 | uint32_t result;
|
---|
| 531 | __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
---|
| 532 | return result;
|
---|
| 533 | }
|
---|
| 534 |
|
---|
| 535 | /** \brief Set Stack Pointer
|
---|
| 536 | \param [in] stack Stack Pointer value to set
|
---|
| 537 | */
|
---|
| 538 | __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
---|
| 539 | {
|
---|
| 540 | __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
---|
| 541 | }
|
---|
| 542 |
|
---|
| 543 | /** \brief Get USR/SYS Stack Pointer
|
---|
| 544 | \return USR/SYS Stack Pointer value
|
---|
| 545 | */
|
---|
| 546 | __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
|
---|
| 547 | {
|
---|
| 548 | uint32_t cpsr = __get_CPSR();
|
---|
| 549 | uint32_t result;
|
---|
| 550 | __ASM volatile(
|
---|
| 551 | "CPS #0x1F \n"
|
---|
| 552 | "MOV %0, sp " : "=r"(result) : : "memory"
|
---|
| 553 | );
|
---|
| 554 | __set_CPSR(cpsr);
|
---|
| 555 | __ISB();
|
---|
| 556 | return result;
|
---|
| 557 | }
|
---|
| 558 |
|
---|
| 559 | /** \brief Set USR/SYS Stack Pointer
|
---|
| 560 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
---|
| 561 | */
|
---|
| 562 | __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
---|
| 563 | {
|
---|
| 564 | uint32_t cpsr = __get_CPSR();
|
---|
| 565 | __ASM volatile(
|
---|
| 566 | "CPS #0x1F \n"
|
---|
| 567 | "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
|
---|
| 568 | );
|
---|
| 569 | __set_CPSR(cpsr);
|
---|
| 570 | __ISB();
|
---|
| 571 | }
|
---|
| 572 |
|
---|
| 573 | /** \brief Get FPEXC
|
---|
| 574 | \return Floating Point Exception Control register value
|
---|
| 575 | */
|
---|
| 576 | __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
---|
| 577 | {
|
---|
| 578 | #if (__FPU_PRESENT == 1)
|
---|
| 579 | uint32_t result;
|
---|
| 580 | __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
|
---|
| 581 | return(result);
|
---|
| 582 | #else
|
---|
| 583 | return(0);
|
---|
| 584 | #endif
|
---|
| 585 | }
|
---|
| 586 |
|
---|
| 587 | /** \brief Set FPEXC
|
---|
| 588 | \param [in] fpexc Floating Point Exception Control value to set
|
---|
| 589 | */
|
---|
| 590 | __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
---|
| 591 | {
|
---|
| 592 | #if (__FPU_PRESENT == 1)
|
---|
| 593 | __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
---|
| 594 | #endif
|
---|
| 595 | }
|
---|
| 596 |
|
---|
| 597 | /*
|
---|
| 598 | * Include common core functions to access Coprocessor 15 registers
|
---|
| 599 | */
|
---|
| 600 |
|
---|
| 601 | #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
---|
| 602 | #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
---|
| 603 | #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
---|
| 604 | #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
---|
| 605 |
|
---|
| 606 | #include "cmsis_cp15.h"
|
---|
| 607 |
|
---|
| 608 | /** \brief Enable Floating Point Unit
|
---|
| 609 |
|
---|
| 610 | Critical section, called from undef handler, so systick is disabled
|
---|
| 611 | */
|
---|
| 612 | __STATIC_INLINE void __FPU_Enable(void)
|
---|
| 613 | {
|
---|
| 614 | __ASM volatile(
|
---|
| 615 | //Permit access to VFP/NEON, registers by modifying CPACR
|
---|
| 616 | " MRC p15,0,R1,c1,c0,2 \n"
|
---|
| 617 | " ORR R1,R1,#0x00F00000 \n"
|
---|
| 618 | " MCR p15,0,R1,c1,c0,2 \n"
|
---|
| 619 |
|
---|
| 620 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
---|
| 621 | " ISB \n"
|
---|
| 622 |
|
---|
| 623 | //Enable VFP/NEON
|
---|
| 624 | " VMRS R1,FPEXC \n"
|
---|
| 625 | " ORR R1,R1,#0x40000000 \n"
|
---|
| 626 | " VMSR FPEXC,R1 \n"
|
---|
| 627 |
|
---|
| 628 | //Initialise VFP/NEON registers to 0
|
---|
| 629 | " MOV R2,#0 \n"
|
---|
| 630 |
|
---|
| 631 | //Initialise D16 registers to 0
|
---|
| 632 | " VMOV D0, R2,R2 \n"
|
---|
| 633 | " VMOV D1, R2,R2 \n"
|
---|
| 634 | " VMOV D2, R2,R2 \n"
|
---|
| 635 | " VMOV D3, R2,R2 \n"
|
---|
| 636 | " VMOV D4, R2,R2 \n"
|
---|
| 637 | " VMOV D5, R2,R2 \n"
|
---|
| 638 | " VMOV D6, R2,R2 \n"
|
---|
| 639 | " VMOV D7, R2,R2 \n"
|
---|
| 640 | " VMOV D8, R2,R2 \n"
|
---|
| 641 | " VMOV D9, R2,R2 \n"
|
---|
| 642 | " VMOV D10,R2,R2 \n"
|
---|
| 643 | " VMOV D11,R2,R2 \n"
|
---|
| 644 | " VMOV D12,R2,R2 \n"
|
---|
| 645 | " VMOV D13,R2,R2 \n"
|
---|
| 646 | " VMOV D14,R2,R2 \n"
|
---|
| 647 | " VMOV D15,R2,R2 \n"
|
---|
| 648 |
|
---|
| 649 | #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
|
---|
| 650 | //Initialise D32 registers to 0
|
---|
| 651 | " VMOV D16,R2,R2 \n"
|
---|
| 652 | " VMOV D17,R2,R2 \n"
|
---|
| 653 | " VMOV D18,R2,R2 \n"
|
---|
| 654 | " VMOV D19,R2,R2 \n"
|
---|
| 655 | " VMOV D20,R2,R2 \n"
|
---|
| 656 | " VMOV D21,R2,R2 \n"
|
---|
| 657 | " VMOV D22,R2,R2 \n"
|
---|
| 658 | " VMOV D23,R2,R2 \n"
|
---|
| 659 | " VMOV D24,R2,R2 \n"
|
---|
| 660 | " VMOV D25,R2,R2 \n"
|
---|
| 661 | " VMOV D26,R2,R2 \n"
|
---|
| 662 | " VMOV D27,R2,R2 \n"
|
---|
| 663 | " VMOV D28,R2,R2 \n"
|
---|
| 664 | " VMOV D29,R2,R2 \n"
|
---|
| 665 | " VMOV D30,R2,R2 \n"
|
---|
| 666 | " VMOV D31,R2,R2 \n"
|
---|
| 667 | #endif
|
---|
| 668 |
|
---|
| 669 | //Initialise FPSCR to a known state
|
---|
| 670 | " VMRS R2,FPSCR \n"
|
---|
| 671 | " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
---|
| 672 | " AND R2,R2,R3 \n"
|
---|
| 673 | " VMSR FPSCR,R2 "
|
---|
| 674 | );
|
---|
| 675 | }
|
---|
| 676 |
|
---|
| 677 | #pragma GCC diagnostic pop
|
---|
| 678 |
|
---|
| 679 | #endif /* __CMSIS_GCC_H */
|
---|