1 | /**************************************************************************//**
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2 | * @file cmsis_cp15.h
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3 | * @brief CMSIS compiler specific macros, functions, instructions
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4 | * @version V1.0.1
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5 | * @date 07. Sep 2017
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6 | ******************************************************************************/
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7 | /*
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8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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9 | *
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10 | * SPDX-License-Identifier: Apache-2.0
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11 | *
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12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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13 | * not use this file except in compliance with the License.
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14 | * You may obtain a copy of the License at
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15 | *
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16 | * www.apache.org/licenses/LICENSE-2.0
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17 | *
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18 | * Unless required by applicable law or agreed to in writing, software
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19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 | * See the License for the specific language governing permissions and
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22 | * limitations under the License.
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23 | */
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24 |
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25 | #if defined ( __ICCARM__ )
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26 | #pragma system_include /* treat file as system include file for MISRA check */
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27 | #elif defined (__clang__)
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28 | #pragma clang system_header /* treat file as system include file */
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29 | #endif
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30 |
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31 | #ifndef __CMSIS_CP15_H
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32 | #define __CMSIS_CP15_H
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33 |
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34 | /** \brief Get ACTLR
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35 | \return Auxiliary Control register value
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36 | */
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37 | __STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
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38 | {
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39 | uint32_t result;
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40 | __get_CP(15, 0, result, 1, 0, 1);
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41 | return(result);
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42 | }
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43 |
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44 | /** \brief Set ACTLR
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45 | \param [in] actlr Auxiliary Control value to set
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46 | */
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47 | __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
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48 | {
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49 | __set_CP(15, 0, actlr, 1, 0, 1);
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50 | }
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51 |
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52 | /** \brief Get CPACR
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53 | \return Coprocessor Access Control register value
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54 | */
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55 | __STATIC_FORCEINLINE uint32_t __get_CPACR(void)
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56 | {
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57 | uint32_t result;
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58 | __get_CP(15, 0, result, 1, 0, 2);
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59 | return result;
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60 | }
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61 |
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62 | /** \brief Set CPACR
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63 | \param [in] cpacr Coprocessor Access Control value to set
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64 | */
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65 | __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
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66 | {
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67 | __set_CP(15, 0, cpacr, 1, 0, 2);
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68 | }
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69 |
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70 | /** \brief Get DFSR
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71 | \return Data Fault Status Register value
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72 | */
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73 | __STATIC_FORCEINLINE uint32_t __get_DFSR(void)
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74 | {
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75 | uint32_t result;
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76 | __get_CP(15, 0, result, 5, 0, 0);
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77 | return result;
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78 | }
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79 |
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80 | /** \brief Set DFSR
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81 | \param [in] dfsr Data Fault Status value to set
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82 | */
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83 | __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
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84 | {
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85 | __set_CP(15, 0, dfsr, 5, 0, 0);
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86 | }
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87 |
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88 | /** \brief Get IFSR
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89 | \return Instruction Fault Status Register value
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90 | */
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91 | __STATIC_FORCEINLINE uint32_t __get_IFSR(void)
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92 | {
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93 | uint32_t result;
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94 | __get_CP(15, 0, result, 5, 0, 1);
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95 | return result;
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96 | }
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97 |
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98 | /** \brief Set IFSR
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99 | \param [in] ifsr Instruction Fault Status value to set
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100 | */
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101 | __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
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102 | {
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103 | __set_CP(15, 0, ifsr, 5, 0, 1);
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104 | }
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105 |
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106 | /** \brief Get ISR
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107 | \return Interrupt Status Register value
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108 | */
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109 | __STATIC_FORCEINLINE uint32_t __get_ISR(void)
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110 | {
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111 | uint32_t result;
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112 | __get_CP(15, 0, result, 12, 1, 0);
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113 | return result;
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114 | }
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115 |
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116 | /** \brief Get CBAR
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117 | \return Configuration Base Address register value
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118 | */
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119 | __STATIC_FORCEINLINE uint32_t __get_CBAR(void)
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120 | {
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121 | uint32_t result;
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122 | __get_CP(15, 4, result, 15, 0, 0);
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123 | return result;
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124 | }
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125 |
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126 | /** \brief Get TTBR0
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127 |
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128 | This function returns the value of the Translation Table Base Register 0.
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129 |
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130 | \return Translation Table Base Register 0 value
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131 | */
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132 | __STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
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133 | {
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134 | uint32_t result;
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135 | __get_CP(15, 0, result, 2, 0, 0);
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136 | return result;
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137 | }
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138 |
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139 | /** \brief Set TTBR0
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140 |
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141 | This function assigns the given value to the Translation Table Base Register 0.
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142 |
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143 | \param [in] ttbr0 Translation Table Base Register 0 value to set
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144 | */
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145 | __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
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146 | {
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147 | __set_CP(15, 0, ttbr0, 2, 0, 0);
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148 | }
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149 |
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150 | /** \brief Get DACR
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151 |
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152 | This function returns the value of the Domain Access Control Register.
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153 |
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154 | \return Domain Access Control Register value
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155 | */
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156 | __STATIC_FORCEINLINE uint32_t __get_DACR(void)
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157 | {
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158 | uint32_t result;
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159 | __get_CP(15, 0, result, 3, 0, 0);
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160 | return result;
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161 | }
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162 |
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163 | /** \brief Set DACR
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164 |
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165 | This function assigns the given value to the Domain Access Control Register.
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166 |
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167 | \param [in] dacr Domain Access Control Register value to set
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168 | */
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169 | __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
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170 | {
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171 | __set_CP(15, 0, dacr, 3, 0, 0);
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172 | }
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173 |
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174 | /** \brief Set SCTLR
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175 |
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176 | This function assigns the given value to the System Control Register.
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177 |
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178 | \param [in] sctlr System Control Register value to set
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179 | */
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180 | __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
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181 | {
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182 | __set_CP(15, 0, sctlr, 1, 0, 0);
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183 | }
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184 |
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185 | /** \brief Get SCTLR
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186 | \return System Control Register value
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187 | */
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188 | __STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
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189 | {
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190 | uint32_t result;
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191 | __get_CP(15, 0, result, 1, 0, 0);
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192 | return result;
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193 | }
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194 |
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195 | /** \brief Set ACTRL
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196 | \param [in] actrl Auxiliary Control Register value to set
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197 | */
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198 | __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
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199 | {
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200 | __set_CP(15, 0, actrl, 1, 0, 1);
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201 | }
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202 |
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203 | /** \brief Get ACTRL
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204 | \return Auxiliary Control Register value
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205 | */
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206 | __STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
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207 | {
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208 | uint32_t result;
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209 | __get_CP(15, 0, result, 1, 0, 1);
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210 | return result;
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211 | }
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212 |
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213 | /** \brief Get MPIDR
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214 |
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215 | This function returns the value of the Multiprocessor Affinity Register.
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216 |
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217 | \return Multiprocessor Affinity Register value
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218 | */
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219 | __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
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220 | {
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221 | uint32_t result;
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222 | __get_CP(15, 0, result, 0, 0, 5);
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223 | return result;
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224 | }
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225 |
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226 | /** \brief Get VBAR
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227 |
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228 | This function returns the value of the Vector Base Address Register.
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229 |
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230 | \return Vector Base Address Register
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231 | */
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232 | __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
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233 | {
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234 | uint32_t result;
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235 | __get_CP(15, 0, result, 12, 0, 0);
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236 | return result;
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237 | }
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238 |
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239 | /** \brief Set VBAR
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240 |
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241 | This function assigns the given value to the Vector Base Address Register.
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242 |
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243 | \param [in] vbar Vector Base Address Register value to set
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244 | */
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245 | __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
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246 | {
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247 | __set_CP(15, 0, vbar, 12, 0, 0);
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248 | }
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249 |
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250 | /** \brief Get MVBAR
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251 |
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252 | This function returns the value of the Monitor Vector Base Address Register.
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253 |
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254 | \return Monitor Vector Base Address Register
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255 | */
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256 | __STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
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257 | {
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258 | uint32_t result;
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259 | __get_CP(15, 0, result, 12, 0, 1);
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260 | return result;
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261 | }
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262 |
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263 | /** \brief Set MVBAR
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264 |
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265 | This function assigns the given value to the Monitor Vector Base Address Register.
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266 |
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267 | \param [in] mvbar Monitor Vector Base Address Register value to set
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268 | */
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269 | __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
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270 | {
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271 | __set_CP(15, 0, mvbar, 12, 0, 1);
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272 | }
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273 |
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274 | #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
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275 | defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
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276 | defined(DOXYGEN)
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277 |
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278 | /** \brief Set CNTFRQ
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279 |
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280 | This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
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281 |
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282 | \param [in] value CNTFRQ Register value to set
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283 | */
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284 | __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
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285 | {
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286 | __set_CP(15, 0, value, 14, 0, 0);
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287 | }
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288 |
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289 | /** \brief Get CNTFRQ
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290 |
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291 | This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
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292 |
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293 | \return CNTFRQ Register value
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294 | */
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295 | __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
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296 | {
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297 | uint32_t result;
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298 | __get_CP(15, 0, result, 14, 0 , 0);
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299 | return result;
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300 | }
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301 |
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302 | /** \brief Set CNTP_TVAL
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303 |
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304 | This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
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305 |
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306 | \param [in] value CNTP_TVAL Register value to set
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307 | */
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308 | __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
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309 | {
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310 | __set_CP(15, 0, value, 14, 2, 0);
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311 | }
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312 |
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313 | /** \brief Get CNTP_TVAL
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314 |
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315 | This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
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316 |
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317 | \return CNTP_TVAL Register value
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318 | */
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319 | __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
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320 | {
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321 | uint32_t result;
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322 | __get_CP(15, 0, result, 14, 2, 0);
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323 | return result;
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324 | }
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325 |
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326 | /** \brief Get CNTPCT
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327 |
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328 | This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
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329 |
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330 | \return CNTPCT Register value
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331 | */
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332 | __STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
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333 | {
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334 | uint64_t result;
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335 | __get_CP64(15, 0, result, 14);
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336 | return result;
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337 | }
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338 |
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339 | /** \brief Set CNTP_CVAL
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340 |
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341 | This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
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342 |
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343 | \param [in] value CNTP_CVAL Register value to set
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344 | */
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345 | __STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
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346 | {
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347 | __set_CP64(15, 2, value, 14);
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348 | }
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349 |
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350 | /** \brief Get CNTP_CVAL
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351 |
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352 | This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
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353 |
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354 | \return CNTP_CVAL Register value
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355 | */
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356 | __STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
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357 | {
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358 | uint64_t result;
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359 | __get_CP64(15, 2, result, 14);
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360 | return result;
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361 | }
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362 |
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363 | /** \brief Set CNTP_CTL
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364 |
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365 | This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
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366 |
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367 | \param [in] value CNTP_CTL Register value to set
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368 | */
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369 | __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
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370 | {
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371 | __set_CP(15, 0, value, 14, 2, 1);
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372 | }
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373 |
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374 | /** \brief Get CNTP_CTL register
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375 | \return CNTP_CTL Register value
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376 | */
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377 | __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
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378 | {
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379 | uint32_t result;
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380 | __get_CP(15, 0, result, 14, 2, 1);
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381 | return result;
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382 | }
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383 |
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384 | #endif
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385 |
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386 | /** \brief Set TLBIALL
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387 |
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388 | TLB Invalidate All
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389 | */
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390 | __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
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391 | {
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392 | __set_CP(15, 0, value, 8, 7, 0);
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393 | }
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394 |
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395 | /** \brief Set BPIALL.
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396 |
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397 | Branch Predictor Invalidate All
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398 | */
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399 | __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
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400 | {
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401 | __set_CP(15, 0, value, 7, 5, 6);
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402 | }
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403 |
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404 | /** \brief Set ICIALLU
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405 |
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406 | Instruction Cache Invalidate All
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407 | */
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408 | __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
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409 | {
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410 | __set_CP(15, 0, value, 7, 5, 0);
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411 | }
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412 |
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413 | /** \brief Set DCCMVAC
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414 |
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415 | Data cache clean
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416 | */
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417 | __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
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418 | {
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419 | __set_CP(15, 0, value, 7, 10, 1);
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420 | }
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421 |
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422 | /** \brief Set DCIMVAC
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423 |
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424 | Data cache invalidate
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425 | */
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426 | __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
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427 | {
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428 | __set_CP(15, 0, value, 7, 6, 1);
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429 | }
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430 |
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431 | /** \brief Set DCCIMVAC
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432 |
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433 | Data cache clean and invalidate
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434 | */
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435 | __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
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436 | {
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437 | __set_CP(15, 0, value, 7, 14, 1);
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438 | }
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439 |
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440 | /** \brief Set CSSELR
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441 | */
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442 | __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
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443 | {
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444 | // __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
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445 | __set_CP(15, 2, value, 0, 0, 0);
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446 | }
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447 |
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448 | /** \brief Get CSSELR
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449 | \return CSSELR Register value
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450 | */
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451 | __STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
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452 | {
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453 | uint32_t result;
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454 | // __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
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455 | __get_CP(15, 2, result, 0, 0, 0);
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456 | return result;
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457 | }
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458 |
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459 | /** \brief Set CCSIDR
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460 | \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
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461 | */
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462 | CMSIS_DEPRECATED
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463 | __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
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464 | {
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465 | __set_CSSELR(value);
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466 | }
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467 |
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468 | /** \brief Get CCSIDR
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469 | \return CCSIDR Register value
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470 | */
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471 | __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
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472 | {
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473 | uint32_t result;
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474 | // __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
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475 | __get_CP(15, 1, result, 0, 0, 0);
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476 | return result;
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477 | }
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478 |
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479 | /** \brief Get CLIDR
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480 | \return CLIDR Register value
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481 | */
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482 | __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
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483 | {
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484 | uint32_t result;
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485 | // __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
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486 | __get_CP(15, 1, result, 0, 0, 1);
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487 | return result;
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488 | }
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489 |
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490 | /** \brief Set DCISW
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491 | */
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492 | __STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
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493 | {
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494 | // __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
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495 | __set_CP(15, 0, value, 7, 6, 2);
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496 | }
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497 |
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498 | /** \brief Set DCCSW
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499 | */
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500 | __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
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501 | {
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502 | // __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
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503 | __set_CP(15, 0, value, 7, 10, 2);
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504 | }
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505 |
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506 | /** \brief Set DCCISW
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507 | */
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508 | __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
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509 | {
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510 | // __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
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511 | __set_CP(15, 0, value, 7, 14, 2);
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512 | }
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513 |
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514 | #endif
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