[270] | 1 | /*
|
---|
| 2 | * TOPPERS Software
|
---|
| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
|
---|
| 4 | *
|
---|
| 5 | * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
|
---|
| 6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
|
---|
| 7 | *
|
---|
| 8 | * ä¸è¨èä½æ¨©è
|
---|
| 9 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
|
---|
| 10 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
|
---|
| 11 | * å¤ã»åé
|
---|
| 12 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
| 13 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
| 14 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
| 15 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
| 16 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 17 | * ç¨ã§ããå½¢ã§åé
|
---|
| 18 | å¸ããå ´åã«ã¯ï¼åé
|
---|
| 19 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
| 20 | * è
|
---|
| 21 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
| 22 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 23 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 24 | * ç¨ã§ããªãå½¢ã§åé
|
---|
| 25 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
| 26 | * ã¨ï¼
|
---|
| 27 | * (a) åé
|
---|
| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
| 30 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 31 | * (b) åé
|
---|
| 32 | å¸ã®å½¢æ
|
---|
| 33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
| 34 | * å ±åãããã¨ï¼
|
---|
| 35 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
| 36 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 37 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
| 38 | 責ãããã¨ï¼
|
---|
| 39 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
|
---|
| 40 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 41 | ããã³TOPPERSããã¸ã§ã¯ãã
|
---|
| 42 | * å
|
---|
| 43 | 責ãããã¨ï¼
|
---|
| 44 | *
|
---|
| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
| 46 | ã
|
---|
| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
|
---|
| 48 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
|
---|
| 49 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
|
---|
| 50 | * ã®è²¬ä»»ãè² ããªãï¼
|
---|
| 51 | *
|
---|
| 52 | * $Id: rza1.h 270 2017-02-09 04:03:47Z coas-nagasima $
|
---|
| 53 | */
|
---|
| 54 |
|
---|
| 55 | /*
|
---|
| 56 | * RZ/A1ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
|
---|
| 57 | */
|
---|
| 58 |
|
---|
| 59 | #ifndef TOPPERS_RZA1_H
|
---|
| 60 | #define TOPPERS_RZA1_H
|
---|
| 61 |
|
---|
| 62 | #include <sil.h>
|
---|
| 63 |
|
---|
| 64 | /*
|
---|
| 65 | * åãã£ã¹ããè¡ããã¯ãã®å®ç¾©
|
---|
| 66 | */
|
---|
| 67 | #ifndef CAST
|
---|
| 68 | #define CAST(type, val) ((type)(val))
|
---|
| 69 | #endif /* CAST */
|
---|
| 70 |
|
---|
| 71 | /*
|
---|
| 72 | * ã¡ã¢ãªãããã®å®ç¾©ï¼MMUã«è¨å®ããããã«å¿
|
---|
| 73 | è¦ï¼
|
---|
| 74 | */
|
---|
| 75 | #define SPI_ADDR 0x18000000 /* ã·ãªã¢ã«ãã©ãã·ã¥ã¡ã¢ãª */
|
---|
| 76 | #define SPI_SIZE 0x08000000 /* 128MB */
|
---|
| 77 |
|
---|
| 78 | #define SRAM_ADDR 0x20000000 /* å
|
---|
| 79 | èµRAM */
|
---|
| 80 | #ifdef TOPPERS_RZA1H
|
---|
| 81 | #define SRAM_SIZE 0x00a00000 /* 10MB */
|
---|
| 82 | #else /* TOPPERS_RZA1H */
|
---|
| 83 | #define SRAM_SIZE 0x00300000 /* 3MB */
|
---|
| 84 | #endif /* TOPPERS_RZA1H */
|
---|
| 85 |
|
---|
| 86 | #define IO1_ADDR 0x3fe00000 /* I/Oé åï¼äºç´é åãå«ãï¼*/
|
---|
| 87 | #define IO1_SIZE 0x00200000 /* 2MB */
|
---|
| 88 | #define IO2_ADDR 0xe8000000 /* I/Oé åï¼äºç´é åãå«ãï¼*/
|
---|
| 89 | #define IO2_SIZE 0x18000000 /* 384MB */
|
---|
| 90 |
|
---|
| 91 | /*
|
---|
| 92 | * åã¯ããã¯å¨æ³¢æ°ã®å®ç¾©
|
---|
| 93 | */
|
---|
| 94 | #define OSTM_CLK RZA1_CLK_P0
|
---|
| 95 | #define SCIF_CLK RZA1_CLK_P1
|
---|
| 96 |
|
---|
| 97 | /*
|
---|
| 98 | * MPCore Private Memory Regionã®å
|
---|
| 99 | é çªå°
|
---|
| 100 | */
|
---|
| 101 | #define MPCORE_PMR_BASE 0xf0000000
|
---|
| 102 |
|
---|
| 103 | /*
|
---|
| 104 | * GICä¾åé¨ã使ç¨ããããã®å®ç¾©
|
---|
| 105 | */
|
---|
| 106 | #ifndef GIC_TNUM_INTNO
|
---|
| 107 | #ifdef TOPPERS_RZA1H
|
---|
| 108 | #define GIC_TNUM_INTNO UINT_C(587)
|
---|
| 109 | #else /* TOPPERS_RZA1H */
|
---|
| 110 | #define GIC_TNUM_INTNO UINT_C(538)
|
---|
| 111 | #endif /* TOPPERS_RZA1H */
|
---|
| 112 | #endif /* GIC_TNUM_INT */
|
---|
| 113 |
|
---|
| 114 | /*
|
---|
| 115 | * å²è¾¼ã¿ã³ã³ããã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿ï¼RZ/A1åºæã®ãã®ï¼
|
---|
| 116 | */
|
---|
| 117 | #define GICC_BASE 0xe8202000
|
---|
| 118 | #define GICD_BASE 0xe8201000
|
---|
| 119 |
|
---|
| 120 | #define RZA1_ICR0 CAST(uint16_t *, 0xfcfef800)
|
---|
| 121 | #define RZA1_ICR1 CAST(uint16_t *, 0xfcfef802)
|
---|
| 122 | #define RZA1_IRQRR CAST(uint16_t *, 0xfcfef804)
|
---|
| 123 |
|
---|
| 124 | /*
|
---|
| 125 | * OSã¿ã¤ãã®ãã¼ã¹ã¢ãã¬ã¹
|
---|
| 126 | */
|
---|
| 127 | #define OSTM0_BASE 0xfcfec000
|
---|
| 128 | #define OSTM1_BASE 0xfcfec400
|
---|
| 129 |
|
---|
| 130 | /*
|
---|
| 131 | * L2ãã£ãã·ã¥ã³ã³ããã¼ã©ï¼PL310ï¼ã®ãã¼ã¹ã¢ãã¬ã¹
|
---|
| 132 | */
|
---|
| 133 | #define PL310_BASE 0x3ffff000
|
---|
| 134 |
|
---|
| 135 | /*
|
---|
| 136 | * ã¯ããã¯ãã«ã¹ã¸ã§ãã¬ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
|
---|
| 137 | */
|
---|
| 138 | #define RZA1_CPG_BASE 0xfcfe0000
|
---|
| 139 | #define RZA1_FRQCR CAST(uint16_t *, RZA1_CPG_BASE + 0x010)
|
---|
| 140 | #define RZA1_FRQCR2 CAST(uint16_t *, RZA1_CPG_BASE + 0x014)
|
---|
| 141 |
|
---|
| 142 | /*
|
---|
| 143 | * ãã¹ã¹ãã¼ãã³ã³ããã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
|
---|
| 144 | */
|
---|
| 145 | #define RZA1_BSC_BASE 0x3FFFC000
|
---|
| 146 | #define RZA1_CMNCR CAST(uint32_t *, RZA1_BSC_BASE)
|
---|
| 147 | #define RZA1_CS0BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0004)
|
---|
| 148 | #define RZA1_CS1BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0008)
|
---|
| 149 | #define RZA1_CS2BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x000C)
|
---|
| 150 | #define RZA1_CS3BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0010)
|
---|
| 151 | #define RZA1_CS4BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0014)
|
---|
| 152 | #define RZA1_CS5BCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0018)
|
---|
| 153 | #define RZA1_CS0WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0028)
|
---|
| 154 | #define RZA1_CS1WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x002C)
|
---|
| 155 | #define RZA1_CS2WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0030)
|
---|
| 156 | #define RZA1_CS3WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0034)
|
---|
| 157 | #define RZA1_CS4WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x0038)
|
---|
| 158 | #define RZA1_CS5WCR CAST(uint32_t *, RZA1_BSC_BASE + 0x003C)
|
---|
| 159 | #define RZA1_SDCR CAST(uint32_t *, RZA1_BSC_BASE + 0x004C)
|
---|
| 160 | #define RZA1_RTCSR CAST(uint32_t *, RZA1_BSC_BASE + 0x0050)
|
---|
| 161 | #define RZA1_RTCNT CAST(uint32_t *, RZA1_BSC_BASE + 0x0054)
|
---|
| 162 | #define RZA1_RTCOR CAST(uint32_t *, RZA1_BSC_BASE + 0x0058)
|
---|
| 163 |
|
---|
| 164 | /*
|
---|
| 165 | * ã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ã®ãã¼ã¹ã¢ãã¬ã¹
|
---|
| 166 | */
|
---|
| 167 | #define SCIF0_BASE 0xe8007000
|
---|
| 168 | #define SCIF1_BASE 0xe8007800
|
---|
| 169 | #define SCIF2_BASE 0xe8008000
|
---|
| 170 | #define SCIF3_BASE 0xe8008800
|
---|
| 171 | #define SCIF4_BASE 0xe8009000
|
---|
| 172 | #ifdef TOPPERS_RZA1H
|
---|
| 173 | #define SCIF5_BASE 0xe8009800
|
---|
| 174 | #define SCIF6_BASE 0xe800a000
|
---|
| 175 | #define SCIF7_BASE 0xe800a800
|
---|
| 176 | #endif /* TOPPERS_RZA1H */
|
---|
| 177 |
|
---|
| 178 | /*
|
---|
| 179 | * ä½æ¶è²»é»åã¢ã¼ãé¢é£ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
|
---|
| 180 | */
|
---|
| 181 | #define RZA1_LOWPWR_BASE 0xfcfe0000
|
---|
| 182 | #define RZA1_STBCR1 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x020)
|
---|
| 183 | #define RZA1_STBCR2 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x024)
|
---|
| 184 | #define RZA1_STBCR3 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x420)
|
---|
| 185 | #define RZA1_STBCR4 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x424)
|
---|
| 186 | #define RZA1_STBCR5 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x428)
|
---|
| 187 | #define RZA1_STBCR6 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x42C)
|
---|
| 188 | #define RZA1_STBCR7 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x430)
|
---|
| 189 | #define RZA1_STBCR8 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x434)
|
---|
| 190 | #define RZA1_STBCR9 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x438)
|
---|
| 191 | #define RZA1_STBCR10 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x43C)
|
---|
| 192 | #define RZA1_STBCR11 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x440)
|
---|
| 193 | #define RZA1_STBCR12 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x444)
|
---|
| 194 | #define RZA1_STBCR13 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x470)
|
---|
| 195 | #define RZA1_SYSCR1 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x400)
|
---|
| 196 | #define RZA1_SYSCR2 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x404)
|
---|
| 197 | #define RZA1_SYSCR3 CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x408)
|
---|
| 198 | #define RZA1_CPUSTS CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x018)
|
---|
| 199 |
|
---|
| 200 | /*
|
---|
| 201 | * æ±ç¨å
|
---|
| 202 | ¥åºåãã¼ãã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
|
---|
| 203 | */
|
---|
| 204 | #define RZA1_PORT_BASE 0xfcfe3000
|
---|
| 205 | #define RZA1_PORT_P(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0000 + (n)*4))
|
---|
| 206 | #define RZA1_PORT_PSR(n) CAST(uint32_t *, (RZA1_PORT_BASE + 0x0100 + (n)*4))
|
---|
| 207 | #define RZA1_PORT_PPR(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0200 + (n)*4))
|
---|
| 208 | #define RZA1_PORT_PM(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0300 + (n)*4))
|
---|
| 209 | #define RZA1_PORT_PMC(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0400 + (n)*4))
|
---|
| 210 | #define RZA1_PORT_PFC(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0500 + (n)*4))
|
---|
| 211 | #define RZA1_PORT_PFCE(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0600 + (n)*4))
|
---|
| 212 | #define RZA1_PORT_PFCAE(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x0a00 + (n)*4))
|
---|
| 213 | #define RZA1_PORT_PIBC(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x4000 + (n)*4))
|
---|
| 214 | #define RZA1_PORT_PBDC(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x4100 + (n)*4))
|
---|
| 215 | #define RZA1_PORT_PIPC(n) CAST(uint16_t *, (RZA1_PORT_BASE + 0x4200 + (n)*4))
|
---|
| 216 |
|
---|
| 217 | /*
|
---|
| 218 | * å²è¾¼ã¿çªå·
|
---|
| 219 | */
|
---|
| 220 | #define INTNO_IRQ0 32 /* IRQ0 */
|
---|
| 221 | #define INTNO_IRQ1 33 /* IRQ1 */
|
---|
| 222 | #define INTNO_IRQ2 34 /* IRQ2 */
|
---|
| 223 | #define INTNO_IRQ3 35 /* IRQ3 */
|
---|
| 224 | #define INTNO_IRQ4 36 /* IRQ4 */
|
---|
| 225 | #define INTNO_IRQ5 37 /* IRQ5 */
|
---|
| 226 | #define INTNO_IRQ6 38 /* IRQ6 */
|
---|
| 227 | #define INTNO_IRQ7 39 /* IRQ7 */
|
---|
| 228 | #define INTNO_OSTM0 134 /* OSã¿ã¤ã0 */
|
---|
| 229 | #define INTNO_OSTM1 135 /* OSã¿ã¤ã1 */
|
---|
| 230 | #define INTNO_SCIF0_BRI 221 /* SCIF0 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 231 | #define INTNO_SCIF0_ERI 222 /* SCIF0 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 232 | #define INTNO_SCIF0_RXI 223 /* SCIF0 åä¿¡å²è¾¼ã¿ */
|
---|
| 233 | #define INTNO_SCIF0_TXI 224 /* SCIF0 éä¿¡å²è¾¼ã¿ */
|
---|
| 234 | #define INTNO_SCIF1_BRI 225 /* SCIF1 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 235 | #define INTNO_SCIF1_ERI 226 /* SCIF1 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 236 | #define INTNO_SCIF1_RXI 227 /* SCIF1 åä¿¡å²è¾¼ã¿ */
|
---|
| 237 | #define INTNO_SCIF1_TXI 228 /* SCIF1 éä¿¡å²è¾¼ã¿ */
|
---|
| 238 | #define INTNO_SCIF2_BRI 229 /* SCIF2 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 239 | #define INTNO_SCIF2_ERI 230 /* SCIF2 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 240 | #define INTNO_SCIF2_RXI 231 /* SCIF2 åä¿¡å²è¾¼ã¿ */
|
---|
| 241 | #define INTNO_SCIF2_TXI 232 /* SCIF2 éä¿¡å²è¾¼ã¿ */
|
---|
| 242 | #define INTNO_SCIF3_BRI 233 /* SCIF3 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 243 | #define INTNO_SCIF3_ERI 234 /* SCIF3 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 244 | #define INTNO_SCIF3_RXI 235 /* SCIF3 åä¿¡å²è¾¼ã¿ */
|
---|
| 245 | #define INTNO_SCIF3_TXI 236 /* SCIF3 éä¿¡å²è¾¼ã¿ */
|
---|
| 246 | #define INTNO_SCIF4_BRI 237 /* SCIF4 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 247 | #define INTNO_SCIF4_ERI 238 /* SCIF4 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 248 | #define INTNO_SCIF4_RXI 239 /* SCIF4 åä¿¡å²è¾¼ã¿ */
|
---|
| 249 | #define INTNO_SCIF4_TXI 240 /* SCIF4 éä¿¡å²è¾¼ã¿ */
|
---|
| 250 | #ifdef TOPPERS_RZA1H
|
---|
| 251 | #define INTNO_SCIF5_BRI 241 /* SCIF5 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 252 | #define INTNO_SCIF5_ERI 242 /* SCIF5 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 253 | #define INTNO_SCIF5_RXI 243 /* SCIF5 åä¿¡å²è¾¼ã¿ */
|
---|
| 254 | #define INTNO_SCIF5_TXI 244 /* SCIF5 éä¿¡å²è¾¼ã¿ */
|
---|
| 255 | #define INTNO_SCIF6_BRI 245 /* SCIF6 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 256 | #define INTNO_SCIF6_ERI 246 /* SCIF6 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 257 | #define INTNO_SCIF6_RXI 247 /* SCIF6 åä¿¡å²è¾¼ã¿ */
|
---|
| 258 | #define INTNO_SCIF6_TXI 248 /* SCIF6 éä¿¡å²è¾¼ã¿ */
|
---|
| 259 | #define INTNO_SCIF7_BRI 249 /* SCIF7 ãã¬ã¼ã¯å²è¾¼ã¿ */
|
---|
| 260 | #define INTNO_SCIF7_ERI 250 /* SCIF7 ã¨ã©ã¼å²è¾¼ã¿ */
|
---|
| 261 | #define INTNO_SCIF7_RXI 251 /* SCIF7 åä¿¡å²è¾¼ã¿ */
|
---|
| 262 | #define INTNO_SCIF7_TXI 252 /* SCIF7 éä¿¡å²è¾¼ã¿ */
|
---|
| 263 | #endif /* TOPPERS_RZA1H */
|
---|
| 264 |
|
---|
| 265 | #ifndef TOPPERS_MACRO_ONLY
|
---|
| 266 |
|
---|
| 267 | /*
|
---|
| 268 | * IRQå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
|
---|
| 269 | */
|
---|
| 270 | Inline void
|
---|
| 271 | rza1_clear_irq(INTNO intno)
|
---|
| 272 | {
|
---|
| 273 | uint16_t reg;
|
---|
| 274 |
|
---|
| 275 | reg = sil_reh_mem(RZA1_IRQRR);
|
---|
| 276 | reg &= ~(0x01U << (intno - INTNO_IRQ0));
|
---|
| 277 | sil_wrh_mem(RZA1_IRQRR, reg);
|
---|
| 278 | }
|
---|
| 279 |
|
---|
| 280 | /*
|
---|
| 281 | * æ±ç¨å
|
---|
| 282 | ¥åºåãã¼ãã®è¨å®
|
---|
| 283 | *
|
---|
| 284 | * æ±ç¨å
|
---|
| 285 | ¥åºåãã¼ãã®å¶å¾¡ã¬ã¸ã¹ã¿ã®ç¹å®ã®ããããï¼ã»ããï¼setã0ã§ãª
|
---|
| 286 | * ãæï¼ã¾ãã¯ã¯ãªã¢ï¼setã0ã®æï¼ããï¼
|
---|
| 287 | */
|
---|
| 288 | Inline void
|
---|
| 289 | rza1_config_port(uint16_t *reg, uint_t bit, uint_t set)
|
---|
| 290 | {
|
---|
| 291 | uint16_t val;
|
---|
| 292 | uint16_t mask;
|
---|
| 293 |
|
---|
| 294 | mask = 0x01U << bit;
|
---|
| 295 | val = sil_reh_mem(reg);
|
---|
| 296 | if (set == 0) {
|
---|
| 297 | val &= ~mask;
|
---|
| 298 | }
|
---|
| 299 | else {
|
---|
| 300 | val |= mask;
|
---|
| 301 | }
|
---|
| 302 | sil_wrh_mem(reg, val);
|
---|
| 303 | }
|
---|
| 304 |
|
---|
| 305 | #endif /* TOPPERS_MACRO_ONLY */
|
---|
| 306 | #endif /* TOPPERS_RZA1_H */
|
---|