[270] | 1 | /*
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| 2 | * TOPPERS Software
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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| 4 | *
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| 5 | * Copyright (C) 2006-2015 by Embedded and Real-Time Systems Laboratory
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| 6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 7 | *
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| 8 | * ä¸è¨èä½æ¨©è
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| 9 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 10 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 11 | * å¤ã»åé
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| 12 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 13 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 14 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 15 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 16 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 17 | * ç¨ã§ããå½¢ã§åé
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| 18 | å¸ããå ´åã«ã¯ï¼åé
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| 19 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 20 | * è
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| 21 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 22 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 23 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 24 | * ç¨ã§ããªãå½¢ã§åé
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| 25 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 26 | * ã¨ï¼
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| 27 | * (a) åé
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| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 30 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (b) åé
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| 32 | å¸ã®å½¢æ
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| 33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 34 | * å ±åãããã¨ï¼
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| 35 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 36 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 37 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 38 | 責ãããã¨ï¼
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| 39 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 40 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 42 | * å
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| 43 | 責ãããã¨ï¼
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| 44 | *
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| 45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 46 | ã
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| 47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 48 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 49 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 50 | * ã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * $Id: arm.c 270 2017-02-09 04:03:47Z coas-nagasima $
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * ARMã³ã¢ãµãã¼ãã¢ã¸ã¥ã¼ã«
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| 57 | */
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| 58 |
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| 59 | #include "arm.h"
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| 60 |
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| 61 | /*
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| 62 | * ãã£ãã·ã¥ã®æä½
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| 63 | */
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| 64 |
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| 65 | /*
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| 66 | * ãã¼ã¿ãã£ãã·ã¥ã®ã¤ãã¼ãã«
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| 67 | */
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| 68 | void
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| 69 | arm_enable_dcache(void)
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| 70 | {
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| 71 | uint32_t reg;
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| 72 |
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| 73 | CP15_READ_SCTLR(reg);
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| 74 | if ((reg & CP15_SCTLR_DCACHE) == 0U) {
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| 75 | arm_invalidate_dcache();
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| 76 |
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| 77 | reg |= CP15_SCTLR_DCACHE;
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| 78 | CP15_WRITE_SCTLR(reg);
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| 79 | }
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| 80 | }
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| 81 |
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| 82 | /*
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| 83 | * ãã¼ã¿ãã£ãã·ã¥ã®ãã£ã¹ã¨ã¼ãã«
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| 84 | *
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| 85 | * ãã¼ã¿ãã£ãã·ã¥ãç¡å¹ãªç¶æ
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| 86 | ã§clean_and_invalidateãå®è¡ããã¨æ´èµ°
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| 87 | * ããå ´åãããããï¼ãã¼ã¿ãã£ãã·ã¥ã®ç¶æ
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| 88 | ãå¤æãã¦ï¼ç¡å¹ãªå ´åã¯ï¼
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| 89 | * ç¡å¹åã®ã¿ãè¡ãï¼
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| 90 | */
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| 91 | void
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| 92 | arm_disable_dcache(void)
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| 93 | {
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| 94 | uint32_t reg;
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| 95 |
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| 96 | CP15_READ_SCTLR(reg);
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| 97 | if ((reg & CP15_SCTLR_DCACHE) == 0U) {
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| 98 | arm_invalidate_dcache();
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| 99 | }
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| 100 | else {
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| 101 | reg &= ~CP15_SCTLR_DCACHE;
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| 102 | CP15_WRITE_SCTLR(reg);
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| 103 |
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| 104 | arm_clean_and_invalidate_dcache();
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| 105 | }
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| 106 | }
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| 107 |
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| 108 | /*
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| 109 | * å½ä»¤ãã£ãã·ã¥ã®ã¤ãã¼ãã«
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| 110 | */
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| 111 | void
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| 112 | arm_enable_icache(void)
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| 113 | {
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| 114 | uint32_t reg;
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| 115 |
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| 116 | CP15_READ_SCTLR(reg);
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| 117 | if ((reg & CP15_SCTLR_ICACHE) == 0U) {
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| 118 | arm_invalidate_icache();
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| 119 |
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| 120 | reg |= CP15_SCTLR_ICACHE;
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| 121 | CP15_WRITE_SCTLR(reg);
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| 122 | }
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| 123 | }
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| 124 |
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| 125 | /*
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| 126 | * å½ä»¤ãã£ãã·ã¥ã®ãã£ã¹ã¨ã¼ãã«
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| 127 | */
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| 128 | void
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| 129 | arm_disable_icache(void)
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| 130 | {
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| 131 | uint32_t reg;
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| 132 |
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| 133 | CP15_READ_SCTLR(reg);
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| 134 | reg &= ~CP15_SCTLR_ICACHE;
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| 135 | CP15_WRITE_SCTLR(reg);
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| 136 |
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| 137 | arm_invalidate_icache();
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| 138 | }
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| 139 |
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| 140 | /*
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| 141 | * ARMv5ã«ããããã¼ã¿ãã£ãã·ã¥ã®ã¯ãªã¼ã³ã¨ç¡å¹å
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| 142 | */
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| 143 | #if __TARGET_ARCH_ARM <= 5
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| 144 |
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| 145 | void
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| 146 | armv5_clean_and_invalidate_dcache(void)
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| 147 | {
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| 148 | ARMV5_CLEAN_AND_INVALIDATE_DCACHE();
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| 149 | }
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| 150 |
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| 151 | #endif /* __TARGET_ARCH_ARM <= 5 */
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| 152 |
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| 153 | /*
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| 154 | * ARMv7ã«ããããã¼ã¿ãã£ãã·ã¥ã®ç¡å¹å
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| 155 | *
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| 156 | * ã¬ãã«0ã®ãã£ãã·ã¥ã®ã¿ãç¡å¹åããï¼
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| 157 | */
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| 158 | #if __TARGET_ARCH_ARM == 7
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| 159 |
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| 160 | void
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| 161 | armv7_invalidate_dcache(void)
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| 162 | {
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| 163 | uint32_t reg;
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| 164 | uint32_t way, no_ways, shift_way;
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| 165 | uint32_t set, no_sets, shift_set;
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| 166 |
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| 167 | CP15_WRITE_CSSELR(0U);
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| 168 | CP15_READ_CCSIDR(reg);
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| 169 | no_sets = ((reg >> 13) & 0x7fffU) + 1;
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| 170 | shift_set = (reg & 0x07U) + 4;
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| 171 | no_ways = ((reg >> 3) & 0x3ffU) + 1;
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| 172 | shift_way = count_leading_zero(no_ways);
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| 173 |
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| 174 | for (way = 0; way < no_ways; way++){
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| 175 | for (set = 0; set < no_sets; set++) {
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| 176 | reg = (way << shift_way) | (set << shift_set);
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| 177 | CP15_WRITE_DCISW(reg);
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| 178 | }
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| 179 | }
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| 180 | }
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| 181 |
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| 182 | #endif /* __TARGET_ARCH_ARM == 7 */
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| 183 |
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| 184 | /*
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| 185 | * ARMv7ã«ããããã¼ã¿ãã£ãã·ã¥ã®ã¯ãªã¼ã³ã¨ç¡å¹å
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| 186 | *
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| 187 | * ã¬ãã«0ã®ãã£ãã·ã¥ã®ã¿ãã¯ãªã¼ã³ã¨ç¡å¹åããï¼
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| 188 | */
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| 189 | #if __TARGET_ARCH_ARM == 7
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| 190 |
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| 191 | void
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| 192 | armv7_clean_and_invalidate_dcache(void)
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| 193 | {
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| 194 | uint32_t reg;
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| 195 | uint32_t way, no_ways, shift_way;
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| 196 | uint32_t set, no_sets, shift_set;
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| 197 |
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| 198 | CP15_WRITE_CSSELR(0U);
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| 199 | CP15_READ_CCSIDR(reg);
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| 200 | no_sets = ((reg >> 13) & 0x7fffU) + 1;
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| 201 | shift_set = (reg & 0x07U) + 4;
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| 202 | no_ways = ((reg >> 3) & 0x3ffU) + 1;
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| 203 | shift_way = count_leading_zero(no_ways);
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| 204 |
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| 205 | for (way = 0; way < no_ways; way++){
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| 206 | for (set = 0; set < no_sets; set++) {
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| 207 | reg = (way << shift_way) | (set << shift_set);
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| 208 | CP15_WRITE_DCCISW(reg);
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| 209 | }
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| 210 | }
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| 211 | }
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| 212 |
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| 213 | #endif /* __TARGET_ARCH_ARM == 7 */
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