15 | | ||= API =||= ID[[BR]][Dec] =||= ID[[BR]][Hex] =|| |
16 | | || [#Rte_Ports Rte_Ports] || 16|| 0x10|| |
17 | | || [#Rte_NPorts Rte_NPorts] || 17|| 0x11|| |
18 | | || [#Rte_Port Rte_Port] || 18|| 0x12|| |
19 | | || [#Rte_Send Rte_Send] || 19|| 0x13|| |
20 | | || [#Rte_Write Rte_Write] || 20|| 0x14|| |
21 | | || [#Rte_Switch Rte_Switch] || 21|| 0x15|| |
22 | | || [#Rte_Invalidate Rte_Invalidate] || 22|| 0x16|| |
23 | | || [#Rte_Feedback Rte_Feedback] || 23|| 0x17|| |
24 | | || [#Rte_SwitchAck Rte_SwitchAck] || 24|| 0x18|| |
25 | | || [#Rte_Read Rte_Read] || 25|| 0x19|| |
26 | | || [#Rte_DRead Rte_DRead] || 26|| 0x1A|| |
27 | | || [#Rte_Receive Rte_Receive] || 27|| 0x1B|| |
28 | | || [#Rte_Call Rte_Call] || 28|| 0x1C|| |
29 | | || [#Rte_Result Rte_Result] || 29|| 0x1D|| |
30 | | || [#Rte_Pim Rte_Pim] || 30|| 0x1E|| |
31 | | || [#Rte_CData Rte_CData] || 31|| 0x1F|| |
32 | | || [#Rte_Prm Rte_Prm] || 32|| 0x20|| |
33 | | || [#Rte_IRead Rte_IRead] || 33|| 0x21|| |
34 | | || [#Rte_IWrite Rte_IWrite] || 34|| 0x22|| |
35 | | || [#Rte_IWriteRef Rte_IWriteRef] || 35|| 0x23|| |
36 | | || [#Rte_IInvalidate Rte_IInvalidate] || 36|| 0x24|| |
37 | | || [#Rte_IStatus Rte_IStatus] || 37|| 0x25|| |
38 | | || [#Rte_IrvIRead Rte_IrvIRead] || 38|| 0x26|| |
39 | | || [#Rte_IrvIWrite Rte_IrvIWrite] || 39|| 0x27|| |
40 | | || [#Rte_IrvRead Rte_IrvRead] || 40|| 0x28|| |
41 | | || [#Rte_IrvWrite Rte_IrvWrite] || 41|| 0x29|| |
42 | | || [#Rte_Enter Rte_Enter] || 42|| 0x2A|| |
43 | | || [#Rte_Exit Rte_Exit] || 43|| 0x2B|| |
44 | | || [#Rte_Mode Rte_Mode] || 44|| 0x2C|| |
45 | | || [#Rte_Trigger Rte_Trigger] || 45|| 0x2D|| |
46 | | || [#Rte_IrTrigger Rte_IrTrigger] || 46|| 0x2E|| |
47 | | || [#Rte_IFeedback Rte_IFeedback] || 47|| 0x2F|| |
48 | | || [#Rte_IsUpdated Rte_IsUpdated] || 48|| 0x30|| |
49 | | || [#Rte_Start Rte_Start] || 112|| 0x70|| |
50 | | || [#Rte_Stop Rte_Stop] || 113|| 0x71|| |
51 | | || [#Rte_PartitionTerminated Rte_PartitionTerminated] || 114|| 0x72|| |
52 | | || [#Rte_PartitionRestarting Rte_PartitionRestarting] || 115|| 0x73|| |
53 | | || [#Rte_RestartPartition Rte_RestartPartition] || 116|| 0x74|| |
54 | | |
55 | | * コンフィギュレーション一覧 |
56 | | * [#RteGeneration RteGeneration] |
57 | | * [#RteCalibrationSupport RteCalibrationSupport] |
58 | | * [#RteCodeVendorId RteCodeVendorId] |
59 | | * [#RteDevErrorDetect RteDevErrorDetect] |
60 | | * [#RteDevErrorDetectUninit RteDevErrorDetectUninit] |
61 | | * [#RteGenerationMode RteGenerationMode] |
62 | | * [#RteIocInteractionReturnValue RteIocInteractionReturnValue] |
63 | | * [#RteMeasurementSupport RteMeasurementSupport] |
64 | | * [#RteOptimizationMode RteOptimizationMode] |
65 | | * [#RteToolChainSignificantCharacters RteToolChainSignificantCharacters] |
66 | | * [#RteValueRangeCheckEnabled RteValueRangeCheckEnabled] |
67 | | * [#RteVfbTraceClientPrefix RteVfbTraceClientPrefix] |
68 | | * [#RteVfbTraceEnabled RteVfbTraceEnabled] |
69 | | * [#RteVfbTraceFunction RteVfbTraceFunction] |
70 | | * [#RteImplicitCommunication RteImplicitCommunication] |
71 | | * [#RteCoherentAccess RteCoherentAccess] |
72 | | * [#RteImmediateBufferUpdate RteImmediateBufferUpdate] |
73 | | * [#RteVariableReadAccessRef RteVariableReadAccessRef] |
74 | | * [#RteVariableWriteAccessRef RteVariableWriteAccessRef] |
75 | | * [#RteSoftwareComponentInstanceRef RteSoftwareComponentInstanceRef] |
76 | | * [#RteInitializationBehavior RteInitializationBehavior] |
77 | | * [#RteInitializationStrategy RteInitializationStrategy] |
78 | | * [#RteSectionInitializationPolicy RteSectionInitializationPolicy] |
79 | | * [#RteOsInteraction RteOsInteraction] |
80 | | * [#RteModeToScheduleTableMapping RteModeToScheduleTableMapping] |
81 | | * [#RteModeScheduleTableRef RteModeScheduleTableRef] |
82 | | * [#RteModeSchtblMapModeDeclarationRef RteModeSchtblMapModeDeclarationRef] |
83 | | * [#RteModeSchtblMapBsw RteModeSchtblMapBsw] |
84 | | * [#RteModeSchtblMapBswInstanceRef RteModeSchtblMapBswInstanceRef] |
85 | | * [#RteModeSchtblMapBswProvidedModeGroupRef RteModeSchtblMapBswProvidedModeGroupRef] |
86 | | * [#RteModeSchtblMapSwc RteModeSchtblMapSwc] |
87 | | * [#RteModeSchtblMapSwcInstanceRef RteModeSchtblMapSwcInstanceRef] |
88 | | * [#RteModeSchtblMapSwcPortRef RteModeSchtblMapSwcPortRef] |
89 | | * [#RteUsedOsActivation RteUsedOsActivation] |
90 | | * [#RteExpectedActivationOffset RteExpectedActivationOffset] |
91 | | * [#RteExpectedTickDuration RteExpectedTickDuration] |
92 | | * [#RteActivationOsAlarmRef RteActivationOsAlarmRef] |
93 | | * [#RteActivationOsSchTblRef RteActivationOsSchTblRef] |
94 | | * [#RteActivationOsTaskRef RteActivationOsTaskRef] |
95 | | * [#RtePostBuildVariantConfiguration RtePostBuildVariantConfiguration] |
96 | | * [#RtePostBuildUsedPredefinedVariant RtePostBuildUsedPredefinedVariant] |
97 | | * [#RteSwComponentInstance RteSwComponentInstance] |
98 | | * [#RteSoftwareComponentInstanceRef RteSoftwareComponentInstanceRef] |
99 | | * [#RteEventToTaskMapping RteEventToTaskMapping] |
100 | | * [#RteActivationOffset RteActivationOffset] |
101 | | * [#RteImmediateRestart RteImmediateRestart] |
102 | | * [#RteOsSchedulePoint RteOsSchedulePoint] |
103 | | * [#RtePositionInTask RtePositionInTask] |
104 | | * [#RteMappedToTaskRef RteMappedToTaskRef] |
105 | | * [#RteUsedOsAlarmRef RteUsedOsAlarmRef] |
106 | | * [#RteUsedOsEventRef RteUsedOsEventRef] |
107 | | * [#RteUsedOsSchTblExpiryPointRef RteUsedOsSchTblExpiryPointRef] |
108 | | * [#RteVirtuallyMappedToTaskRef RteVirtuallyMappedToTaskRef] |
109 | | * [#RteEventRef RteEventRef] |
110 | | * [#RteExclusiveAreaImplementation RteExclusiveAreaImplementation] |
111 | | * [#RteExclusiveAreaImplMechanism RteExclusiveAreaImplMechanism] |
112 | | * [#RteExclusiveAreaOsResourceRef RteExclusiveAreaOsResourceRef] |
113 | | * [#RteExclusiveAreaRef RteExclusiveAreaRef] |
114 | | * [#RteExternalTriggerConfig RteExternalTriggerConfig] |
115 | | * [#RteTriggerSourceQueueLength RteTriggerSourceQueueLength] |
116 | | * [#RteSwcTriggerSourceRef RteSwcTriggerSourceRef] |
117 | | * [#RteInternalTriggerConfig RteInternalTriggerConfig] |
118 | | * [#RteTriggerSourceQueueLength RteTriggerSourceQueueLength] |
119 | | * [#RteSwcTriggerSourceRef RteSwcTriggerSourceRef] |
120 | | * [#RteNvRamAllocation RteNvRamAllocation] |
121 | | * [#RteNvmRamBlockLocationSymbol RteNvmRamBlockLocationSymbol] |
122 | | * [#RteNvmRomBlockLocationSymbol RteNvmRomBlockLocationSymbol] |
123 | | * [#RteSwNvRamMappingRef RteSwNvRamMappingRef] |
124 | | * [#RteNvmBlockRef RteNvmBlockRef] |
125 | | * [#RteSwComponentType RteSwComponentType] |
126 | | * [#RteComponentTypeRef RteComponentTypeRef] |
127 | | * [#RteImplementationRef RteImplementationRef] |
128 | | * [#RteComponentTypeCalibration RteComponentTypeCalibration] |
129 | | * [#RteCalibrationSupportEnabled RteCalibrationSupportEnabled] |
130 | | * [#RteCalibrationSwAddrMethodRef RteCalibrationSwAddrMethodRef] |
| 15 | ||= API =||= ID[[BR]][Dec] =||= ID[[BR]][Hex] =||= R4.0.3 =|| |
| 16 | || [#Rte_Ports Rte_Ports] || 16|| 0x10|| ○ || |
| 17 | || [#Rte_NPorts Rte_NPorts] || 17|| 0x11|| ○ || |
| 18 | || [#Rte_Port Rte_Port] || 18|| 0x12|| ○ || |
| 19 | || [#Rte_Send Rte_Send] || 19|| 0x13|| ○ || |
| 20 | || [#Rte_Write Rte_Write] || 20|| 0x14|| ○ || |
| 21 | || [#Rte_Switch Rte_Switch] || 21|| 0x15|| ○ || |
| 22 | || [#Rte_Invalidate Rte_Invalidate] || 22|| 0x16|| ○ || |
| 23 | || [#Rte_Feedback Rte_Feedback] || 23|| 0x17|| ○ || |
| 24 | || [#Rte_SwitchAck Rte_SwitchAck] || 24|| 0x18|| ○ || |
| 25 | || [#Rte_Read Rte_Read] || 25|| 0x19|| ○ || |
| 26 | || [#Rte_DRead Rte_DRead] || 26|| 0x1A|| ○ || |
| 27 | || [#Rte_Receive Rte_Receive] || 27|| 0x1B|| ○ || |
| 28 | || [#Rte_Call Rte_Call] || 28|| 0x1C|| ○ || |
| 29 | || [#Rte_Result Rte_Result] || 29|| 0x1D|| ○ || |
| 30 | || [#Rte_Pim Rte_Pim] || 30|| 0x1E|| ○ || |
| 31 | || [#Rte_CData Rte_CData] || 31|| 0x1F|| ○ || |
| 32 | || [#Rte_Prm Rte_Prm] || 32|| 0x20|| ○ || |
| 33 | || [#Rte_IRead Rte_IRead] || 33|| 0x21|| ○ || |
| 34 | || [#Rte_IWrite Rte_IWrite] || 34|| 0x22|| ○ || |
| 35 | || [#Rte_IWriteRef Rte_IWriteRef] || 35|| 0x23|| ○ || |
| 36 | || [#Rte_IInvalidate Rte_IInvalidate] || 36|| 0x24|| ○ || |
| 37 | || [#Rte_IStatus Rte_IStatus] || 37|| 0x25|| ○ || |
| 38 | || [#Rte_IrvIRead Rte_IrvIRead] || 38|| 0x26|| ○ || |
| 39 | || [#Rte_IrvIWrite Rte_IrvIWrite] || 39|| 0x27|| ○ || |
| 40 | || [#Rte_IrvRead Rte_IrvRead] || 40|| 0x28|| ○ || |
| 41 | || [#Rte_IrvWrite Rte_IrvWrite] || 41|| 0x29|| ○ || |
| 42 | || [#Rte_Enter Rte_Enter] || 42|| 0x2A|| ○ || |
| 43 | || [#Rte_Exit Rte_Exit] || 43|| 0x2B|| ○ || |
| 44 | || [#Rte_Mode Rte_Mode] || 44|| 0x2C|| ○ || |
| 45 | || [#Rte_Trigger Rte_Trigger] || 45|| 0x2D|| ○ || |
| 46 | || [#Rte_IrTrigger Rte_IrTrigger] || 46|| 0x2E|| ○ || |
| 47 | || [#Rte_IFeedback Rte_IFeedback] || 47|| 0x2F|| ○ || |
| 48 | || [#Rte_IsUpdated Rte_IsUpdated] || 48|| 0x30|| ○ || |
| 49 | || [#Rte_Start Rte_Start] || 112|| 0x70|| ○ || |
| 50 | || [#Rte_Stop Rte_Stop] || 113|| 0x71|| ○ || |
| 51 | || [#Rte_PartitionTerminated Rte_PartitionTerminated] || 114|| 0x72|| ○ || |
| 52 | || [#Rte_PartitionRestarting Rte_PartitionRestarting] || 115|| 0x73|| ○ || |
| 53 | || [#Rte_RestartPartition Rte_RestartPartition] || 116|| 0x74|| ○ || |
| 54 | |
| 55 | * コンフィギュレーション一覧(R4.0.3) |
| 56 | * [#RteGeneration RteGeneration] (○) |
| 57 | * [#RteCalibrationSupport RteCalibrationSupport] (○) |
| 58 | * [#RteCodeVendorId RteCodeVendorId] (○) |
| 59 | * [#RteDevErrorDetect RteDevErrorDetect] (○) |
| 60 | * [#RteDevErrorDetectUninit RteDevErrorDetectUninit] (○) |
| 61 | * [#RteGenerationMode RteGenerationMode] (○) |
| 62 | * [#RteIocInteractionReturnValue RteIocInteractionReturnValue] (○) |
| 63 | * [#RteMeasurementSupport RteMeasurementSupport] (○) |
| 64 | * [#RteOptimizationMode RteOptimizationMode] (○) |
| 65 | * [#RteToolChainSignificantCharacters RteToolChainSignificantCharacters] (○) |
| 66 | * [#RteValueRangeCheckEnabled RteValueRangeCheckEnabled] (○) |
| 67 | * [#RteVfbTraceClientPrefix RteVfbTraceClientPrefix] (○) |
| 68 | * [#RteVfbTraceEnabled RteVfbTraceEnabled] (○) |
| 69 | * [#RteVfbTraceFunction RteVfbTraceFunction] (○) |
| 70 | * [#RteImplicitCommunication RteImplicitCommunication] (○) |
| 71 | * [#RteCoherentAccess RteCoherentAccess] (○) |
| 72 | * [#RteImmediateBufferUpdate RteImmediateBufferUpdate] (○) |
| 73 | * [#RteVariableReadAccessRef RteVariableReadAccessRef] (○) |
| 74 | * [#RteVariableWriteAccessRef RteVariableWriteAccessRef] (○) |
| 75 | * [#RteSoftwareComponentInstanceRef RteSoftwareComponentInstanceRef] (○) |
| 76 | * [#RteInitializationBehavior RteInitializationBehavior] (○) |
| 77 | * [#RteInitializationStrategy RteInitializationStrategy] (○) |
| 78 | * [#RteSectionInitializationPolicy RteSectionInitializationPolicy] (○) |
| 79 | * [#RteOsInteraction RteOsInteraction] (○) |
| 80 | * [#RteModeToScheduleTableMapping RteModeToScheduleTableMapping] (○) |
| 81 | * [#RteModeScheduleTableRef RteModeScheduleTableRef] (○) |
| 82 | * [#RteModeSchtblMapModeDeclarationRef RteModeSchtblMapModeDeclarationRef] (○) |
| 83 | * [#RteModeSchtblMapBsw RteModeSchtblMapBsw] (○) |
| 84 | * [#RteModeSchtblMapBswInstanceRef RteModeSchtblMapBswInstanceRef] (○) |
| 85 | * [#RteModeSchtblMapBswProvidedModeGroupRef RteModeSchtblMapBswProvidedModeGroupRef] (○) |
| 86 | * [#RteModeSchtblMapSwc RteModeSchtblMapSwc] (○) |
| 87 | * [#RteModeSchtblMapSwcInstanceRef RteModeSchtblMapSwcInstanceRef] (○) |
| 88 | * [#RteModeSchtblMapSwcPortRef RteModeSchtblMapSwcPortRef] (○) |
| 89 | * [#RteUsedOsActivation RteUsedOsActivation] (○) |
| 90 | * [#RteExpectedActivationOffset RteExpectedActivationOffset] (○) |
| 91 | * [#RteExpectedTickDuration RteExpectedTickDuration] (○) |
| 92 | * [#RteActivationOsAlarmRef RteActivationOsAlarmRef] (○) |
| 93 | * [#RteActivationOsSchTblRef RteActivationOsSchTblRef] (○) |
| 94 | * [#RteActivationOsTaskRef RteActivationOsTaskRef] (○) |
| 95 | * [#RtePostBuildVariantConfiguration RtePostBuildVariantConfiguration] (○) |
| 96 | * [#RtePostBuildUsedPredefinedVariant RtePostBuildUsedPredefinedVariant] (○) |
| 97 | * [#RteSwComponentInstance RteSwComponentInstance] (○) |
| 98 | * [#RteSoftwareComponentInstanceRef RteSoftwareComponentInstanceRef] (○) |
| 99 | * [#RteEventToTaskMapping RteEventToTaskMapping] (○) |
| 100 | * [#RteActivationOffset RteActivationOffset] (○) |
| 101 | * [#RteImmediateRestart RteImmediateRestart] (○) |
| 102 | * [#RteOsSchedulePoint RteOsSchedulePoint] (○) |
| 103 | * [#RtePositionInTask RtePositionInTask] (○) |
| 104 | * [#RteMappedToTaskRef RteMappedToTaskRef] (○) |
| 105 | * [#RteUsedOsAlarmRef RteUsedOsAlarmRef] (○) |
| 106 | * [#RteUsedOsEventRef RteUsedOsEventRef] (○) |
| 107 | * [#RteUsedOsSchTblExpiryPointRef RteUsedOsSchTblExpiryPointRef] (○) |
| 108 | * [#RteVirtuallyMappedToTaskRef RteVirtuallyMappedToTaskRef] (○) |
| 109 | * [#RteEventRef RteEventRef] (○) |
| 110 | * [#RteExclusiveAreaImplementation RteExclusiveAreaImplementation] (○) |
| 111 | * [#RteExclusiveAreaImplMechanism RteExclusiveAreaImplMechanism] (○) |
| 112 | * [#RteExclusiveAreaOsResourceRef RteExclusiveAreaOsResourceRef] (○) |
| 113 | * [#RteExclusiveAreaRef RteExclusiveAreaRef] (○) |
| 114 | * [#RteExternalTriggerConfig RteExternalTriggerConfig] (○) |
| 115 | * [#RteTriggerSourceQueueLength RteTriggerSourceQueueLength] (○) |
| 116 | * [#RteSwcTriggerSourceRef RteSwcTriggerSourceRef] (○) |
| 117 | * [#RteInternalTriggerConfig RteInternalTriggerConfig] (○) |
| 118 | * [#RteTriggerSourceQueueLength RteTriggerSourceQueueLength] (○) |
| 119 | * [#RteSwcTriggerSourceRef RteSwcTriggerSourceRef] (○) |
| 120 | * [#RteNvRamAllocation RteNvRamAllocation] (○) |
| 121 | * [#RteNvmRamBlockLocationSymbol RteNvmRamBlockLocationSymbol] (○) |
| 122 | * [#RteNvmRomBlockLocationSymbol RteNvmRomBlockLocationSymbol] (○) |
| 123 | * [#RteSwNvRamMappingRef RteSwNvRamMappingRef] (○) |
| 124 | * [#RteNvmBlockRef RteNvmBlockRef] (○) |
| 125 | * [#RteSwComponentType RteSwComponentType] (○) |
| 126 | * [#RteComponentTypeRef RteComponentTypeRef] (○) |
| 127 | * [#RteImplementationRef RteImplementationRef] (○) |
| 128 | * [#RteComponentTypeCalibration RteComponentTypeCalibration] (○) |
| 129 | * [#RteCalibrationSupportEnabled RteCalibrationSupportEnabled] (○) |
| 130 | * [#RteCalibrationSwAddrMethodRef RteCalibrationSwAddrMethodRef] (○) |